The current clock register definition is wrong, which results in wrong
audio sampling rate. Fix it by adjusting the POSTDIV registers of
APLL1-APLL5.
TEST=build pass
BUG=b:250459803, b:250464574
Change-Id: I7a627169593f41906856777d738c6b13ff72d5a0
Signed-off-by: Johnson Wang <johnson.wang@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73134
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
MT8188 supports port0/port1 download. The hardware needs a trapping pin
to select the port to use. When port1 is selected, the phy of port1 will
be switched to port0. That is, port1 connector will be the physical line
of port0. Since port0 phy isn't initialized in coreboot, switch back to
port1 phy.
BUG=b:269059211
TEST=can detect USB2 devices in depthcharge.
Change-Id: Ic97d0bd9d0233883196b2e73ac2a22cd8ea9466b
Signed-off-by: Shaocheng Wang <shaocheng.wang@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73170
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
USB2 port 6 may be used for a PL2303 USB to UART bridge, so enable the
port.
BUG=b:269690930
TEST=kernel can detect a PL2303 USB device
BRANCH=dedede
Change-Id: I0ba421c3a502e69d101de40bbd31122211d3fb05
Signed-off-by: Sam McNally <sammc@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73125
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Add functionality such that the FPMCU is power cycled long enough
on boot to ensure proper reset.
This solution relies solely on coreboot to sequence the power and reset
signals appropriately (150ms on boot).
BUG=b:245954151
TEST=Confirmed FPMCU is still functional on Nami.
Confirmed power is off for 150ms seconds on boot.
Confirmed RCC_CSR of FPMCU indicates power cycle occurred.
Confirmed reset is de-asserted approx 3ms after power application
(target >2.5ms)
Change-Id: I21eb85dc11e0ea0eb5de8a6092b01663d3c3df91
Signed-off-by: Tarun Tuli <taruntuli@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68820
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Phoenix2 VBIOS PCI DID is 15c8 though the VBIOS image uses a different
PCI ID i.e. 0x1205, so we need to implement map_oprom_vendev for the SoC.
Change-Id: I7eef5eb41b781f02abb9dd4098e92a8652a431f5
Signed-off-by: Ritul Guru <ritul.bits@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73122
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
VGA defineds the extended ASCII set based on CP437, but there is a bug
on printing them: in vga_write_at_offset(), we perform a bitwise or
between 'unsigned short' and 'signed char':
```
p[i] = 0x0F00 | string[i];
```
If we want to show an extended ASCII character, string[i] will be
negative and this bitwise operation will fail due to their implicit
casting rule: convert signed char to unsigned short by adding 65536.
To fix this, we need to cast the string to unsigned char manually
somewhere. Since we still want to leverage the built-in string utilities
which only accepts const char*, we still preserve the original
prototypes before, and cast it until we write into the frame buffer.
BRANCH=brya
BUG=b:264666392
TEST=emerge-brya coreboot chromeos-bootimage
and verify drawing characters with code > 127.
Change-Id: I9cd65fe9794e5b0d338147924f28efd27fc8a1e8
Signed-off-by: Hsuan Ting Chen <roccochen@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73090
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Based on product spec v1.4, update T3 timing from 180 ms to 150 ms.
BRANCH=none
BUG=b:262734395
TEST=emerge-skyrim coreboot chromeos-bootimage
Then the Elan touchscreen works fine.
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Change-Id: I0d8f1e008276fccdfbb8c76cfebaccbe71160b64
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73130
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
After first recovery request coreboot would get stuck in bootloop with
VB2_RECOVERY_PREAMBLE as recovery reason due to not checking whether
coreboot is alread in recovery mode, and calling failing code.
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: Idc947a1d150ff6487cf973b36bf4f0af41daa220
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73091
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Package C state demotion is now disabled for all RPL SoCs from within
soc/intel/alderlake/fsp_params, so no need to duplicate that in the
skolas devicetree.cb.
BUG=268296760
BRANCH=firmware-brya-14505.B
TEST=Boot and verified that S0ix issue is resolved.
Change-Id: I1c630e2efbdddd18a5423c79b73269e9b1be79c7
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73074
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
The EFS entry at offset 0x14 can point to either the first level PSP
directory table or to the PSP combo directory structure that was used
before the introduction of the AMD A/B recovery scheme. This scheme is
not to be confused with the VBOOT scheme. The PSP verstage code checks
if the header this entry points to begins with the PSP_COOKIE, which
indicates the entry is a first level PSP directory table. Due to that,
the EFS entry at offset 0x14 is always expected to point to a PSP
directory table, so rename combo_psp_directory to new_psp_directory to
match the actual usage. This EFS entry that points to the PSP directory
table is called new_psp_directory, since the entry at EFS offset 0x10
was used on some early AMD chips to point to the older PSP directory
table and that one is already called psp_directory. amdfwtool uses the
same naming scheme for those two PSP directory table pointers.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I10f19ee63f8d422433dba64402d84fd6bb9e0f9e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73083
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The ctags tool (called by ctags-project target) currently complains
about not finding certain files.
The project_filelist.txt generation includes the compiler
generated "*.d" files, except for files found in build/util. Most file
paths in these "*.d" files are file paths relative to the root
directory of coreboot. Some projects though are compiled separately from
coreboot (e.g. payload, vboot, util). Some of these (e.g. util, vboot)
are also put into the build directory of coreboot and relative file
paths are relative to these projects instead of coreboot. This has the
uncanning side effect that the ctags Makefile target can't find these
files, since they are not relative to the coreboot root directory.
This patch also excludes the build/external directory from those files,
since they contain 'separately' compiled projects like 3rdparty/vboot.
That fixes the ctags-project Makefile target.
Change-Id: I16294171c29a0d5fd25a31018846f1013e130ee0
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71517
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Select NO_S0IX_SUPPORT for `starlabs/starbook` and `atlas/prodrive`
so their configurations are unchanged.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I718952165daa6471f11e8025e745fe7c249d3b46
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72800
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Report `4` in `_S0W` only when D3COLD_SUPPORT is enabled, as if it
is not, it will break S3 exit.
When D3COLD_SUPPORT is not enabled, return `3` (D3Hot).
This fixed S3 exit on both TGL and ADL. Tested on StarBook
Mk V and Mk VI.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I3a4b89132b594ad568a5851137575f921f8e2a2e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72765
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
If BIOS_DONE MSR is supported, set it after ReadyToBoot, because FSP
programs certain registers via Notify phase ReadyToBoot and it cannot
be modified by FSP after coreboot has set BIOS_DONE MSR, therefore we
try to set BIOS_DONE MSR as late as possible to avoid this.
Signed-off-by: Tim Chu <Tim.Chu@quantatw.com>
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Signed-off-by: Jonathan Zhang <jonzhang@meta.com>
Change-Id: I4f19a7c54818231ebbccd2b6f8b23f47b117eb1f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71964
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Add fast_spi_set_vcl() to be called by the SOC lockdown function if SPI
Vendor Specific Component Capabilities are desired.
Change-Id: I6d9b58e90fa16c539b90c6b961862e97e1bf29a2
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72478
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
It is not more necessary to patch binutils, we can
pass an argument during build time to not build docs.
Regenerate binutils-2.37_no-makeinfo.patch.
Change-Id: If600f0bb46db5f84956940683a7adc83eaca01e5
Signed-off-by: Elias Souza <eliascontato@protonmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73115
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Add support for LP5X 8533Mbps in SPD tool.
BUG=b:263189532
TEST=None
Change-Id: I72b02514f68647dda996822f910db8bc93f61ca4
Signed-off-by: Kyle Lin <kylelinck@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73038
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marx Wang <marx.wang@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
To make MIPI/eDP panel functional on unprovisioned devices, it requires
passing SKU ID and panel ID info to the payload(depthcharge) to load the
corresponded device tree for kernel.
BUG=b:247415660
TEST=cbmem -1 |grep "SKU Code".
Change-Id: Id2254729b7bd621d1e9bc520e8f40916d0f81030
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73076
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
This patch adds enable/disable FSP DisableEnergyReport feature
option to be used in devicetree for power instrument purpose.
BUG=None
Branch=None
Test=Build and boot MTL RVP.
Signed-off-by: Yong Zhi <yong.zhi@intel.com>
Change-Id: I58d4aea28ee2561d2ed73260c40cb22ce3fdd135
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73061
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Replace the magic number with the CPUID_FROM_FMS macro to make it easier
to read.
TEST=Resulting image of timeless build for pcengines/apu2 is identical
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I15480dc883b65b5ffaf0cd38cf4e1f7b2222022e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73069
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Instead of having two entries for two different steppings of the same
family and model combination using the CPUID_EXACT_MATCH_MASK, just have
one entry that uses CPUID_ALL_STEPPINGS_MASK to cover all steppings.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I0118bb9b4b0be4d954a657d50789addca08a784e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73068
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The platform supports a discrete LPC TPM module. However, ME firmware
enables PTT by default and descriptor is configured for SPI TPM on the
platform's original firmware. So disabling PTT in ME is not enough,
because it falls back to SPI TPM. Ensure PTT is disabled in ME and SPI
TPM is disabled in descriptor soft straps.
TEST=Boot VP4650 and see LPC TPM is recognized by coreboot.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I3764e085f2eb5ae957b9087d150320def7af4fc6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68920
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Based on product spec v1.4, update T3 timing to 150 ms from 300 ms
BRANCH=none
BUG=b:269041202
TEST=emerge-skyrim coreboot chromeos-bootimage
Then the Elan touchscreen works fine.
Change-Id: Ie5bd4bc2c8be2e43470edd374af0623162067497
Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73067
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Chao Gui <chaogui@google.com>
Some users of MSI Z690-A board reported non-working IGD display
during post using various CPUs. As not all PCI IDs were hooked,
coreboot didn't detect GOP-provided framebuffer nor passed the
framebuffer information to the payload, causing a black screen.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I07584e07182ee56b61b6f751100431589d1cbe83
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70101
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elias Souza <eliascontato@protonmail.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
While the work on updating GCC to version 12 is still WIP, update it
to the latest minor release 11.3.
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Change-Id: I8810bbb238b01985774ff8da1e246ab1b192e663
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70221
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
We can not use 'boolean' since commit 53ea1d44 "util/kconfig: Uprev to Linux 5.13's kconfig".
This also reduce difference with upstream.
Change-Id: Iff9fbde46784547c07726816d2fdd71967e0595e
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71940
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Add NO_S0IX_SUPPORT for boards that do not support, or do not want
to support S0IX.
As all the boards in the tree that do this, don't support D3Cold,
add D3COLD_SUPPORT that defaults to `n` when NO_S0IX_SUPPORT is
selected to disable D3Cold support.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I03378cc7bb76fd65fcec81018e47f6288d437cd8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73042
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Besides crashlog, there's also other errors such as MCA error, which
should be recorded in BERT table. With current code, BERT table is
not generated if crashlog is not enabled. Add if statement for
SOC_INTEL_CRASHLOG so that MCA error can be recorded in BERT table
when crashlog is not supported.
For some server mainboard, crashlog is supported through BMC instead
of host firmware.
Also check if BERT region is generated when crashlog is not enabled.
Change-Id: I323ca889eef2b246fc4e062582d2d11b4213316f
Signed-off-by: Tim Chu <Tim.Chu@quantatw.com>
Signed-off-by: Jonathan Zhang <jonzhang@meta.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68878
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Enable HDA device and update jack codec HID from ALC5682I-VD to
ALC5682I-VS.
BUG=b:268309238
TEST=kernel detects audio DSP and rt5682s
BRANCH=dedede
Change-Id: Icd17d5009ab8ef4711bb6c5fa414a8188fc0912f
Signed-off-by: Sam McNally <sammc@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73057
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
pmc_lock_smi() and pmc_lockdown_config() have PCH specific
implementations. Move them from common lockdown.c and pmc.c
into lbg/soc_pmutil.c.
Move sata_lockdown_config() and spi_lockdown_config() to
lbg/lockdown.c.
While here, fix some coding style issues.
Change-Id: I9b357ce877123530dd5c310a730808b6e651712e
Signed-off-by: Jonathan Zhang <jonzhang@meta.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72396
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Simon Chou <simonchou@supermicro.com.tw>
Reviewed-by: Jian-Ming Wang <jianmingW@supermicro.com>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
BUG=b:265611305
TEST=Reboot test 2500 times pass
Signed-off-by: Chia-Ling Hou <chia-ling.hou@intel.com>
Change-Id: I2b114cac58a7fadeaee6d48996cb8b51f192e78f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73022
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
This patch improves `incomplete` debug messages for missing ACPI
name PCI devices.
Additionally, using the proper PCI device B:D:F to locate the device
with the missing ACPI name.
Finally, modify the msg time from Debug to Warning to make it more
purposeful.
TEST=Able to build and boot google/rex.
Without this patch:
```
[DEBUG] dev->path.devfn=10
[DEBUG] dev->path.devfn=a2
[DEBUG] dev->path.devfn=b0
```
With this patch:
```
[WARN] Missing ACPI Name for PCI: 00:02.0
[WARN] Missing ACPI Name for PCI: 00:14.2
[WARN] Missing ACPI Name for PCI: 00:16.0
```
Change-Id: I605e59de8cbec18c9a56eaa6e90a34f36ea4cdd9
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73072
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Johnson Wang