We still had a lingering reference to the old sabrina codename in the
vendorcode directory. Searching through the code now, the only places
the sabrina codename is seen is in the release notes, as is proper.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I41762880b45a85ce7cd4210b8ce623076d874c06
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68645
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Update generated FSP headers for Alder Lake N from v3301.00 to v3343.04.
Changes include:
- FspsUpd.h: 1. Add PchFivrVccstIccMaxControl UPD
BUG=b:254374913
BRANCH=None
TEST=Build using "emerge-nissa intel-adlnfsp" and boot Nissa.
Change-Id: I20b13d3dff2951e6ec3aa754c8954989a3b4e176
Signed-off-by: Shaik Shahina <shahina.shaik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68424
Reviewed-by: Reka Norman <rekanorman@google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add two new types for MDN DDI descriptor
BUG=b:228284940
TEST=Normal boot and S0i3 cycles
Signed-off-by: Jason Nien <finaljason@gmail.com>
Change-Id: I02793f032f9855dac202a5aca8666c26426d6cb2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66847
Reviewed-by: Bao Zheng <fishbaozi@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
This README.md file specifies the expectations and agreements implied by
contributing code to the coreboot src/vendorcode directory.
Licenses, structure, formatting and the like are all the responsibility
of the contributors, however as the code is a part of the coreboot
codebase, members of the coreboot community are allowed to modify the
code to the extent deemed necessary.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ib7e2aedce9383158d03be342cb10ae18d85146ae
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67485
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Initial commit of the FSP-specific code for the Morgana SoC.
This is just an initial framework and still needs to be updated
to match the Morgana FSP.
Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Change-Id: Ic53c59404f96c73c55eb2648113c5ced26d6e20c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68192
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
The common directory is for files that shouldn't change, or shouldn't
change much between platforms.
These will be removed from other directories and used in upcoming
commits.
Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Change-Id: I37ed98a67b066598fdebcc5b034e64dc639fda7f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68191
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
The headers added are generated as per FSP v3361.03
In the future, when Alder Lake and Raptor Lake fsp align, Raptor Lake
fsp headers can be deleted and Raptor Lake soc will also use headers
from alderlake/ folder.
BUG=b:247855492
BRANCH=firmware-brya-14505.B
TEST=Boot to OS
Signed-off-by: Selma Bensaid <selma.bensaid@intel.com>
Change-Id: I267a0aefca18492bcbcfbf7acbe271887f0a39cf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67748
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Add new PSP svc call to pass psp firmware hash table to the PSP.
psp_verstage will verify hash table and then pass them to the PSP.
The PSP will check if signed firmware contents match these hashes.
This will prevent anyone replacing signed firmware in the RW region.
BUG=b:203597980
TEST=Build and boot to OS in Skyrim.
Change-Id: I512d359967eae925098973e90250111d6f59dd39
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67259
Reviewed-by: Robert Zieba <robertzieba@google.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
CL:3825558 changes all vb2_digest and vb2_hash functions to take a new
hwcrypto_allowed argument, to potentially let them try to call the
vb2ex_hwcrypto API for hash calculation. This change will open hardware
crypto acceleration up to all hash calculations in coreboot (most
notably CBFS verification). As part of this change, the
vb2_digest_buffer() function has been removed, so replace existing
instances in coreboot with the newer vb2_hash_calculate() API.
Due to the circular dependency of these changes with vboot, this patch
also needs to update the vboot submodule:
Updating from commit id 18cb85b5:
2load_kernel.c: Expose load kernel as vb2_api
to commit id b827ddb9:
tests: Ensure auxfw sync runs after EC sync
This brings in 15 new commits.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I287d8dac3c49ad7ea3e18a015874ce8d610ec67e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66561
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
Add the headers for 2.2.3.1, which includes the following changes
over 2.2.0.0:
• [Implemented]GLK: XHCLKGTEN Register setting causes S0ix entry
failure in less than 5 cycles when a USB2 Ethernet Dongle is
connected. Refer GLK BIOS Spec Volume1 CDI# 571118 under chapter
7.20.6 for new Register settings.
• [Implemented] [GLK/GLK-R] DDR4 16Gb SDP Memory support for Gemini
Lake/Gemini Lake – R
• [Update] MRC new version update to 1.38.
• [Fixed][GLK-R][WLAN] Removed the DSW function - Wake on LAN from
S4 issue with latest Wifi driver.
[Update] MRC new version update to 1.39. Included fix for
MinRefRate2xEnable and support for Rowhammer mitigation.
• [Fixed] Disable Dynamic DiffAmp and set CTLE from 7 to 5. This
change specific to DDR4 memory configuration.
• GLK Klocwork Fix
• [Update] MRC new version update to 1.40.
Added in a separate directory as the default. The 2.2.0.0 headers
were left and will be used for Google boards, as some offsets have
moved.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I09498368b116c2add816eeada2fa4d0dba6e5765
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64533
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
The headers added are generated as per FSP v3301.03
In the future, when Alder Lake and Raptor Lake fsp align, Raptor Lake
fsp headers can be deleted and Raptor Lake soc will also use headers
from alderlake/ folder.
BUG=b:243693364
BRANCH=firmware-brya-14505.B
TEST=Boot to OS
Signed-off-by: Selma Bensaid <selma.bensaid@intel.com>
Change-Id: Idbd39ed53d4ba05248a0e83c104846960253931e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67084
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Synchronize with AGESA/AgesaModulePkg/Include/MemDmi.h.
Add/correct values for DDR5, LPDDR5, LPDDR5X.
BUG=b:239000826
TEST=Build and verify with other patches in train
Change-Id: I127f21bfe2dfcd7794eb543185ea3fb362ff3914
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66952
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
To generate a complete _CPC ACPI object, coreboot needs the minimal and
nominal core speed values which are specific to the CPU and not only the
CPU family. Since this is done by an undocumented mechanism, FSP has to
do this and puts the information we need into a HOB. This adds the HOB
GUID and the structure of the HOB data.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Change-Id: Ibf338c32de367a3fd57695873da1625338fa196d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66549
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
'Mendocino' was an embargoed name and could previously not be used
in references to Skyrim. coreboot has references to sabrina both
in directory structure and in files. This will make life difficult
for people looking for Mendocino support in the long term. The code
name should be replaced with "mendocino".
BUG=b:239072117
TEST=Builds
Cq-Depend: chromium:3764023
Cq-Depend: chromium:3763392
Cq-Depend: chrome-internal:4876777
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: I2d0f76fde07a209a79f7e1596cc8064e53f06ada
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65861
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
This patch adds `_DEPRECATED_` tag to ChromeOS boot mode related event
logging types as below:
* ELOG_TYPE_CROS_RECOVERY_MODE <---- to record recovery boot reason
while booting into recovery mode
* ELOG_TYPE_CROS_DEVELOPER_MODE <--- if the platform is booted into
developer mode.
* ELOG_TYPE_CROS_DIAGNOSTICS <---- if the platform is booted into
diagnostic mode.
Drop static structure `cros_deprecated_recovery_reasons` as it has been
replaced by vb2_get_recovery_reason_string() function.
ELOG_TYPE_FW_BOOT_INFO event type is now used to record all those
related fw boot info along with ChromeOS boot mode/reason etc.
BUG=b:215615970
TEST=Build and boot google/kano to ChromeOS.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I932952ce32337e2d54473667ce17582a90882da8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65802
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
This patch calls into vboot API (vb2api_get_fw_boot_info) to retrieve
FW slot boot information like (tries count, current boot slot, previous
boot slot, previous boot status and boot mode).
Upon retrieval of the vboot information, elog callback from ramstage
records the info into the eventlog.
Additionally, this patch refactors the existing event logging mechanism
to add newer APIs to record vboot firmware boot related information.
BUG=b:215615970
TEST=Build and boot google/kano to ChromeOS and run below command to
check the cbmem log:
Scenario 1:
localhost ~ # cbmem -c | grep VB2
[INFO ] VB2:vb2_check_recovery() Recovery reason from previous boot:
0x0 / 0x0
[INFO ] VB2:vb2api_fill_boot_config() boot_mode=`Developer boot`
VB2:vb2api_get_fw_boot_info() fw_tried=`A` fw_try_count=0
fw_prev_tried=`A` fw_prev_result=`Success`.
....
Scenario 2:
localhost ~ # crossystem recovery_request=1
localhost ~ # cbmem -c | grep VB2
[INFO ] VB2:vb2api_fill_boot_config() boot_mode=`Manual recovery boot`
VB2:vb2api_fill_boot_config() recovery_reason=0x13 / 0x00
VB2:vb2api_get_fw_boot_info() fw_tried=`A` fw_try_count=0
fw_prev_tried=`A` fw_prev_result=`Unknown`.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I6882cd1c4dbe5e24f6460388cd1af4e4a05fc4da
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65561
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This reverts commit 78261e308de5361b2ff045091e8fb18cad2a5035.
Reason for revert: Now that PSP supports a soft fuse flag to toggle the
verstage serial logs, prevent PSP verstage from writing to the UART.
BUG=None
TEST=Build and boot to OS in Skyrim with PSP verstage. Ensure that PSP
verstage logs are not seen twice in the console.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I7ef2d585c320ea5903197939136dd2049a71af95
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66248
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
SoC FW ID needs to be populated at offset 0x58 and 0x59 in the PSP
header.
BUG=b:217414563
TEST=Build Skyrim BIOS image and ensure that PSP verstage is getting
loaded.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: Ibe7b26aea0567e5337ee3e6e9447aa3944c55f5b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65860
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
The headers added are generated as per FSP v3257_00_40.
In the future, when Alder Lake and Raptor Lake fsp align, Raptor Lake
fsp headers can be deleted and Raptor Lake soc will also use headers
from alderlake/ folder.
BUG=b:238791453
BRANCH=firmware-brya-14505.B
TEST=none
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: If8fd6700f0afed7e2bd5d73a95407dbfd3e88abd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65803
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
This patch fixes a missing header file compilation issue when coreboot
selects MP_SERVICES_PPI_V2 config from MTL SoC.
The `MpServices2.h` file doesn't exist in the upstreamed EDK2 repo
(integrated with `edk2-stable202111` stable tag).
Currently MpServices2.h file is being copied from the
`edk2_stable202005` stable tag.
BUG=b:237960384 ([Intel FSP][EDK2011] MpServices2.h header is missing
in upstream EDKII git)
TEST=Able to fix the compilation issue on Google/Rex (Meteor Lake)
when MP_SERVICES_PPI_V2 kconfig is enabled.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ib7c406ff51439c93c6d15f3a69808b4d1590cfa5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65624
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Sabrina previously didn't support UART mapping in psp verstage. Now that it has been enabled, add the relevant uart code here.
BUG=b:218709292
TEST=Set serial soft fuse, boot to kernel, check logs
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: I591fa69b6e722929839babfff62e9d56c68e1112
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65532
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Branding changes to unify and update Chrome OS to ChromeOS (removing the
space).
This CL also includes changing Chromium OS to ChromiumOS as well.
BUG=None
TEST=N/A
Change-Id: I39af9f1069b62747dbfeebdd62d85fabfa655dcd
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65479
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Update header files for FSP for Meteor Lake platform to version 2222_01, previous version being 2173_00.
FSPM:
Includes below 2 UPDs
1. TdcEnable
2. TdcTimeWindow
FSPS:
Address Offset changes.
BUG=b:234701164
TEST=util/abuild/abuild -p none -t google/rex -a -c max
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: I529118c35fa9f851ee2b5f23712ac70e2a5b53c5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64878
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Do not discard the const qualifier in `GnbRegisterWriteTNDump()` to fix
the compiler warning below.
CC libagesa/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbRegisterAccTN.o
In file included from src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbRegisterAccTN.c:53:
src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbRegisterAccTN.c: In function 'GnbRegisterWriteTN':
src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbRegisterAccTN.c:836:57: error: passing argument 3 of 'GnbRegisterWriteTNDump' discards 'const' qualifier from pointer target type [-Werror=discarded-qualifiers]
836 | GnbRegisterWriteTNDump (RegisterSpaceType, Address, Value);
| ^~~~~
src/vendorcode/amd/agesa/f15tn/Proc/GNB/Common/Gnb.h:68:35: note: in definition of macro 'GNB_DEBUG_CODE'
68 | #define GNB_DEBUG_CODE(Code) Code
| ^~~~
src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbRegisterAccTN.c:86:33: note: expected 'VOID *' {aka 'void *'} but argument is of type 'const VOID *' {aka 'const void *'}
86 | IN VOID *Value
| ~~~~~~~~~~~~~~~~~~~~~^~~~~
CC libagesa/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieComplexDataTN.o
CC libagesa/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieConfigTN.o
CC libagesa/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieEarlyInitTN.o
CC libagesa/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieEnvInitTN.o
CC libagesa/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieLibTN.o
src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbRegisterAccTN.c: At top level:
cc1: note: unrecognized command-line option '-Wno-pragma-pack' may have been intended to silence earlier diagnostics
cc1: all warnings being treated as errors
Found-by: gcc (Debian 11.3.0-3) 11.3.0
Change-Id: I2039cf66030030458bd247a31adc0621b9d033e6
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64989
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
The headers added are generated as per FSP v3172
In the future, when Alder Lake and Raptor Lake fsp align, Raptor Lake
fsp headers can be deleted and Raptor Lake soc will also use headers
from alderlake/ folder.
BUG=b:229134437
BRANCH=firmware-brya-14505.B
TEST=Boot to OS
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: I5aa0611b19bb4f6667a95d2539cc2d17de6dcf07
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64839
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
The headers added are generated as per FSP v3127_05_8.
In the future, when Alder Lake and Raptor Lake fsp align, Raptor Lake
fsp headers can be deleted and Raptor Lake soc will also use headers
from alderlake/ folder.
BUG=b:229134437
BRANCH=firmware-brya-14505.B
TEST=none
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: I9dd14468ec09bfe1a0904686e66d37a7389efdd4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64529
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
There are zero-initialized arrays within AGESA that were previously not
declared with CONST qualifier. Without this flag, such arrays would have
consumed valuable CAR space in romstage.
After adding CONST qualifiers these arrays have actually moved to
.rodata and removing the flag does not add anything to .bss.
TEST: see that BUILD_TIMELESS=1 results in the same binary.
Change-Id: I5b91deb1bf1b64bd9c88dc311db4e0b36df86c18
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64445
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Martin L Roth <gaumless@tutanota.com>
AGESA has a lot of code in the .data section which is for initialized
data, that in fact should be .rodata. This adds the 'CONST' keyword
everywhere it is needed.
TEST: See in the .elf file (e.g. using readelf) that there is nothing in
.data section.
Change-Id: Ie8817434ee0bc6c195eabe090f195512c0043ae5
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64400
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
AGESA has a lot of code in the .data section which is for initialized
data, that in fact should be .rodata. This adds the 'CONST' keyword
everywhere it is needed.
TEST: See in the .elf file (e.g. using readelf) that there is nothing in
.data section.
Change-Id: I657d09f05070f5a88a4a162872c961db869a8df3
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64399
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
AGESA has a lot of code in the .data section which is for initialized
data, that in fact should be .rodata. This adds the 'CONST' keyword
everywhere it is needed.
TEST: See in the .elf file (e.g. using readelf) that there is nothing in
.data section.
Change-Id: I9593c24f764319f66a64715d91175f64edf10608
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64386
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Update the PSP header to set the SOC FW ID to 0x0149 for
this platform
BUG=b:217414563
TEST=Build and verify header is set correctly
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: Ic604ec96560c2d4d89c48c4a27528c5cfe4ca7e7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64482
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Use 'ENV' consistently and drop the redundant 'STAGE' in the naming.
Change-Id: I51f2a7e70eefad12aa214e92f23e5fd2edf46698
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64296
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Add and use defines instead of magic values in fsp_m_params.c.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ie0e33eb0af5310ab4610ea8951688464c4960260
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64126
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This file started as a copy from Cezanne. Sabrina has less USB ports
than Cezanne. Also the struct definition of fch_usb2_phy has changed and
FSP_USB_STRUCT_MINOR_VERSION is also updated.
TEST=None
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I1ef2b62373b178d729b3230d0d8539986cc631ae
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64129
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Add and use defines instead of magic values in fsp_m_params.c. The
values will be updated to match the Sabrina FSP in a follow-up commit.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I91da9e9d2b95e169dd73153766f24cf8afbfa4ef
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64128
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Although useful to declare local symbols inside macros clang does not
support them. Using the \@ symbol which increments each time the macro
is used we can do the same. With BUILD_TIMELESS=1 the binaries don't
change and do build with GCC so nothing is lost here.
Change-Id: I01054e2bdcb63810b21eb51b46bdc6e1bd999516
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63045
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Martin Roth