Commit Graph

22545 Commits

Author SHA1 Message Date
Lubomir Rintel 752d447b61 mainboard/winnet/g170: drop the redundant vendor name
"WinNET WinNET G170" doesn't look too cool :(

Change-Id: Iae0a8725645b9d6321b64ccbad10633e0049d477
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Reviewed-on: https://review.coreboot.org/21612
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-09-26 16:49:29 +00:00
Lubomir Rintel 297b8392bc mainboard/winnet/g170: disable use of upper memory for SeaBIOS
Otherwise the USB init gets unhappy:

  |3df52000| EHCI init on dev 00:10.4 (regs=0xfd010010)
  |3df3d000| WARNING - Timeout at ehci_wait_td:515!
  |3df3d000| ehci pipe=0x3df52880 cur=00000000 tok=00000000 next=3df3ddc0 td=0x3df3ddc0 status=80e80
  |3df3e000| WARNING - Timeout at ehci_wait_td:515!
  |3df3e000| ehci pipe=0x3df52a80 cur=3df3ee00 tok=00000d00 next=3df3edc0 td=0x3df3edc0 status=80e80
  |3df3e000| WARNING - Timeout at ehci_wait_td:515!
  |3df3e000| ehci pipe=0x000ee680 cur=00000000 tok=00000000 next=3df3ecc0 td=0x3df3ecc0 status=1f0c80

Change-Id: I69f1fe38503b0f8d6015b515637d8376726490c0
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Reviewed-on: https://review.coreboot.org/18905
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
2017-09-26 16:49:12 +00:00
Lubomir Rintel c8832e1cee mainboard: use SeaBIOS config only when it's the payload of choice
It makes no sense for Das U-Boot which uses the same setting.

Change-Id: I1629aecf33cb62bb1e6856ef5627748a7dc74d8a
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Reviewed-on: https://review.coreboot.org/21611
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-09-26 16:48:27 +00:00
Marshall Dawson 7ac2af32f3 amd/stoneyridge: Make UMA memory cacheable
Use reserved_ram_resource to help ensure the UMA memory is typed
as WB.

BUG=b:65856868
TEST=Inspect MTRRs and compare with UMA memory

Change-Id: Ifa54d9b1c206d2ee6dc4b8f90b445a6820ceb8fd
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21606
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-09-26 16:44:54 +00:00
Marshall Dawson bbf91af9a2 amd/stoneyridge: Remove EXT_CONF_SUPPORT check
The EXT_CONF_SUPPORT symbol doesn't exist for the Stoney Ridge SoC.
Clean up northbridge.c by removing the check for the config value set.

Remove the CPU initialization code that clears the EnableCf8ExtCfg
bit.  The location where it was set was removed in
  c1d72942 Disable PCI_CFG_EXT_IO

BUG=b:66202622

Change-Id: Ic58c47fc5f568d17f5027c96d4152b0e5b3e1d14
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21497
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-09-26 16:42:38 +00:00
Marshall Dawson 29f1b74795 amd/stoneyridge: Simplify memory hole calculation
Delete the obselete Kconfig symbols regarding the memory hole.  Integrate
the hole check into domain_set_resources().  The hardware configuration
is done by AGESA, so only discover the setting and adjust the mmio_basek
accordingly.

BUG=b:66202887
TEST=Check settings with HDT

Change-Id: Id15a88897e29bff28ab7c498dc4d3818834f08b2
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21496
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-26 16:40:11 +00:00
Bill XIE c8050f4bfc device/dram/ddr2.c: fix a hidden syntax error introduced earlier
A regression is hidden in commit 7eb0157fca
(device/dram/ddr2.c: Decoding byte[12] bit7 as self refresh flag ), which
breaks the build procedure when CONFIG_DEBUG_RAM_SETUP is set.

Maybe it had better implement "printram" and the like as inline
functions instead of macros.

Change-Id: If956435bd0c39b1f3e722c2cfc48d2d0f35abc9b
Signed-off-by: Bill XIE <persmule@gmail.com>
Reviewed-on: https://review.coreboot.org/21673
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-09-26 15:53:55 +00:00
Furquan Shaikh a4ab665a55 mb/google/*: Use newly added Chrome EC boardid function
Instead of duplicating code across multiple mainboards, use newly
added helper function to read boardid from Chrome EC.

Change-Id: I1671c0a0b87d0c4c45da5340e8f17a4a798317ca
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/21682
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-26 15:20:39 +00:00
Furquan Shaikh a2094835b1 chromeec: Provide helper routine to read boardid from Chrome EC
Instead of duplicating the code across multiple mainboards, provide a
helper function to read boardid from Chrome EC.

Change-Id: I2008de7032bc880e90b2c3c385b2a67bfb8724cc
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/21681
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2017-09-26 13:38:44 +00:00
Kyösti Mälkki d4955f0ade AGESA: Move API interface under drivers/
New AGESA support files will be used for binaryPI
platforms as well. Furthermore, some of those should
move from split nb/ sb/ directories to soc/, so move
support files for the API under drivers/.

Change-Id: I549788091de91f61de8b9adc223d52ffb5732235
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21455
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-26 10:07:07 +00:00
Kyösti Mälkki 0f6c0b1a6f AGESA: Drop CAR teardown without POSTCAR_STAGE
Except for family15, all AGESA boards have moved
away from AGESA_LEGACY_WRAPPER, thus they all
have POSTCAR_STAGE now.

AGESA family15 boards remain at AGESA_LEGACY=y, but
those boards have per-board romstage.c files and
are not touched here.

Change-Id: If750766cc7a9ecca4641a8f14e1ab15e9abb7ff5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/18632
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-26 10:06:32 +00:00
Kyösti Mälkki 63fac81fc8 AGESA: Implement POSTCAR_STAGE
Move all boards that have moved away from AGESA_LEGACY_WRAPPER
or BINARYPI_LEGACY_WRAPPER to use POSTCAR_STAGE.

We use POSTCAR_STAGE as a conditional in CAR teardown to tell
our MTRR setup is prepared such that invalidation without
writeback is a valid operation.

Change-Id: I3f4e2170054bdb84c72d2f7c956f8d51a6d7f0ca
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21384
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-26 10:05:48 +00:00
Kyösti Mälkki 8bf978c2aa AGESA: Drop unused code in eventlog
Change-Id: I1d4b86c0e74cf4e1a7862889638125e5adcd4c3d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21665
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-09-26 10:01:03 +00:00
Kyösti Mälkki f724e89dce binaryPI: Drop Options.h include
Change-Id: Ide14bd164fe4a1846f86c6be326e2cd4f540bf97
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21662
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-09-26 09:58:47 +00:00
Kyösti Mälkki 525930bdf4 binaryPI boards: Fix indirect AGESA.h include
Change-Id: I3f6030879da61168adf42db0a4913d70a737594e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21649
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-09-26 09:58:29 +00:00
Kyösti Mälkki d41feed800 AGESA: Avoid cpuRegisters.h include
Change-Id: I077677c10508a89a79bcb580249c1310e319aaf1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21664
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-26 09:26:09 +00:00
Kyösti Mälkki d229d4a28e AGESA cimx: Move cb_types.h to vendorcode
This file mostly mimics Porting.h and should be removed.
For now, move it and use it consistently with incorrect form
as #include "cbtypes.h".

Change-Id: Ifaee2694f9f33a4da6e780b03d41bdfab9e2813e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21663
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-26 09:25:47 +00:00
Kyösti Mälkki d42b799a9e AGESA: Fix OptionsIds.h include
Fix regression of IDS debugging after commit

  1210026 AGESA buildsystem: Reduce include path exposure

Mainboard directory was removed from libagesa includes
path here, and this resulted with fam15tn and fam16kb using
a template OptionsIds.h file under vendorcode/ instead.

Add mainboard directory back to include path of libagesa
and remove those (empty) template files.

Change-Id: Iee4341a527b4c152269565cac85e52db44503ea6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21661
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-26 09:23:27 +00:00
Kyösti Mälkki 87df26731e AGESA: Remove heap allocations from OemCustomize.c
We can simply declare these structures const.

Change-Id: I637c60cc2f83e682bd5e415b674f6e27c705ac91
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21631
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-26 09:22:03 +00:00
Kyösti Mälkki e66e39059e AGESA: Allow const PcieComplexList for OemCustomize
It's already implemented like this with binaryPI API header.
That implementation is essentially the same with 'const' qualifier
just being ignored in the build process for PI blob.

For open-source AGESA build, work around -Werror=discarded-qualifier
using a simple but ugly cast.

Change-Id: Ib84eb9aa40f1f4442f7aeaa8c15f6f1cbc6ca295
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21630
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-26 09:21:43 +00:00
Kyösti Mälkki e52738b428 AGESA binaryPI boards: Fix some whitespace
Change-Id: I150d4a71536137a725f43d900d483e7e35592bb3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21629
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-09-26 08:36:05 +00:00
Kyösti Mälkki e1dced4561 amd/torpedo: Drop PlatformGnbPcieComplex.h
Copy-paste, was not really used at all.

Change-Id: I9a916f6fa0f6a48de6ac62be6f366cee0e406a8f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21648
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-09-26 08:35:43 +00:00
Kevin Chiu b6850ddbff google/snappy: Override SKU ID by VPD
Since snappy PCB may have over 9 SKU and current GPIO board ID GP16/GP17
is insufficient to use.
Using VPD to control could prevent H/W change.

BUG=b:65339688
BRANCH=reef
TEST=emerge-snappy coreboot
Change-Id: I55ab741354797e022dd945da9c8499ee5e041316
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/21533
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-09-26 03:35:29 +00:00
Aaron Durbin a871059ef2 mainboard/google/reef: expose sku strapping helper function
variant_board_sku() callback exists to allow some of the variants to
report the sku id differently based on board implementation. However,
there are cases where there are multiple ways to encode the sku id, but
the original way should be used as a fallback. As such expose a helper
function, sku_strapping_value(), such that there isn't code duplication
for the common fallback case.

BUG=b:65339688

Change-Id: I1e917733eb89aebc41a483e2001a02acfda31bf4
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/21645
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-09-26 03:35:24 +00:00
Furquan Shaikh 8f08f5f5c7 soraka: Ensure I2C5 frequency is less than 400kHz
Update I2C5 bus parameters to obtain clock frequency <400kHz.

BUG=b:65062416
TEST=Verified using an oscilloscope that I2C5 bus frequency
in factory is ~397kHz.

Change-Id: I3d0b0388343d4c6c5e7eabf3e06799d059307517
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/21669
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-26 02:20:48 +00:00
Jonathan Neuschäfer 3a182f7e31 soc/intel: lpc: Use IS_POWER_OF_2 instead of open-coding it
Change-Id: I7a10a3fa5e1e9140a558f61109d0c9094d46e521
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/21655
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-09-25 23:38:43 +00:00
Patrick Rudolph df27690df3 mb/lenovo/x2?0/devicetree: Fix regression of BDC detection
The x220 and x230 do have BDC detection, but it's broken.
Disable BDC detection on those two boards, and add a comment
why it doesn't work.

The issue has been reported and tested on Lenovo X220.

Change-Id: Id1ccc2c4387370e284ff8964e1c41d945cefe74c
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/21587
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-09-25 16:18:38 +00:00
Patrick Rudolph 3b0f5426af ec/lenovo/pmh7: Dump revision and ID
Dump PMH7 revision and ID for diagnostic purposes.

Tested on Lenovo T430: PMH7: ID 05 Revision 12

Change-Id: I60d15a8f740aeb974a79b27507e974a730cec174
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/20807
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2017-09-25 16:18:19 +00:00
Arthur Heymans 5661945c3b nb/i945/raminit: Don't fall back to smbus read on failed SPD decode
SPD decoding problems are no longer a good method for detecting if i2c
byte read failed, since the return value of i2c_block_read is checked.

Change-Id: I230aa22964c452cf28a9370c927b82c57e39cc62
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/21621
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-09-25 13:35:48 +00:00
Kyösti Mälkki c8bc983673 console: Ignore loglevel in nvram until ramstage
Calling get_option() triggers printk's before consoles
are ready. Skip the call since console_loglevel is const
anyways for __PRE_RAM__.

Change-Id: I4d444bee1394449ce096c0aa30dca56365290e31
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21659
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-09-25 13:35:29 +00:00
Arthur Heymans 8b64e7ae21 mb/intel/dg43gt: Add romstage timestamps
Change-Id: I0383dd9b582d5c77be66ecd74bcf1a438f874cc7
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/21635
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-09-23 22:29:35 +00:00
Arthur Heymans b47444533b mb/intel/dg43gt: Set SuperIO gpio correctly
Set SuperIO GPIO like vendor firmware.

Change-Id: I46a48776382eb0d9be9727691c68912991e14dfe
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/21627
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-09-23 22:29:09 +00:00
Arthur Heymans b29078e401 mb/*/*: Remove rtc nvram configurable baud rate
There have been discussions about removing this since it does not seem
to be used much and only creates troubles for boards without defaults,
not to mention that it was configurable on many boards that do not
even feature uart.

It is still possible to configure the baudrate through the Kconfig
option.

Change-Id: I71698d9b188eeac73670b18b757dff5fcea0df41
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19682
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-09-23 11:06:25 +00:00
Nico Huber 1850aa6df6 toolchain: Always use GCC for Ada sources
We can't use $(CC) in case it's set to Clang.

TEST=Built one target with Ada sources before and after this change and
     verified that the same compiler commands are emitted.

Change-Id: I9b8ea35352d74b364f09fc12d8d981ca42f8b7c8
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/21366
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-09-23 10:57:40 +00:00
Nico Huber 5218533ae7 Makefile.inc: Remove -gnatg from ADAFLAGS_common
It was only set by accident. `-gnatg` is a special mode for GNAT
internals and libgnat (we already set it explicitly for the latter).

TEST=Gave libgfxinit a shot on lenovo/t420.

Change-Id: Ie56a95da2dafd014bd6152cb419a2d315e7c78c4
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/21365
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-09-23 10:50:45 +00:00
Nico Huber dd9754dd62 toolchain: Use xcompile proposed CFLAGS for Ada
We don't output special ADAFLAGS in xcompile but its CFLAGS are
compatible with and necessary for Ada too. So use the latter and
make sure we use them for libgnat too.

Fixes i386 builds with x86_64 toolchain.

TEST=Gave libgfxinit a shot on lenovo/t420.

Change-Id: I0d13f182acfaa9bd1b608edd8a508c4ceedef3b3
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/21363
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-09-23 10:50:29 +00:00
Nico Huber 2ac149d294 sb/intel/bd82x6x: Revise flash ROM lockdown options
The original options were named and described under the false assumption
that the chipset lockdown would only be executed during S3 resume. Fix
that.

Change-Id: I435a3b63dd294aa766b1eccf1aa80a7c47e55c95
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/21327
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2017-09-22 19:17:49 +00:00
Arthur Heymans 7eb0157fca device/dram/ddr2.c: Decoding byte[12] bit7 as self refresh flag
"Annex J: Serial Presence Detects for DDR2 SDRAM (Revision 1.3)" note
4 says bit7 of byte 12 indicates whether the assembly supports self
refresh.

This patch decodes this and modifies decoding tRR accordingly.

Change-Id: I091121a5d08159cea4befdedb5f3a92ce132c6e5
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/21620
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-09-22 18:31:03 +00:00
Arthur Heymans c88e370f85 sb/intel/common/spi.c: Port to i82801gx
Offsets are a little different.

Change-Id: I39199f3279a8b76e290b6693adc50dc2ac0ccf23
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/21113
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-09-22 18:04:36 +00:00
Arthur Heymans 524d497355 nb/intel/x4x: Select LAPIC_MONOTONIC_TIMER
Needed for coreboot spi driver.

Change-Id: I01059c8cbdc6a002dfd75b6da3a629811b137702
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/21320
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-09-22 17:31:40 +00:00
Patrick Georgi a2248cbf9a device/dram/ddr2: Add break to several case statements that lack it
For all valid SPD values the same decoded tRR was returned.

Change-Id: Iec43f8c7460dfcf68f7c92dfdf333b004f368b65
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Found-by: Coverity Scan #1381369, #1381370, 1381371, 1381372, 1381373
Reviewed-on: https://review.coreboot.org/21642
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-09-22 17:24:39 +00:00
Subrata Banik fdddc463ce soc/intel/skylake: Calculate soc reserved memory size
This patch implements soc override function to calculate reserve memory
size (PRMRR, TraceHub, PTT etc). System memory should reserve those
memory ranges.

BRANCH=none
BUG=b:63974384
TEST=Ensures DRAM based resource allocation has taken care
of intel soc reserved ranges.

Change-Id: I19583f7d18ca11c3a58eb61c927e5c3c3b65d2ec
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/21540
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-09-22 16:23:30 +00:00
Subrata Banik 73b8503183 soc/intel/common: Add function to get soc reserved memory size
This patch ensures to consider soc reserved memory size while
allocating DRAM based resources.

Change-Id: I587a9c1ea44f2dbf67099fef03d0ff92bc44f242
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/21539
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-22 15:33:41 +00:00
Subrata Banik 7387e04a35 soc/intel/skylake: Use EBDA area to store cbmem_top address
This patch uses BIOS EBDA area to store relevent details
like cbmem top during romstage after MRC init is done.
Also provide provision to use the same EBDA data across
various stages without reexecuting memory map algorithm.

BRANCH=none
BUG=b:63974384
TEST=Ensures HW based memmap algorithm is executing once in romstage
and store required data into EBDA for other stage to avoid redundant
calculation and get cbmem_top start from EBDA area.

Change-Id: Ib1a674efa5ab3a4fc076fc93236edd911d28b398
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/21424
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-22 15:32:03 +00:00
Subrata Banik ef059c5a09 soc/intel/common: Add intel common EBDA support
This patch provides EBDA library for soc usage.

Change-Id: I8355a1dd528b111f1391e6d28a9b174edddc9ca0
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/21538
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-22 15:31:14 +00:00
Subrata Banik 82ef364f9a soc/intel/skylake: Refactor memory layout calculation
This patch split entire memory layout calculation into
two parts. 1. Generic memory layout 2. SoC specific
reserve memory layout.

usable memory start = TOLUD - Generic memory size -
                   - soc specific reserve memory size.

Change-Id: I510d286ce5e0d8509ec31a65e971d5f19450364f
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/21537
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-22 15:31:09 +00:00
Subrata Banik 19dbffd010 arch/x86: Add ebda read/write functions into EBDA library
This patch provides new APIs to write into EBDA area
and read from EBDA area based on user input structure.

Change-Id: I26d5c0ba82c842f0b734a8e0f03abf148737c5c4
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/21536
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2017-09-22 15:29:38 +00:00
Subrata Banik c7590cd9f3 arch/x86: Enable ebda library for romstage and postcar
This patch provides a kconfig option as EARLY_EBDA_INIT to
ensures user can make use of EBDA library even during early
boot stages like romstage, postcar.

Change-Id: I603800a531f56b6ebd460d5951c35a645fbfe492
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/21388
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-22 15:29:30 +00:00
Subrata Banik 5d2928cdab arch/x86: Include acpi_s3.c support in postcar stage
This patch ensures acpi APIs are available for postcar
stage.

Change-Id: Ia0f83cd4886ba7a16286dbbeb3257ede014ee3c7
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/21626
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-22 15:29:25 +00:00
Arthur Heymans fd440bb79e mb/asrock/g41c-gs: Fix the SATA clock output on ck505
With reset default of the clockgen on this board the SATA clock which
needs to be 100MHz depends on FSB BSEL straps.

This explains why SATA was originally tested to be working but fails
with CPUs operating at different FSB.

This change sets a bit in the clockgen configuration which fixes the
SATA clock.

TESTED on with a 1333MHz FSB CPU.

Change-Id: Ic2b8ca91920f015ae3265871bc092023302fefdc
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/21257
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
2017-09-22 13:09:10 +00:00