Commit Graph

43590 Commits

Author SHA1 Message Date
Felix Singer f9948a4d39 util/liveiso: Add NixOS configs for bootable live systems
Add NixOS configurations for bootable live systems containing a set of
tools which might be useful for firmware development in general and for
working on coreboot.

There are two configurations provided. One for console-only and a
graphical one, which is mostly the same as the console image but it
comes with Gnome Shell as window manager and some graphical tools in
addition.

An image can be built using `build-console.sh`, respectively
`build-graphical.sh`. The resulting iso image can be found in
`result/iso/`.

The console image results in ~700MB, while the graphical one results in
~2GB.

Change-Id: Iaf49d198e99781434bd89d2a8a125a4988b77e1c
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50194
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-09-03 19:38:15 +00:00
Subrata Banik 5586c79978 arch/x86: Update debug message to callout the reason for failure
This patch updates debug message to specifically the case when SMBIOS
table 7 write would abort due to either `unknown` CPU or CPU `doesn't
have support for deterministic cache cpuid leaf`.

Change-Id: I288593b3f78ab858bf66c689e7cfb6ba2ff746d0
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57337
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-03 19:14:49 +00:00
Subrata Banik 6efc4aa4af arch/x86: Check unsupported CPU type while writing to SMBIOS table 7
Don't attempt to fill the SMBIOS table if the CPU doesn't support
deterministic cache CPUID.

TEST=Able to fix the hang issue seen on ASRock E350M1 with commit hash
e2b5fee.

Change-Id: Id65dc963e235f7080370a32cf69bcc4bee94d28f
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57306
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Swift Geek (Sebastian Grzywna) <swiftgeek@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-03 19:14:31 +00:00
Subrata Banik 72f1e62bbb arch/x86: Skip returning default leaf value as `0`
`cpu_get_cache_info_leaf()` function is responsible to report leaf
value for CPU that have support for deterministic cache cpuid. As per
available datasheets from AMD and Intel the supported CPUID leafs are
0x8000_001d for AMD and 0x04 for Intel. Hence, this CL skips returning
default leaf value as `0`.

TEST=Verified fixes: e2b5fee3b0 (arch/x86: smbios write 7 table using
deterministic cache functions) hang issue on ASRock E350M1.

Change-Id: Iee33b39298e7821ac5280d998172b58a70c8715b
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57305
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-03 19:14:16 +00:00
Roja Rani Yarubandi 04096b9773 sc7280: Refactor QSPI driver
Refactor Qcom QSPI driver to separate common
and SoC specific driver code.

BUG=b:182963902
TEST=Validated on qualcomm sc7280 development board

Signed-off-by: Rajesh Patil <rajpat@codeaurora.org>
Change-Id: Ibe1dc3fe8bd71957ff8604ef4c9d97963100ccfb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55322
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
2021-09-03 18:01:57 +00:00
Sumeet Pawnikar 684a4f21bb mb/google/brya/variants: fix override values for power limits
There are two different types of 682 SKU available with TDP
of 28W and 45W. This patch fix override values for power
limits for these 682 SKU. This patch also sets power limit
values dynamically based on machine ID and CPU TDP of SKU.

BUG=b:194745919
BRANCH=None
TEST=Build FW and test on brya0 board

Change-Id: I796e56321ae9c8312530a4b8986cd73a2245f5fa
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57290
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-03 17:06:20 +00:00
Ravi Kumar Bokka 423945876d soc/qualcomm/common/qspi: Add support for common QSPI driver
copy existing QSPI driver from /soc/qualcomm/sc7180 to common folder.

This common QSPI driver works in master mode and provides read/write
operation for the slave devices like flash.

BUG=b:182963902
TEST=Validated on qualcomm sc7180 and sc7280 development board

Signed-off-by: Rajesh Patil <rajpat@codeaurora.org>
Change-Id: I5b3816b823e14db1dd13f1eb4a6761c7a61604b9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55323
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
2021-09-03 16:59:06 +00:00
Ravi Kumar Bokka 65af8bbe72 soc/qualcomm/sc7280: DDR One-Time-Training Support
Introduce DDR One-Time-Training Support
Device reboots without training from second iteration
and also DDR training data is 32kb size, hence update
required in memlayout and to sync with upstream changes
the Fmap size even got bumped up.

BUG=b:182963902
TEST=Validated on qualcomm sc7280 development board

Change-Id: I81038c5c7802c154f4310509c6c64710580b8ce4
Signed-off-by: Sudheer Kumar Amrabadi <samrabad@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54352
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
2021-09-03 16:58:32 +00:00
Shaik Sajida Bhanu 1de2dd25f7 mainboard/google/herobrine: Configure SDCC clock
Configure 384MHz for eMMC clock and 50MHz for SD card clock.

BUG=b:182963902
TEST=Validated on qualcomm sc7280 development board

Change-Id: I8acbce58614add0228adc39289762da10937cbe2
Signed-off-by: Shaik Sajida Bhanu <sbhanu@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50585
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
2021-09-03 16:53:56 +00:00
Taniya Das 3fe6c03a39 qualcomm/sc7280: Move to use common clock driver for sc7280
It supports the clock consumers for QUP, SDCC, PCIE, Display to be able
to configure & enable the desired clocks.

The clock driver also supports reset of subsystems like AOP and SHRM.
Also add support for Zonda PLL enable for CPU in common clock driver.

Refactor the SC7280 clock driver to use the common clock driver APIs.

BUG=b:182963902
TEST=Validated on qualcomm sc7280 development board

Change-Id: I590a93cda0d6eccb51b54692b620d43ccacede77
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50580
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-03 16:45:37 +00:00
Selma Bensaid 6239e1b252 mb/intel/adlrvp_m: Fix TPM IRQ conflict with I2C4
Add TPM IRQ config to gpio_m.c, so the TPM IRQ is not allocated
to I2C4.

BUG=NA
BRANCH=None
TEST= boot to os and check cat /proc/interrupts, cr50 SPI interrupt is assigned
and does not conflict with I2C.
            CPU0       CPU1       CPU2       CPU3       CPU4       CPU5       CPU6       CPU7       CPU8       CPU9       CPU10      CPU11
   0:         36          0          0          0          0          0          0          0          0          0          0          0   IO-APIC    2-edge      timer
   1:          0          0          0          0          0          0          0          0          9          0          0          0   IO-APIC    1-edge      i8042
   8:          0          0          0          0          0          0          0          0          0          0          0          0   IO-APIC    8-edge      rtc0
   9:          0          0          0          0          0          0          0          0          0          0          0          0   IO-APIC    9-fasteoi   acpi
  14:          0          0          0          0          0          0          0          0          0          0          0          0   IO-APIC   14-fasteoi   INTC1055:00
  16:          0          0          0          0          0          0          0          0          0          0          4          0   IO-APIC   16-fasteoi   intel-ipu6
  22:          0         13          0          0          0          0          0          0          0          0          0          0   IO-APIC   22-fasteoi   idma64.4, i801_smbus, ttyS0
  37:          0          0          0          0          0          0          0          0          0          0          0          0   IO-APIC   37-fasteoi   idma64.0, i2c_designware.0
  38:          0          0          0          0          0          0          0          0          0          0          4          0   IO-APIC   38-fasteoi   idma64.1, i2c_designware.1
  41:          0          0          0          0       2274          0          0          0          0          0          0          0   IO-APIC   41-edge      cr50_spi
  42:          0          0          0          0          0          0          0          0          0          0          0          0   IO-APIC   42-fasteoi   idma64.2, i2c_designware.2
  43:          4          0          0          0          0          0          0          0          0          0          0          0   IO-APIC   43-fasteoi   idma64.3, i2c_designware.3

Signed-off-by: Selma Bensaid <selma.bensaid@intel.com>
Change-Id: Id0f3885dec5a6f635254c233709090321491c739
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57102
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-03 16:36:02 +00:00
Sumeet Pawnikar eaf87a9d60 soc/intel/alderlake: set power limits dynamically for thermal
Set power limit values dynamically based on CPU TDP and PCI ID of SKU.

BUG=b:194745919
BRANCH=None
TEST=Build FW and test on brya0 board

Change-Id: Ic331a3debb076ef08a312a31edc1468974fd4902
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57035
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-03 16:14:28 +00:00
Sumeet Pawnikar dc0e066406 soc/intel/common: get tdp of CPU for different SKUs
Get tdp value of CPU for different SKUs based on PKG POWER MSR.

BUG=b:194745919
BRANCH=None
TEST=Build FW and test on brya0 board

Change-Id: I9fba0a64da2f1d79d633054dddd9fdf1d3d8e258
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57143
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-09-03 16:14:15 +00:00
Felix Held 2909b487a2 mb/pcengines/apu2: add and use IOMUX defines
Add GPIO IOMUX defines for the pins that are used in the mainboard code
which enables using the PAD_GPI and PAD_GPO macros.

TEST=Timeless build for APU2/3/4/5 results in identical binary.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ie32df9ed2cb6a5670a29cff91e085a3585c8bcf7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56836
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2021-09-03 15:56:54 +00:00
Felix Held 4b027690b6 soc/amd/common/block/gpio_banks/Kconfig: add option for non-soc/ chips
southbridge/amd/pi/hudson uses the common GPIO bank access code from
soc/amd, but doesn't provide all functionality that would be needed to
use the full functionality. Add a Kconfig option that switches off some
functionality in the common SoC GPIO access code, so that more of the
functionality proviced by the common SoC GPIO code can be used in the
AMD binaryPI chipset and board code.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib10d5d5580aab30a359aa001bb6fc7e9fdb8fc41
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56783
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-03 15:51:37 +00:00
Felix Held 99c4a29cdc mb/pcengines/apu2/gpio_ftns.h: add comment about GPIO numbers
The mapping of the package GPIO numbers to the GPIO numbers on the GPIO
controller isn't a 1:1 one, so add a comment about that to avoid
confusion. Also change the comment style to match the style guide.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ie30bf5483ea2e2516d7e3fdd21ea9338362e526e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56808
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2021-09-03 15:41:00 +00:00
Felix Held 5d933c483f mb/pcengines/apu2/romstage: use proper GPIO configuration API
Also remove the unused amdblocks/acpimmio.h include in gpio_ftns.c.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: Michał Kopeć <michal.kopec@3mdeb.com>
Change-Id: If121941c8a6ba88913653192740997aeef426548
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56784
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-03 15:40:32 +00:00
Seunghwan Kim 923b16fbba mb/google/dedede/var/bugzzy: Configure DDI port A as MIPI DSI
Override DdiPortAConfig as MIPI DSI

BUG=b:192521391
BRANCH=None
TEST=Built test coreboot image and boot on bugzzy board

Change-Id: If308f9d69fea56176527e7b67f36b29c43adb525
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57107
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Henry Sun <henrysun@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-09-03 15:16:18 +00:00
Felix Held 2651d99133 drivers/intel/fsp2_0/Makefile: add condition for FSP-T CBFS file
Make adding the FSP-T file to CBFS depend on both ADD_FSP_BINARIES and
FSP_CAR Kconfig options being set. The FSP_T_FILE Kconfig option depends
on both, so also check if both are selected in the Makefile where it
tries to add the FSP-T to the CBFS.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Suggested-by: Furquan Shaikh <furquan@google.com>
Change-Id: Id347336f2751c6d871f31d89c30a1222037c2d69
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57220
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-09-03 14:45:41 +00:00
Ryan Chuang e895b2aa9d vc/mediatek/mt8195: Remove unused code
Remove unused drivers and some fast calibration implementations
to align with the latest MTK memory reference code.

Signed-off-by: Ryan Chuang <ryan.chuang@mediatek.corp-partner.google.com>
Change-Id: I3b235cbceb231898f00fce7905f596eab54ca595
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57275
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-03 07:10:36 +00:00
Taniya Das d37aeb1bcb soc/qualcomm/common: clock: Add support for common clock driver
The clock driver supports configuring the general purpose PLLs,
configuring the root clock generator (RCG), enable clock branch, enable
gdsc and also the block resets.

The common clock driver exposes PLL configuration functions and also
different Agera PLL enable functions for the CPU PLLs.

While at it, the common driver also supports reset of subsystems like
AOP and SHRM.

SC7180 clock driver is also refactored to use the common clock
driver APIs.

BUG=b:182963902
TEST=Validated on qualcomm sc7180 and sc7280 development board.

Change-Id: I03d1b4a2fb90303c7259ec08f312d78b4e33ec39
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56588
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
2021-09-03 06:04:18 +00:00
Taniya Das 310edec617 qualcomm/sc7180: Clean up drivers with common clock
As we move to use the common clock driver, the sc7180 clock driver,
watchdog and display drivers requires few cleanups, thus update the
impacted drivers.

Earlier the display client is expected to provide 2n divider value,
as the divider value in register is in form "2n-1".
mdss_clk_cfg.div = half_divider ? (half_divider - 1) : 0;

The older convention in the upcoming patches would be replaced with
the common macro of QCOM_CLOCK_DIV, thus need the divider needs to
be updated.
mdss_clk_cfg.div = half_divider ? QCOM_CLOCK_DIV(half_divider) : 0;

To accommodate impacting the functionality, the half_divider is taken
care in the clock driver.

BUG=b:182963902
TEST=Validated on qualcomm sc7180 development board

Change-Id: Ic334fd0d43e5b4b1e43a27d5db7665f0bc151d66
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56587
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
2021-09-03 06:03:08 +00:00
Subrata Banik a74eb4f6e8 mb/intel/adlrvp: Move common Kconfig from mb Kconfig.name to Kconfig
CONFIG_DRIVERS_INTEL_MIPI_CAMERA and CONFIG_SOC_INTEL_COMMON_BLOCK_IPU
are getting selected for all ADLRVPs irrespective of ADL-P and ADL-M
(internal and external EC SKUs) hence, select those Kconfigs from
mainboard Kconfig rather Kconfig.name.

Also, select DRIVERS_INTEL_SOUNDWIRE as per alphabetical order.

TEST=No changes are seen while the .config file is getting auto
generated.

Change-Id: I62d5ec19c3364da79ebe7287b1b3d6eb2a0efca0
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57314
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-09-03 01:23:15 +00:00
Angel Pons b4d3a14360 skylake: Default to `BOARD_TYPE_DESKTOP` for PCH-H
Set the `UserBd` FSP-M UPD to `BOARD_TYPE_DESKTOP` by default on PCH-H.
Remove now-redundant mainboard code to set the `UserBd` UPD.

Change-Id: I349abe5d89f562c158ce9baadbca2b2f56695846
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57261
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-03 00:12:37 +00:00
Angel Pons 8f4098bb3d mb/prodrive/hermes: Do not overwrite `IedSize` UPD
SoC code already sets this UPD to `CONFIG_IED_REGION_SIZE`, which
defaults to 0x400000 for soc/intel/cannonlake.

Change-Id: I6587e17a4a3425c561cffe6e3df0d932a2458168
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57260
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
2021-09-03 00:12:01 +00:00
Angel Pons 7b378b1469 mb/prodrive/hermes: Use `BOARD_TYPE_SERVER` define
Change-Id: I291dc71bb6e3888b71ebce315f9ad09ccbc4a9a7
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57259
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
2021-09-03 00:11:35 +00:00
Angel Pons 1b3462749b src/*: Specify type of `DIMM_MAX` once
Specify the type of the `DIMM_MAX` Kconfig symbol once.

Change-Id: I2e86baaa8bd50c7b82c399fde5dcea05da6b4307
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57258
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Crawford <tcrawford@system76.com>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
2021-09-03 00:11:02 +00:00
Angel Pons 28a16d960c src/*: Specify type of `DIMM_SPD_SIZE` once
Specify the type of the `DIMM_SPD_SIZE` Kconfig symbol once.

Change-Id: I619833dbce6d2dbe414ed9b37f43196b4b52730e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57257
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-09-03 00:10:33 +00:00
Martin Roth 349f13071d mb/google/guybrush: Update PCIe WWAN path for WWAN PCIe check
variant_has_pcie_wwan() was always coming back as disabled because
find_dev_nested_path() couldn't find the device until the domain was
added to the array.

BUG=b:193036827
TEST=Boot guybrush with PCIe & USB WWAN devices.

Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: Id94fa0b0ff5c29fa447e869220d27ccfe61438c6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57315
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-09-02 23:38:35 +00:00
Iru Cai cd8267b69c Documentation: add Intel Broadwell
Change-Id: I0b1c29162a64030b5c100368f2471702e22b8311
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54744
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-09-02 23:33:39 +00:00
Nick Vaccaro dae7d81a3c mb/google/brya: reduce RW_MRC_CACHE size to 64K
The RW_MRC_CACHE only needs to be 64K for Brya.

BUG=none
TEST="emerge-brya coreboot chromeos-bootimage", flash and boot
brya0 to kernel.

Change-Id: I74365b795e184b92f483ae2bf862791e235c5362
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56989
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-02 23:31:32 +00:00
Sugnan Prabhu S d70f481891 wifi: Add support for DSM methods for intel wifi card
Add support for DSM methods as per the connectivity document
559910_Intel_Connectivity_Platforms_BIOS_Guidelines_Rev6_4.pdf

BUG=b:191720858
TEST=Check the generated SSDT tables for DSM methods

Change-Id: Ie154edf188531fe6c260274edaa694cf3b3605d3
Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56751
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-02 22:55:37 +00:00
Sugnan Prabhu S cc50770cd0 wifi: Add support for wifi time average SAR config
Add support for the WTAS ACPI BIOS configuration table as per the
connectivity document:
559910_Intel_Connectivity_Platforms_BIOS_Guidelines_Rev6_4.pdf

BUG=b:193665559
TEST=Generated SAR file with the WTAS related configuration values and
verified that the SSDT has the WTAS ACPI table.

Change-Id: I42cf3cba7974e6db0e05de30846ef103a15fd584
Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57061
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-02 22:55:00 +00:00
Sugnan Prabhu S d1fc832c52 wifi: Add support for per-platform antenna gain
Add support for the PPAG ACPI BIOS configuration table as per the
connectivity document:
559910_Intel_Connectivity_Platforms_BIOS_Guidelines_Rev6_4.pdf

BUG=b:193665559
TEST=Generated SAR file with the PPAG related configuration values and
verified that the SSDT has the PPAG ACPI table.

Change-Id: Ie8d25113feeeb4a4242cfd7d72a5091d2d5fb389
Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57060
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-02 22:54:35 +00:00
Sugnan Prabhu S fcb4f2d77e wifi: Add support for new revisions of SAR table entries
Existing SAR infrastructure supports only revision 0 of the SAR tables.
This patch modifies it to extend support for intel wifi 6 and wifi 6e
configurations as per the connectivity document:
559910_Intel_Connectivity_Platforms_BIOS_Guidelines_Rev6_4.pdf

The SAR table and WGDS configuration block sizes were static in the
legacy SAR file format. Following is the format of the new binary file.

+------------------------------------------------------------+
| Field     | Size     | Description                         |
+------------------------------------------------------------+
| Marker    | 4 bytes  | "$SAR"                              |
+------------------------------------------------------------+
| Version   | 1 byte   | Current version = 1                 |
+------------------------------------------------------------+
| SAR table | 2 bytes  | Offset of SAR table from start of   |
| offset    |          | the header                          |
+------------------------------------------------------------+
| WGDS      | 2 bytes  | Offset of WGDS table from start of  |
| offset    |          | the header                          |
+------------------------------------------------------------+
| Data      | n bytes  | Data for the different tables       |
+------------------------------------------------------------+

This change supports both the legacy and the new format of SAR file

BUG=b:193665559
TEST=Checked the SSDT entries for WRDS, EWRD and WGDS with different
binaries generated by setting different versions in the config.star

Change-Id: I08c3f321938eba04e8bcff4d87cb215422715bb2
Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56750
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-02 22:53:26 +00:00
Meera Ravindranath 93ca873f20 mb/google/brya: Fix Idle S0ix issue due to dynamic GPIO PM disabled
GPIO PM was disabled for brya to evaluate if longer interrupt pulses
are required for ADL. Since ADL requires 4us long pulses (EDS:626817),
GPIO PM can be enabled. All devices currently tested on brya support 4us
long pulses. This change drops the GPIO PM override and re-enables
dynamic GPIO PM.

TEST=Boot brya to OS, ensure no TPM errors.

Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Change-Id: I0c7b66b5514d8b80775ab7578ce7b12181af7882
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56926
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-02 22:32:13 +00:00
Julius Werner 1f84b2c025 drivers/mipi: Make orientation a property of the mainboard, not panel
It doesn't make sense to store the orientation field directly in the
panel information structure, which is supposed to be reuseable between
different boards. The thing that determines orientation is how that
panel is built into the board in question, which only the board itself
can know. The same portrait panel could be rotated left to be used as
landscape in one board and rotated right to be used as landscape in
another. This patch moves the orientation field out of the panel
structure back into the mainboards to reflect this.

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: If2b716aa4dae036515730c12961fdd8a9ac34753
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57324
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-02 21:43:11 +00:00
David Wu 14bb6f5dab mb/google/brya/variants/brask: Enable PCIE port 7 for Ethernet
Enable PCIE port 7 using clk 6 for RTL8125 Ethernet

BUG=b:193750191
BRANCH=None
TEST=build pass

Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: Ic60a66dbd6ad87cf9c0de85ca7df4d854c371bf5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57273
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-02 15:31:34 +00:00
Tim Crawford f496286bdc soc/intel/tigerlake: Set MAX_CPUS for TGL-H to 16
TGL-H supports up to 8 cores (16 threads).

Change-Id: I2ee1be37f564bf1b6249a6c223be093747c38ab5
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57267
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-02 15:31:12 +00:00
Tim Crawford f05bd8830d mb/system76/*: cmos.layout: Reserve century byte
Windows will write to the century byte (0x32), causing the option table
checksum to be invalid and reset all options to their default values.
Move options and checksum to start after the century byte.

Change-Id: Ia395acacda1e251251c880587bbf61d7ee81ba3d
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57055
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
2021-09-02 15:28:31 +00:00
Kevin Chiu e4859b7406 mb/google/guybrush/nipperkin: update DRAM table
MT53E512M32D2NP-046 WT:E
K4U6E3S4AA-MGCR
H9HCNNNCPMMLXR-NEE
K4UBE3D4AA-MGCR

BUG=b:194031783
BRANCH=guybrush
TEST=emerge-guybrush coreboot chromeos-bootimage

Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Change-Id: I71ceaf0a2738584d316a5b7cc51539821b430128
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57197
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
2021-09-02 14:54:47 +00:00
Peter Marheine 5d91bdd312 mb/google/zork: correct MST probes
It turns out that putting a device ref in an overridetree at a different
point in the tree will generate a duplicate device definition, such that
the change introducing this support was ignoring the device presence
specified by overridetree.cb and only using the baseboard configuration.
I believe testing of that change was not redone after the baseboard was
changed to disable the MST, so that conflicting behavior was not
noticed.

The incorrect behavior generated a disabled device for the MST at the
location specified by the baseboard, and one with the probe as a child
of the soc. At runtime this did a fw_config probe of the "I2C 00:4a"
device, and later probed a different "I2C 00:4a" which was already
disabled. As the disabled one came later, it seems to have completely
disabled the MST, discarding the results of the variant-specific probe.

BUG=b:185862297
TEST=10EC2141 device is now present on a Dali berknip
BRANCH=zork

Change-Id: I2a8feb544f3fc198fe6313b226ad8995aad31c3e
Signed-off-by: Peter Marheine <pmarheine@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57298
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-02 14:53:59 +00:00
Dun Tan 4a35940137 util/cbftool: Fix the bug in parsing Uefipayload with extended header
The patch is to fix "Not a usable UEFI firmware volume" issue when
creating CBFS/flash image. This issue is caused by adding FvNameGuid
in UefiPayloadEntry.fdf in EDKII. There is an ext header between header
of Fv and header of PayloadEntry in Fv with FvNameGuid. The ext header
causes the UefiPayloadEntry to be found incorrectly when parsing Fv.

Commit in EDKII: 4bac086e8e007c7143e33f87bb96238326d1d6ba
Bugzila: https://bugzilla.tianocore.org/show_bug.cgi?id=3585

Signed-off-by: Dun Tan <dun.tan@intel.com>
Change-Id: Id063efb1c8e6c7a96ec2182e87b71c7e8b7b6423
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57296
Reviewed-by: Ray Ni <ray.ni@intel.com>
Reviewed-by: King Sumo <kingsumos@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-02 06:07:08 +00:00
Jakub Czapiga 6f3fd6358f tests: Add lib/cbfs-verification-test test case
This commit adds test case for lib/cbfs verification mechanisms.

Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: I1d8cbb1c2d0a9db3236de065428b70a9c2a66330
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56601
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-02 00:31:02 +00:00
Julius Werner 6813d561b2 cbfs: Make sure all cases of single file header corruption are isolated
The new CBFS stack was written to try to isolate cases of single file
corruption as far as possible and still make other files avaialble (at
least as long as verification is disabled and they can still be found at
all). For most cases of header corruption, it will just continue trying
to parse the next file. However, in cases where parts of the file extend
beyond the end of the rdev, we have been relying on the range checking
of the rdev API rather than doing it explicitly.

This is fine in general, but it causes the problem that these errors
cannot be distinguished from I/O errors, and I/O errors always make the
whole cbfs_walk() fail. That means we will not return a successful
result from cbfs_mcache_build(), and leads to an odd discrepancy in how
certain kinds of corrupted CBFSes are treated with and without mcache.
This patch adds an explicit range check to make the behavior consistent.

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: Ice2b6960284bd0c19be35b0607e5e32791e7a64c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57271
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
2021-09-01 23:57:14 +00:00
Jakub Czapiga 7c6081e02b tests: Improve test output readability
When running multiple tests, e.g. by using unit-tests target, it is hard
to differentiate, which output comes from which file and/or
configuration. This patch makes the output easier to analyze and
understand by using new wrapper macro cb_run_group_tests(). This macro
uses __TEST_NAME__ value (containing test path and Makefile test name)
as a group name when calling cmocka group runner.

Example:
 Test path: tests/lib/
 Makefile test name: cbmem_stage_cache-test
 Test group array name: tests
 Result: tests/lib/cbmem_stage_cache-test(tests)

Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: I4fd936d00d77cbe2637b857ba03b4a208428ea0d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57144
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-09-01 19:38:09 +00:00
Karthikeyan Ramasubramanian c2310a16ad soc/amd/cezanne: Increase the FSP_M_SIZE configuration
On mainboards with Cezanne SOC, serial enabled FSP_M binary size is
greater than the size allocated in DRAM. Increase the allocated size for
FSP_M binary in DRAM to handle both debug and release FSP_M binaries.
Also adjust the verstage load address accordingly.

BUG=None
TEST=Build and boot to OS in guybrush with both debug and release FSP_M.
Perform warm, cold reboot and suspend/resume cycling for 10 iterations.

Change-Id: Ic6f90041e258039e691cbdb3a978cfe1f782642a
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57293
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-01 19:36:20 +00:00
Jakub Czapiga c35659d930 libpayload: Move EXTRA_CFLAGS to enable option override
Before this patch EXTRA_CFLAGS were placed before many other options.
This made overriding impossible even, when necessary. This patch moves
EXTRA_CFLAGS to be placed after original CFLAGS, thus making option
overriding possible.

Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: If8394b151696eee4bd736d2fb1ad340209e05fbb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57181
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-01 19:34:20 +00:00
Wisley Chen b8461aab52 mb/goog/brya: Add probed fw_configs to SMBIOS OEM strings
Enable this feature, and it can use the probe statement in devicetree
to cache of fw_config field as oem string.

BUG=b:191931762
TEST=With CBI FW_CONFIG field set to 0x8,
set probe AUDIO MAX98390_ALC5682I_I2S_4SPK in devicetree

dmidecode -t 11
OEM Strings
   AUDIO-MAX98390_ALC5682I_I2S_4SPK

Change-Id: I93cd9ef2d1ad963e66c422cff17b083abf731046
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57142
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-01 19:32:43 +00:00
Furquan Shaikh b9c22e0965 util/sconfig: Compare probe conditions for override device match
When the override functionality looks for device match, check that
the probe list for both the devices matches exactly if probe list
exists for the base device. This ensures that if there are two devices
with same identity (e.g. I2C address or USB port #) but using
different properties (registers) controlled by different probe
statements, then the two devices are not incorrectly matched as the
same device.

The check for base device having a probe list is performed before
comparing the probe lists because a base device might not really have
any probe requirements at all. So, when overriding such a device,
there is no need to check for the probe list match.

BUG=b:187193527
TEST=Verified by adding two I2C devices in the override tree with the
same I2C address and chip but different probe statements and confirmed
that both the devices are present in generated static.c file.

Change-Id: Ib18868b336cf4ffc9aa38aee7c6f333a35d32fce
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57111
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-09-01 19:20:05 +00:00