Commit Graph

31099 Commits

Author SHA1 Message Date
Subrata Banik 319b096869 soc/intel/icelake: Remove unused headers
This patch removes inclusion of unused headers from soc/intel/icelake

Change-Id: Icb653dee7992538aadf98d84adadd081f816fd01
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36536
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-04 08:20:11 +00:00
Subrata Banik 6c1b18090d soc/intel/icelake: Skip BIOS OpRom execution based on CONFIG_RUN_FSP_GOP
This patch replaces BIOS OpRpm execution checks from CONFIG_INTEL_GMA_ADD_VBT
to CONFIG_RUN_FSP_GOP as adding VBT files doesn't mean GFX PEIM is going
to execute to initialize IGD.

Change-Id: Ic76529ba11f621f644d4472be6cbbc34682f00bf
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36532
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-11-04 08:20:03 +00:00
Subrata Banik 522b7c0324 soc/intel/icelake: Clean up report_cpu_info() function
This patch makes below clean up for report_cpu_info() function
1. Replace cpu_string with cpu_not_found
2. Assign default string "Platform info not available" to cpu_not_found string
3. Add array out of bound check while skiping leading white space in cpu brand
string name

Change-Id: I41c76eb93f0c5229c4a49aa041339b8ad51ad34a
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36531
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-04 08:19:50 +00:00
Angel Pons bda870242e cpu/x86/mtrr/xip_cache.c: Fix inconsistent message
Change-Id: Ic99e61632664f86cc12507f2ddffa364fdd79202
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36585
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-03 20:48:18 +00:00
Arthur Heymans 5ff6a6af0e mb/intel/{i82801gx,x4x}: Don't select ASPM options
These are likely not properly set up and L1 is not even supported on
the desktop variant of the southbridge.

This fixes observed instability on some PCIe GPUs.

Change-Id: I70d3536984342614a6ef04a45bc6591e358e3abe
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36576
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-03 19:22:57 +00:00
Arthur Heymans d05f57cfcb arch/arm64: Pass cbmem_top to ramstage via calling argument
This solution is very generic and can in principle be implemented on
all arch/soc. Currently the old infrastructure to pass on information
from romstage to ramstage is left in place and will be removed in a
follow-up commit.

Nvidia Tegra will be handled in a separate patch because it has a
custom ramstage entry.

Instead trying to figure out which files can be removed from stages
and which cbmem_top implementations need with preprocessor, rename all
cbmem_top implementation to cbmem_top_romstage.

Mechanisms set in place to pass on information from rom- to ram-stage
will be replaced in a followup commit.

Change-Id: I86cdc5c2fac76797732a3a3398f50c4d1ff6647a
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36275
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-11-03 11:19:24 +00:00
Arthur Heymans 2f389f151a arch/arm: Pass cbmem_top to ramstage via calling argument
This solution is very generic and can in principle be implemented on
all arch/soc.

Instead trying to figure out which files can be removed from stages
and which cbmem_top implementations need with preprocessor, rename all
cbmem_top implementation to cbmem_top_romstage.

Mechanisms set in place to pass on information from rom- to ram-stage
will be placed in a followup commit.

Change-Id: If31f0f1de17ffc92c9397f32b26db25aff4b7cab
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36145
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-11-03 11:19:04 +00:00
Arthur Heymans 7c9a0e8a9c arch/x86: Use the stage argument to implement cbmem_top
Currently all stages that need cbmem need an implementation of a
cbmem_top function.  On FSP and AGESA platforms this proves to be
painful and a pointer to the top of lower memory if often passed via
lower memory (e.g. EBDA) or via a PCI scratchpad register.

The problem with writing to lower memory is that also need to be
written on S3 as one cannot assume it to be still there. Writing
things on S3 is always a fragile thing to do.

A very generic solution is to pass cbmem_top via the program argument.
It should be possible to implement this solution on every
architecture.

Instead trying to figure out which files can be removed from stages
and which cbmem_top implementations need with preprocessor, rename all
cbmem_top implementation to cbmem_top_romstage.

TESTED on qemu-x86.

Change-Id: I6d5a366d6f1bc76f26d459628237e6b2c8ae03ea
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36144
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2019-11-03 11:18:31 +00:00
Kyösti Mälkki 463ad5169d boot_state: Reduce precision of reported times
When diffing boot logs, lines reporting times spent in each
boot_state always get highlighed due the little fluctuation
in microsecond-scale. Reduce the logged precision to
milliseconds to avoid that.

Change-Id: I7a27d6c250d8432131f30e9a4869cb45ad75d9fd
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36528
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-11-03 06:17:20 +00:00
Kyösti Mälkki ddd6ca78a1 intel/quark: Switch to TSC_MONOTONIC_TIMER
Change-Id: I5ea899863c5b9ed516a55ba2e7524dd33a6f651d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36554
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-03 06:16:24 +00:00
Kyösti Mälkki 5b15e01035 intel/broadwell: Switch to TSC_MONOTONIC_TIMER
Change-Id: I01b73e20c8af1b00175dc6d9ee56e6b33ac5768d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36537
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-03 06:15:59 +00:00
Kyösti Mälkki 0d6ddf8da7 cpu/x86/tsc: Flip and rename TSC_CONSTANT_RATE to UNKNOWN_TSC_RATE
The x86 timers are a bit of a mess. Cases where different stages use
different counters and timestamps use different counters from udelays.

The original intention was to only flip TSC_CONSTANT_RATE Kconfig
to NOT_CONSTANT_TSC_RATE. The name would be incorrect though, those
counters do run with a constant rate but we just lack tsc_freq_mhz()
implementation for three platforms.

Note that for boards with UNKNOWN_TSC_RATE=y, each stage will have a
slow run of calibrate_tsc_with_pit(). This is easy enough to fix with
followup implementation of tsc_freq_mhz() for the platforms.

Implementations with LAPIC_MONOTONIC_TIMER typically will not have
tsc_freq_mhz() implemented and default to UNKNOWN_TSC_RATE. However,
as they don't use TSC for udelay() the slow calibrate_tsc_with_pit()
is avoided.

Because x86/tsc_delay.tsc was using two different guards and nb/via/vx900
claimed UDELAY_TSC, but pulled UDELAY_IO implementation, we also switch
that romstage to use UDELAY_TSC.

Change-Id: I1690cb80295d6b006b75ed69edea28899b674b68
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33928
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-11-03 06:15:35 +00:00
Arthur Heymans ea2bec2c4b nb/intel/gm45: Add VBOOT support
Change-Id: I943723da7167a47f514eda19fb9b71b8f56c2d32
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35997
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-02 16:15:42 +00:00
Arthur Heymans 4f7568b126 cpu/intel/core2: Cache XIP romstage with C_ENVIRONMENT_BOOTBLOCK.
Tested on Thinkpad X200: the romstage execution speeds are back to
pre-C_ENVIRONMENT_BOOTBLOCK levels.

Change-Id: Id0b50d2f56e7cc0e055cdc8b9aa28794327eca28
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35994
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-02 16:15:33 +00:00
Arthur Heymans 47be2d9f70 cpu/x86: Add a prog_run hook to set up caching of XIP stages
Some platforms lack a non-eviction mode and therefore caching the
whole ROM to speed up XIP stages can be dangerous as it could result
in eviction if too much of the ROM is being accessed. The solution is
to only cache a region, about the size of the stage that the bootblock
is about to load: verstage and/or romstage.

TODO: now a limit of 256KiB is set for the total amount of cache that
can be used. This should fit most use cases for the time being.

Change-Id: I94d5771a57ffd74d53db3e35fe169d77d7fbb8cd
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35993
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-11-02 16:15:19 +00:00
Michael Niewöhner d60089b7b1 soc/intel/skylake: set FSP param to enable or skip GOP
Set the FSP parameter PeiGraphicsPeimInit according to RUN_FSP_GOP to
enable or skip GOP.

Change-Id: I5731003c8a094c4d108efbea14d31d335758bbb7
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36350
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-02 16:13:24 +00:00
Kyösti Mälkki de09679c13 timestamps: COLLECT_TIMESTAMPS is mostly optional
It is a user-visible option and enabled by default for ARCH_X86,
some consider it as debugging aid only. Therefore platform design
should not depend on it.

It must remain selected with CHROMEOS and boards are allowed
to explicitly select it as well.

For siemens/mc_bdx1,mc_aplX boot time will be increased due
the use of get_us_since_boot() with COLLECT_TIMESTAMPS=n.
When unable to determine if N seconds has elapsed from boot,
this turns into a delay of N seconds.

Change-Id: I6ee4195d266440143344781d39db9578cd8bdcb3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36527
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2019-11-02 13:36:11 +00:00
Michael Niewöhner 836994e083 soc/intel/common/pch: move EBDA Kconfig to soc level
EBDA is not PCH related, thus move the Kconfig to the appropriate socs.

Change-Id: I216871ad1a8dd5bc294062a4e9b54eb51f71b781
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36409
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-11-02 13:27:15 +00:00
Michael Niewöhner 48fb573e1f soc/intel/skylake: set LT_LOCK_MEMORY at end of POST
Use the new common function to set LT_LOCK_MEMORY at end of POST to
protect SMM in accordance to Intel BWG.

Tested successfully on X11SSH-M by disabling SGX and running chipsec.

Change-Id: I623e20a34667e4df313aeab49bb57907ec75f8a8
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36355
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-11-02 13:09:42 +00:00
Michael Niewöhner 7253e7a135 soc/intel: common,apl,skl: remove orphaned memory locking API
Remove the now orphaned memory locking API that was replaced by a
Kconfig-based approach.

Change-Id: Iebc45f514c576d77f90f558151d25c21f0554779
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36515
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-11-02 13:09:32 +00:00
Michael Niewöhner c5fc753b13 soc/intel/common: sgx: use cpu_lt_lock_memory in sgx setup
Use the new common function to set LT_LOCK_MEMORY prior to SGX
activation based on Kconfig.

Change-Id: Iefec0e61c7482a70af60dabc0bec3bf712d8b48a
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36354
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-11-02 13:09:25 +00:00
Michael Niewöhner c169a4751f soc/intel/skylake: select the new SGX Kconfig option for LT_LOCK_MEMORY
Select the new SGX Kconfig option for LT_LOCK_MEMORY.

Change-Id: I8b422ae50d11815ead10bfd5a8b47a13daa82821
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36514
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-11-02 13:09:19 +00:00
Michael Niewöhner 4e8db0fa32 soc/intel/common: sgx: add new Kconfig option for setting LT_LOCK_MEMORY
Add new Kconfig option for setting LT_LOCK_MEMORY.

Change-Id: I1b232e34a1288ce36a3dce2ab0293c26f10f3881
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36513
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-11-02 13:09:15 +00:00
Kyösti Mälkki 2ca11a527c soc/amd/stoneyridge: Remove UDELAY_LAPIC_FIXED_FSB
We only need this defined with udelay() implementation
on top of LAPIC_MONOTONIC_TIMER.

Change-Id: I490245fa0d57de3a6e8609e735f668626cf1201e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36526
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-02 06:28:53 +00:00
Kyösti Mälkki 432516586e cpu/x86: Move calibrate_tsc_with_pit() to drivers/pc80
Change-Id: Ia8d8dc23ee0b51d62c83f5ba640b3a9aea4e744b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36507
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2019-11-02 06:28:28 +00:00
Arthur Heymans e1c0cb737c mb/emulation/*-riscv: Initialize cbmem in romstage
It is expected that cbmem is initialized in romstage. The qemu-riscv
target did not perform that correctly. Fix this omission.

Change-Id: I00f8e3b315e57a5c042889f48450f79d263f24b1
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36446
Reviewed-by: Philipp Hug <philipp@hug.cx>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-01 19:41:51 +00:00
Wim Vervoorn 3e9061e27c mb/facebook/fbg1701: Add public key to bootblock_verify_list
The public key was not verified during the verified boot operation.
This is now added. The items in the manifest are now fixed at 12 as
we always have the postcar stage.

BUG=N/A
TEST=tested on facebook fbg1701

Change-Id: I85fd391294db0ea796001720c2509f797be5aedf
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36504
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-01 13:56:21 +00:00
Elyes HAOUAS 9dfa60aaee src/Kconfig: Drop unused HAVE_POSTCAR
Change-Id: Id8dcba8e83b0f896c26ab684d857908c6f272453
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36497
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-11-01 11:58:59 +00:00
Arthur Heymans b43ec47ed3 console/kconfig: Move ONBOARD_VGA_IS_PRIMARY to 'devices'
This has nothing to do with console options.

This also improves the help text to reflect what it actually does.

Change-Id: I039f4f6bbe144769d6a362192b225838ed3d9d43
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32042
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-11-01 11:58:40 +00:00
Elyes HAOUAS 57248c2b8c mb/apple/macbook21: Use DEBUG_RAM_SETUP
Also, the loglevel is never set to value of > 8.

Change-Id: Ief29e07be6ac075956bf0f9aee85b14eb89af44c
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36496
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Evgeny Zinoviev <me@ch1p.io>
2019-11-01 11:57:44 +00:00
Wim Vervoorn 7011e546e1 mb/facebook/fbg1701: Remove confusing text boxes from menu
The Kconfig contained some items that were only intended to
set a default and that now were displayed in two locations
in the menuconfig.

BUG=N/A
TEST=build

Change-Id: If5d9c993c03a0e901fd6c2a2107a6be6b94d063b
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36481
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-01 11:55:14 +00:00
Eric Lai 7aed33e95e mb/google/drallion: Add second touch pad support
Add second source touch pad with i2c address 0x15.

BUG=b:142629138
BRANCH=N/A
TEST=check new touch pad can work properly

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Icc58dbcf307f11c368a1a5408f32111ed5841d39
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36501
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com>
Reviewed-by: Mathew King <mathewk@chromium.org>
2019-11-01 11:54:25 +00:00
Praveen Hodagatta Pranesh 55e5cb8d4e mb/intel/saddlebrook: Enable Chipset_lockdown coreboot config
This patch enables lockdown configuration for saddlebrook platform

BUG=None
TEST=Boot to Linux on saddlebrook and verified MRC is restored on warm, cold,
	resume boot path's.

Change-Id: Ia324c118b0c8e72b66a757dee5be43ba79abbeab
Signed-off-by: Praveen Hodagatta Pranesh <praveenx.hodagatta.pranesh@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36451
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-11-01 11:54:12 +00:00
Praveen Hodagatta Pranesh 242a03365d mb/intel/saddlebrook: Select coreboot MP init
use coreboot MP init for saddlebrook by default.

BUG=None
TEST=Boot till yocto linux 2.7 on saddlebrook and verified the AP's
    proper initialization using 'cat /proc/cpuinfo' command.

Change-Id: I2db2fe92c8ba0e649dccf95ce804a97ae4a05603
Signed-off-by: Praveen Hodagatta Pranesh <praveenx.hodagatta.pranesh@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36450
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Michael Niewöhner
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-11-01 11:53:55 +00:00
Patrick Rudolph 5666c29df1 Documentation: Fix typo
The document isn't included in any toc-tree due to a typo.

Change-Id: Ic1491dde2d48b5d004fc28c743bbee6de12f433c
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36540
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-01 11:53:01 +00:00
Maxim Polyakov c56ca6ba17 soc/skylake/vr_config: fix VR config for KBL-U CPUs
These changes are in accordance with the documentation:
[1] page 106, 7th Generation Intel(R) Processor Families for U/Y
    Platforms and 8th Generation Intel(R) Processor Family for U Quad
    Core and Y Dual Core Platforms. Datasheet, Volume 1. January 2019.
    Document Number: 334661-006

Change-Id: I5232a7a670b97d51ff3b3b71a08f25f961ac1d6f
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36058
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-01 11:51:31 +00:00
Subrata Banik 29f12e4d48 soc/intel/{cnl,icl,skl}: Move ipu.asl into common/block/acpi
This patch creates a common instance of ipu.asl inside intel common
code (soc/intel/common/block/acpi/acpi) and ask cnl & icl soc code to
refer ipu.asl from common code block.

TEST=Able to build and boot Hatch and ICL DE system. Dump DSDT.asl to verify
Device(IMGU) presence after booting to OS.

Change-Id: I4d18571008c199fd5c3dbeed8cba9374520359b4
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36459
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-11-01 11:50:45 +00:00
Subrata Banik fa2f793957 soc/intel/{cnl,icl}: Move globalnvs.asl/nvs.h into common/block/
This patch creates a common instance of globalnvs.asl/nvs.h inside intel common
code (soc/intel/common/block/) and ask cnl & icl soc code to refer globalnvs.asl
and nvs.h from common code block.

TEST=Able to build and boot Hatch and ICL DE system. Dump DSDT.asl to verify
GNVS operation region presence after booting to OS.

Change-Id: Ia9fb12a75557bd7dc38f6d22ba2b32065d18b3ee
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36457
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Michael Niewöhner
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-11-01 11:50:31 +00:00
Subrata Banik 2715cdb3f3 soc/intel/{IA-CPU/SOC}: Move sleepstates.asl into southbridge/intel/common/acpi
This patch creates a common instance of sleepstates.asl inside intel common
code (southbridge/intel/common/acpi) and asks all IA CPU/SOC code to
refer sleepstates.asl from common code block.

TEST=Able to build and boot Hatch and ICL DE system. Dump DSDT.asl to verify
S0/S3/S4/S5 entries after booting to OS.

Change-Id: Ie2132189f91211df74f8b5546da63ded4fdf687a
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36463
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-01 11:50:03 +00:00
Subrata Banik 1e8f305957 soc/intel/{apl,cnl,dnv,icl,skl}: Move lpc.asl into common/block/acpi
This patch creates a common instance of lpc.asl inside intel common
code (soc/intel/common/block/acpi/acpi) and asks specific soc code to
refer lpc.asl from common code block.

Note: From ICL onwards Intel Bus Device 0:1f.0 is known as eSPI
rather than LPC.

TEST=Able to build and boot ICL DE system. Dump DSDT.asl to verify
Device(LPCB) device presence after booting to OS.

Change-Id: I266d6e667e7ae794377e4882791e3be933d35e87
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36455
Reviewed-by: Michael Niewöhner
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-01 11:49:48 +00:00
Himanshu Sahdev 96ca0d93d2 arch/acpi.h: Use the predefined typedef acpi_addr_t
Use already declared typedef and modify the usage accordingly.

Change-Id: Icc8413050bfae896d78605416aaaaa6a52eb39f1
Signed-off-by: Himanshu Sahdev <himanshusah@hcl.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36429
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-11-01 11:47:51 +00:00
Wim Vervoorn ac4896fbcb vendorcode/eltan/security: Use vb2 public key
Start using the vb2 public key format and process the signature
verification using the vb2 routines. This allows us to use the
futility to prepare the keys and eliminates the need for custom
tools.

BUG=N/A
TEST=tested on fbg1701 board

Change-Id: Id5d28595bbfb1f5ca5bca0fcfb06134bb1143f25
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36480
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2019-11-01 11:46:44 +00:00
Elyes HAOUAS eb48bb4fc8 mb/google/kukui: Unselect FATAL_ASSERT
FATAL_ASSERT is used for debugging purpos. Don't select it by default.

Change-Id: If4d521827f3d50fb662b89b24d00fb0517e7af2d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36508
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2019-11-01 11:45:47 +00:00
Arthur Heymans 340e4b8090 lib/cbmem_top: Add a common cbmem_top implementation
This adds a common cbmem_top implementation to all coreboot target.

In romstage a static variable will be used to cache the result of
cbmem_top_romstage.

In ramstage if CONFIG_RAMSTAGE_CBMEM_TOP_ARG is set a global variable
needs to be populated by the stage entry with the value passed via the
calling arguments. if CONFIG_RAMSTAGE_CBMEM_TOP_ARG is not set the
same implementation as will be used as in romstage.

Change-Id: Ie767542ee25483acc9a56785ce20a885e9a63098
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36273
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-11-01 11:44:51 +00:00
Wim Vervoorn 44874482fe mb/portwell/m107: Remove Intel wifi disable
The Intel wifi drivers were disabled by default. This should not
be done here as the baseboard defines if this present or not.

BUG=N/A
TEST=build

Change-Id: I364a821f8387d580b1fbfb7cf77b32a3a6dceebb
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36503
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-01 11:43:27 +00:00
Wim Vervoorn f6671a89c5 mb/portwell/m107: Add Kingston memory support
Add support for board revision 1.3 containing Kingston memory.

BUG=N/A
TEST=tested on portwell m107 module

Change-Id: I436698ee079952580c764e840ee0ad2e18ea8d3b
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36502
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2019-11-01 11:43:05 +00:00
Wim Vervoorn 34bc60b865 mb/facebook/fbg1701: Disable Intel wifi
The facebook fbg1701 never contains Intel wifi functionality
so this can be disabled.

BUG=N/A
TEST=tested on facebook fbg1701

Change-Id: Iab7dd760020cb7a9f7fea24812afb19bf5e62183
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36505
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2019-11-01 11:41:32 +00:00
Nico Huber 2e6a0f8052 lib/uuid: Add UUID parsing function
Implement a simple function that parses a canonical UUID string into the
common byte representation. Inspired by acpigen_write_uuid().

Change-Id: Ia1bd883c740873699814fde6c6ddc1937a40093e
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36297
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-11-01 11:38:22 +00:00
Elyes HAOUAS f71bb5d174 soc/{mediatek,sifive}: Remove unused 'include <arch/barrier.h>'
Change-Id: Ia15824effc8f846ff1143abe698c5a0546df7868
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36489
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-01 11:37:33 +00:00
Elyes HAOUAS 011688f861 soc/intel/fsp_baytrail: Remove unused 'barrier()'
Change-Id: I4330fd9b2ec6ca36beae3213642f7a4ae61f7dbe
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36488
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-11-01 11:37:19 +00:00