CB:59479 introduced a blank default statement. This is treated as an
error or warning on some older toolchains. Add a break statement on
default case.
BUG=None
TEST=Build the Guybrush mainboard.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I3d034cfebc8b8ae7d7024d41b4b2207cdeb083e8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59551
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Patrick Georgi <patrick@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
The device is a PCIe Gen1 to SD 3.0 card reader controller to be
used in the Chromebook. The datasheet name is GL9750S and the revision
is 01.
The patch disables ASPM L0s.
BUG=b:206014046
TEST=Verify GL9750 enters L1 by observing CLKREQ# de-asserts.
Signed-off-by: Ben Chuang <benchuanggli@gmail.com>
Change-Id: I6d60cef41baade7457a159d3ce2f8d2e6b66e71c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59429
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Introduce firmware-power-managed DSD ACPI property for TPM devices.
This property can be checked by the kernel TPM driver to override how
the TPM power states are managed. This is a tri-state flag, true,
false, or unset. So an enum used to keep the flag is unset by default.
When firmware-power-managed is true, the kernel driver will not send a
shutdown during s2idle/s0i3 suspend.
BUG=b:200578885
BRANCH=None
TEST=TPM shutdown is triggered on s0ix suspend on guybrush with patched
kernel
Change-Id: Ia48ead856fc0c6e637a2e07a5ecc58423f599c5b
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59479
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
The _DSC (Device State for Configuration) object evaluates to an integer
may be used to tell Linux the highest allowed D state for a device
during probe. The support for _DSC requires support from the kernel
bus type if the bus driver normally sets the device in D0 state for
probe.
The D states and thus also the allowed values for _DSC are listed below.
Number State Description
0 D0 Device fully powered on
1 D1
2 D2
3 D3hot
4 D3cold Off
More details can be found here https://lkml.org/lkml/2021/10/25/397
BUG=none
BRANCH=none
TEST=Add corresponding field in brya, boot and dump SSDT to check if
_DSC field is as per expectation.
Name (_ADR, Zero) // _ADR: Address
Name (_HID, "OVTI8856") // _HID: Hardware ID
Name (_UID, Zero) // _UID: Unique ID
Name (_DDN, "Ov 8856 Camera") // _DDN: DOS Device Name
Method (_STA, 0, NotSerialized) // _STA: Status
{
Return (0x0F)
}
Method (_DSC, 0, NotSerialized)
{
Return (0x04)
}
Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com>
Change-Id: I5471f144918413a2982f86beaf3dbf7e4e66cc9b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58767
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
So far POST codes were mapped on IO port 0x80 inside the NC FPGA which
was connected via the LPC bus to the host CPU. On recent x86 generations
the LPC bus was replaced with eSPI and not all Siemens boards have the
eSPI routed to the NC FPGA. In order to have POST codes visible on those
boards the display is accessible via PCI in addition.
This patch adds the feature of sending the POST codes to the NC FPGA via
a PCI mapped register.
Change-Id: Ie15686de49cface17830365d78fe7c54cce183a0
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59346
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Change to use MAX_DSAR_SET_COUNT which WLAN driver always expects 3
no matter what the revision is for EWRD.
It will pass the WLAN driver check then to retrieve the data properly.
BUG=b:204414616
TEST= tested on brya with DRTU tool to verify if SAR table is
read properly or not.
Change-Id: I18e7d5f658bbf42b7eeed3da330508f14b86c0f8
Signed-off-by: Matt Chen <matt.chen@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58951
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kane Chen <kane.chen@intel.corp-partner.google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Currently, the MMCONF Kconfigs only support the Enhanced Configuration
Access mechanism (ECAM) method for accessing the PCI config address
space. Some platforms have a different way of mapping the PCI config
space to memory. This patch renames the following configs to
make it clear that these configs are ECAM-specific:
- NO_MMCONF_SUPPORT --> NO_ECAM_MMCONF_SUPPORT
- MMCONF_SUPPORT --> ECAM_MMCONF_SUPPORT
- MMCONF_BASE_ADDRESS --> ECAM_MMCONF_BASE_ADDRESS
- MMCONF_BUS_NUMBER --> ECAM_MMCONF_BUS_NUMBER
- MMCONF_LENGTH --> ECAM_MMCONF_LENGTH
Please refer to CB:57861 "Proposed coreboot Changes" for more
details.
BUG=b:181098581
BRANCH=None
TEST=./util/abuild/abuild -p none -t GOOGLE_KOHAKU -x -a -c max
Make sure Jenkins verifies that builds on other boards
Change-Id: I1e196a1ed52d131a71f00cba1d93a23e54aca3e2
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57333
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
In the non-XIP world, FSP is normally memmapped and then decompressed.
The AMD SPI DMA controller can actually read faster than mmap. So by
reading the contents into a buffer and then decompressing we reduce boot
time.
BUG=b:179699789
TEST=Boot guybrush and see 30ms reduction in boot time
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I28d7530ae9e50f743e3d6c86a5a29b1fa85cacb6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58987
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This option will allow setting the FSP alignment in CBFS.
BUG=b:179699789
TEST=Boot with and without the option set and verify -a option was
passed.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I4533f6c9d56bea6520aa3aa87dd49f2144a23850
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58986
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
AMD platforms pass in the base address to cbfs tool:
fspm.bin-options: -b $(CONFIG_FSP_M_ADDR)
There is no technical reason not to allow FSP-M to be relocated when
!XIP. By allowing this, we no longer need to pass in the base address
into cbfstool when adding fspm.bin. This enables passing in the
`--alignment` argument to cbfs tool instead. cbfstool currently has a
check that prevents both `-b` and `-a` from being passed in.
BUG=b:179699789
TEST=Boot guybrush to OS
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I797fb319333c53ad0bbf7340924f7d07dfc7de30
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58984
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
elog init requires doing a lot of SPI transactions. This change makes it
clear how long we spend initializing elog.
BUG=b:179699789
TEST=Boot guybrush and see elog init timestamps
114:started elog init 3,029,116 (88)
115:finished elog init 3,071,281 (42,165)
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ia92372dd76535e06eb3b8a08b53e80ddb38b7a8f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58957
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The `find_resource` function will never return null (will die instead).
In cases where the existing code already accounts for null pointers, it
is better to use `probe_resource` instead, which returns a null pointer
instead of dying.
Change-Id: Ia9a4b62c857f7362d67aee4f9de3bb2da1838394
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58908
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Add backlight support in ps8640 through the AUX channel using eDP
DPCD registers.
BUG=b:202966352
BRANCH=trogdor
TEST=verified firmware screen works on homestar rev4
Change-Id: Ief1bf56c89c8215427dcbddfc67e8bcd4c3607d2
Signed-off-by: xuxinxiong <xuxinxiong@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58624
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
commit 6af980a2a
(drivers/intel/fsp2_0: Allow `mp_startup_all_cpus()` to run serially)
drops CB_SUCCESS check for mp_run_on_all_aps function hence, this
changes bring back the required return type against CB_SUCCESS.
Change-Id: I9fc81e6a7eebbf0072ea2acb36b3c33539b517a7
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58757
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
As per MP service specification, EDK2 is allowed to specify the mode
in which a 'func' routine should be executed on APs.
`SingleThread` sets to 'true' meaning to execute the function one by
one (serially) or sets to 'false' meaning to execute the function
simultaneously.
MP service API `StartupAllAPs` was designed to pass such options as
part of function argument.
But another MP service API `StartupAllCPUs` doesn't specify any such
requirement. Running the `func` simultaneously on APs results in
a coherency issue (hang while executing `func`) due to lack of
acquiring a spin lock while accessing common data structure in
multiprocessor environment.
BUG=b:199246420
Change-Id: Ia95d11408f663212fd40daa9fd9b0881a07f1ce7
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57343
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Not all platforms need to generate power resources, but the code does
not get optimized out at build time because the devicetree gets
compiled into a linked list. As this code pulls in some heavy ACPI
dependencies that is even implemented with weak empty function it
makes sense to optimize out this code using a Kconfig constant.
This saves 1.5K in ramstage size on gigabyte/ga-945gcm-s2l.
Change-Id: I82289aa7e6e82318417f3b827b86182891dfc2a6
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58657
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
There are manual timeout-loops which use a fixed value and udelay().
In all cases there is a debug printk() inside this loop which, when
enabled, takes way longer than the counted microsecond delay. This
leads to the result that e.g. a 1 second delay takes nearly an eternity
if the debug messages are enabled due to the longer function execution
time.
This patch uses the stopwatch scheme for the timeout-loops which still
makes sure that the timeout period is maintained while it takes longer
function calls like printk() into account. In order to keep the minimum
delay between two register accesses on the TPM keep the udelay(1)-call.
TEST=Enable TPM debug messages on a board where the TPM hits a timeout
by failure and make sure that the debug messages occur in the log
just in the timeout period. It still works as expected if the debug
messages are disabled.
Change-Id: I8fd261c9d60a9a60509c847dbc4983bc05f41d48
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58240
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Using cb_err as return type of mp_run_on_aps, mp_run_on_all_aps,
mp_run_on_all_cpus and mp_park_aps clarifies the meaning of the
different return values. This patch also adds the types.h include that
provides the definition of the cb_err enum and checks the return value
of all 4 functions listed above against the enum values instead of
either checking if it's non-zero or less than zero to handle the error
case.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I4b3f03415a041d3ec9cd0e102980e53868b004b0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58494
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
All boards with DRIVERS_GENERIC_IOAPIC select it.
Presumably the related configuration of routing IRQ0 when
IOAPIC is enabled should be always done to provide i8259
legacy compatibility for payloads.
Change-Id: Ie87816271fa63bba892c8615aa5e72ee68f6ba93
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55287
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
There is the wrong register offset printed in the debug log when the
data register is written:
'lpc_tpm: Write reg 0x18 with 0xnn' should be
'lpc_tpm: Write reg 0x24 with 0xnn' for data FIFO access.
This can be confusing when searching for issues with the help of the
TPM debug messages since the code itself is correct. Fix this error.
Change-Id: Ic28ee5a07146e804574b887ea05c62e7e88e9078
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58155
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Return the package with a value for the dptf user space service.
This is required in write tpch method for pch device under dptf
driver.
BUG=b:198582766
BRANCH=None
TEST=Build FW and test on brya0 board
Change-Id: I64e1bb04a6115c7f93c84a5d6644101ac1d3d8ba
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58174
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Add various methods support for pch device under dptf driver.
This provides support of different control knobs for FIVR.
BUG=b:198582766
BRANCH=None
TEST=Build FW and test on brya0 board
Change-Id: I2d40fff98cb4eb9144d55fd5383d9946e4cb0558
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57925
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Some distributions (e.g. NixOS, Debian) are actively working on getting
rid of EOL Python 2. Since `SplitFspBin.py` supports both Python 2 and
Python 3 as of upstream commit 0bc2b07, use whatever version is present
by utilizing `python`.
Change-Id: I2a657d0d4fc1899266a9574cfdfec1380828d72d
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58088
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
These issues were found and fixed by codespell, a useful tool for
finding spelling errors.
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I5b8ecdfe75d99028fee820a2034466a8ad1c5e63
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58080
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change adds type-c port information for USB type-c ports to cbmem.
BUG=b:149830546
TEST='emerge-volteer coreboot chromeos-bootimage', flash and boot
volteer2 to kernel, log in and check cbmem for type-c info exported to
the payload:
localhost ~ # cbmem -c | grep type-c
added type-c port0 info to cbmem: usb2:9 usb3:1 sbu:0 data:0
added type-c port1 info to cbmem: usb2:4 usb3:2 sbu:1 data:0
Change-Id: Ic56a1ad1b617e3af000664147d21165e6ea3a742
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57345
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Move the locally declared typec_orientation enum from chip.h to
coreboot_tables.h.
Change enum typec_orientation name to type_c_orientation for consistency
with contents of coreboot_tables.h.
Rename TYPEC_ORIENTATION_FOLLOW_CC to TYPEC_ORIENTATION_NONE.
BUG=b:149830546
TEST="emerge-volteer coreboot" and make sure it compiles successfully.
Change-Id: I24c9177be72b0c9831791aa7d1f7b1236309c9cd
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58084
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Furquan Shaikh <furquan@google.com>
On AArch64 platforms, GIC initialization is generally the job of Trusted
Firmware and shouldn't be necessary in coreboot. Only the ancient T210
platform (which was started before we had decided on using Trusted
Firmware) calls this code, and even there they have a comment wondering
"do we still need this?". I'm just gonna assume (without testing because
that board is ancient and I'm lazy) that they don't, and that the TF GIC
initialization[1] is sufficient here. Remove this obsolete driver.
[1] https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/3ff448/plat/nvidia/tegra/soc/t210/plat_setup.c#259
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I3e9d90039dd27cb3a13f830ba21fc5cc7a70abe2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57818
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
When the entry delay of L0s is less than the entry delay of L1, GL9755
will enter L0s state first. When it exits from L0s state, the time of L1
entry will be reset. Therefore, the conditions for entering L1 state
cannot be met. In order to enter L1 state, L0s needs to be disabled.
BUG=b:195611000
TEST=Verify GL9755 enters L1 by observing CLKREQ# de-asserts.
Signed-off-by: Ben Chuang <benchuanggli@gmail.com>
Change-Id: If121b5cb534eb32bac8992683c3f0eee8946acec
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57632
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This change drops the function `find_gfx_dev()` as it is unused now.
Change-Id: Ie42707bd45348dc7485ca0ca12ebff2994897e6b
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57746
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
This include provides the definition of enum cb_err.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Idfee720de920377796e3fd64cb47514b8cb08c34
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57730
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
smp_processor_id is defined in src/arch/arm64/include/armv8/arch/cpu.h.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I0b610189bf439774cb900f74559dee314cbc5854
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57728
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Add mipi panel support for wormdingler
- Add the following panel for wormdingler:
INX P110ZZD-DF0
BOE TV110C9M-LL0
- Use panel_id to distinguish which mipi panel to use.
- Setup panel orientation
BUG=b:195898400,b:198548221
BRANCH=none
TEST=emerge-strongbad coreboot
Change-Id: I8cd28e024ecbfdcd473bc39efb529eb4aca1b5d0
Signed-off-by: Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57642
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
FspMultiPhaseSiInit API was introduced with FSP 2.2 specification
onwards. EnableMultiPhaseSiliconInit is an arch UPD also introduced
as part of FSP 2.2 specification to allow calling FspMultiPhaseSiInit
API.
However, some platforms adhere to the FSP specification but
don't have arch UPD structure, for example : JSL, TGL and Xeon-SP.
Out of these platforms, TGL supports calling of FspMultiPhaseSiInit
API and considered EnableMultiPhaseSiliconInit as a platform-specific
UPD rather than an arch UPD to allow calling into FspMultiPhaseSiInit
API.
It is important to ensure that the UPD setting and the callback for
MultiPhaseInit are kept in sync, else it could result in broken
behavior e.g. a hang is seen in FSP if EnableMultiPhaseSiliconInit
UPD is set to 1 but the FspMultiPhaseSiInit API call is skipped.
This patch provides an option for users to choose to bypass calling
into MultiPhaseSiInit API and ensures the EnableMultiPhaseSiliconInit
UPD is set to its default state as `disable` so that FSP-S don't
consider MultiPhaseSiInit API is a mandatory entry point prior to
calling other FSP API entry points.
List of changes:
1. Add `FSPS_HAS_ARCH_UPD` Kconfig for SoC to select if
`FSPS_ARCH_UPD` structure is part of `FSPS_UPD` structure.
2. Drop `soc_fsp_multi_phase_init_is_enable()` from JSL and Xeon-SP
SoCs, a SoC override to callout that SoC doesn't support calling
MultiPhase Si Init is no longer required.
3. Add `FSPS_USE_MULTI_PHASE_INIT` Kconfig for SoC to specify if
SoC users want to enable `EnableMultiPhaseSiliconInit` arch UPD (using
`fsp_fill_common_arch_params()`) and execute FspMultiPhaseSiInit() API.
4. Presently selects `FSPS_USE_MULTI_PHASE_INIT` from IA TCSS common
code.
5. Add `fsp_is_multi_phase_init_enabled()` that check applicability of
MultiPhase Si Init prior calling FspMultiPhaseSiInit() API to
honor SoC users' decision.
6. Drop `arch_silicon_init_params()` from SoC as FSP driver (FSP 2.2)
would check the applicability of MultiPhase Si Init prior calling
FspMultiPhaseSiInit() API.
Additionally, selects FSPS_HAS_ARCH_UPD for Alder Lake as Alder Lake
FSPS_UPD structure has `FSPS_ARCH_UPD` structure and drops
`arch_silicon_init_params()` from SoC
`platform_fsp_silicon_init_params_cb()`.
Skip EnableMultiPhaseSiliconInit hardcoding for Tiger Lake and uses
the fsp_is_multi_phase_init_enabled() function to override
EnableMultiPhaseSiliconInit UPD prior calling MultiPhaseSiInit FSP API.
TEST=EnableMultiPhaseSiliconInit UPD is getting set or reset based on
SoC user selects FSPS_USE_MULTI_PHASE_INIT Kconfig.
Change-Id: I019fa8364605f5061d56e2d80b20e1a91857c423
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56382
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The call to the `get_smbios_data` device operation is followed by
calls to unconditional default functions, which lacks flexibility.
Instead, have devices that implement `get_smbios_data` call these
default functions as needed.
Most `get_smbios_data` implementations are in mainboard code, and are
bound to the root device. The default functions only operate with PCI
devices because of the `dev->path.type != DEVICE_PATH_PCI` checks, so
calling these functions for non-PCI devices is unnecessary. QEMU also
implements `get_smbios_data` but binds it to the domain device, which
isn't PCI either.
Change-Id: Iefbf072b1203d04a98c9d26a30f22cfebe769eb4
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57366
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
...because I just spent hours chasing a refactoring bug that would have
been way more obvious with a little more error transparency in here.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I3354ff0370ae79f05e5c37d292ac16d446898606
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57573
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The MIPI source video data has a large variation (e.g. 59Hz ~ 61Hz),
anx7625 defines K ratio for matching MIPI input video clock and
DP output video clock. A bigger k value can match a bigger video data
variation. IVO panel has smaller variation than DP CTS spec, so decrease
k value to 0x3b.
BUG=b:194659777
BRANCH=none
TEST=Display is normal on Asurada
Change-Id: If3a09811999babda45e9a9a559dd447920109204
Signed-off-by: Xin Ji <xji@analogixsemi.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57439
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Our MIPI panel initialization framework differentiates between DCS and
GENERIC commands, but the exact interpretation of those terms is left to
the platform drivers. In practice, the MIPI DSI transaction codes for
these are standardized and platforms always need to do the same
operation of combining the command length and transfer type into a
correct DSI protocol code. This patch factors out the various
platform-specific DSI protocol definitions into a single global one and
moves the transaction type calculation into the common panel framework.
The Qualcomm SC7180 implementation which previously only supported DCS
commands is enhanced to (hopefully? untested for now...) also support
GENERIC commands. While we're rewriting that whole section also fix some
other issues about how exactly long and short commands need to be passed
to that hardware which we identified in the meantime.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I09ade7857ca04e89d286cf538b1a5ebb1eeb8c04
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57150
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Moves MAX_EVENT_SIZE to commonlib/bsd/include, and renames it
ELOG_MAX_EVENT_SIZE to give it an "scoped" name.
The moving is needed because this defined will be used from
util/cbfstool (see next CL in the chain).
BUG=b:172210863
TEST=compiles Ok
Change-Id: I86b06d257dda5b325a8478a044045b2a63fb1a84
Signed-off-by: Ricardo Quesada <ricardoq@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57394
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
As per the connectivity document deny list entry size should be uint16
559910_Intel_Connectivity_Platforms_BIOS_Guidelines_Rev6_4.pdf
Fixes: cc50770cd0("wifi: Add support for wifi time average SAR config")
Change-Id: I045c21350cf4c2266df108eede6350d090322ba0
Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57407
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Retype loop variable `i` to `uint32_t` for consistency with the types of
the `number_of_phases` and `phase_index` struct fields and the parameter
of the `platform_fsp_multi_phase_init_cb()` function.
Change-Id: I82916f33c2dc5dab6a31111c9acba2a18a5cfb0b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57491
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Platforms that rely on the FSP for parts of the hardware initialization
likely won't boot successfully when no FSP binaries are added during the
build, so print a warning at the end of the build in this case.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Suggested-by: Nico Huber <nico.h@gmx.de>
Suggested-by: Martin Roth <martinroth@google.com>
Change-Id: I6efc184ecc4059818474937fd31574f703c9bdc6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57368
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
