Elyes HAOUAS 92f46aaac7 src: Include <arch/io.h> when appropriate ... Change-Id: I4077b9dfeeb2a9126c35bbdd3d14c52e55a5e87c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45404 Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>		2020-10-26 06:44:40 +00:00
..
acpi	nb/intel/ironlake/acpi/hostbridge.asl: Use ASL 2.0 syntax	2020-08-04 21:31:08 +00:00
registers	nb/intel/ironlake: Put DMIBAR/EPBAR registers into separate files	2020-10-13 21:10:28 +00:00
acpi.c	nb/intel/ironlake/acpi.c: Factor out PCIEXBAR decoding	2020-08-04 21:36:00 +00:00
bootblock.c	nb/intel/ironlake: Correct PCIEXBAR definition	2020-08-03 05:30:59 +00:00
chip.h	nb/intel/ironlake: Use an enum for gpu_panel_port_select	2020-09-08 05:27:26 +00:00
early_init.c	nb/intel/ironlake: Add Generic Non-Core register definitions	2020-08-03 05:32:20 +00:00
finalize.c	nb/intel/ironlake: Drop copy-pasted and unused macro	2020-07-01 18:15:58 +00:00
gma.c	nb/intel/ironlake: Clean up code style (except raminit)	2020-07-02 19:29:10 +00:00
ironlake.h	nb/intel/ironlake: Put DMIBAR/EPBAR registers into separate files	2020-10-13 21:10:28 +00:00
Kconfig
Makefile.inc	src: Remove leading blank lines from SPDX header	2020-05-18 07:00:27 +00:00
memmap.c	nb/intel/ironlake: Drop unnecessary smm_region_start function	2020-10-05 09:19:28 +00:00
northbridge.c	nb/intel/ironlake: Add more host bridge PCI IDs	2020-10-24 16:30:42 +00:00
raminit.c	nb/intel/ironlake: Clean up DMIBAR/EPBAR registers	2020-10-10 19:30:56 +00:00
raminit.h
raminit_tables.c
raminit_tables.h
romstage.c	src: Include <arch/io.h> when appropriate	2020-10-26 06:44:40 +00:00
smi.c	nb/intel/ironlake: Add definition for SAD PCI device	2020-08-03 05:30:50 +00:00