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coreboot-kgpe-d16/src/soc/intel/skylake
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Subrata Banik 15943df29c soc/intel/skylake: Remove TCO lock down programming 
FSP is doing TCO lock inside Post PCI bus enumeration
NotifyPhase(). Hence remove TCO Lock down programming
from coreboot.

TEST= Ensure TCO_LOCK offset 8 bit 12 is set.

Change-Id: Iec9e3075df01862f8558b303a458126c68202bff
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/21031
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-25 18:07:01 +00:00
..
acpi soc/intel/skylake: Enable UART debug controller on S3 resume 2017-08-10 16:25:10 +00:00
bootblock soc/intel/skylake: Add proper support to enable UART2 in 16550 mode 2017-08-16 23:29:56 +00:00
include soc/intel/skylake: Usable dram top calculation based on HW registers 2017-08-23 17:56:50 +00:00
nhlt intel/skylake: nhlt: Add 48Khz 2ch 16bit config for max98927 2017-05-04 01:57:36 +02:00
romstage soc/intel/skylake: Configure FSP to skip ME MBP step 2017-08-17 11:28:24 +00:00
acpi.c soc/intel/skylake: Use CPU common library code 2017-06-09 19:24:58 +02:00
chip.c soc/intel/skylake: Add LPC and SPI lock down config option 2017-08-25 17:58:08 +00:00
chip.h soc/intel/skylake: Add LPC and SPI lock down config option 2017-08-25 17:58:08 +00:00
chip_fsp20.c soc/intel/skylake: Add LPC and SPI lock down config option 2017-08-25 17:58:08 +00:00
cpu.c soc/intel/skylake: Fix SGX init sequence 2017-08-21 19:46:43 +00:00
dsp.c skylake: Add Audio DSP device 2016-05-31 18:45:15 +02:00
elog.c soc/intel/skylake: Log wakes caused by PME on internal bus and PCIE RP 2017-08-08 15:25:27 +00:00
finalize.c soc/intel/skylake: Remove TCO lock down programming 2017-08-25 18:07:01 +00:00
gpio.c soc/intel/skylake: Use common PCR module 2017-04-10 20:04:01 +02:00
gspi.c lib: provide clearer devicetree semantics 2017-04-25 18:14:38 +02:00
i2c.c intel/common/block/i2c: Add common block for I2C and use the same in SoCs 2017-05-18 06:07:15 +02:00
igd.c soc/intel/skylake: Skip disabled IGD device 2017-08-03 20:30:09 +00:00
irq.c soc/pci_devs.h: Use consistent naming in soc/pci_devs.h 2017-03-28 16:39:28 +02:00
Kconfig soc/intel/skylake: Add Kconfig option to select UART index 2017-08-21 16:13:10 +00:00
lockdown.c soc/intel/skylake: Move PMC lock down config after resource allocation 2017-08-25 18:02:44 +00:00
lpc.c soc/intel/skylake: Use PCI IDs from device/pci_ids.h 2017-06-06 19:42:17 +02:00
Makefile.inc soc/intel/skylake: Move LPC lock down config after resource allocation 2017-08-25 18:02:06 +00:00
me.c soc/intel/skylake: Remove incorrect ME PG-status print 2017-07-28 16:17:26 +00:00
memmap.c soc/intel/skylake: Usable dram top calculation based on HW registers 2017-08-23 17:56:50 +00:00
pch.c soc/intel/skylake: Clean up code by using common FAST_SPI module 2017-05-02 18:26:07 +02:00
pei_data.c
pmc.c soc/intel/skylake: Split AC/DC settings for Deep Sx config 2017-04-13 09:09:16 +02:00
pmutil.c soc/intel/skylake: Enable power button SMI when jumping to payload 2017-08-19 00:33:04 +00:00
reset.c Consolidate reset API, add generic reset_prepare mechanism 2017-06-13 20:53:09 +02:00
sd.c soc/intel/skylake: Use SCS common code 2017-06-16 17:37:13 +02:00
smi.c soc/intel/skylake: Enable power button SMI when jumping to payload 2017-08-19 00:33:04 +00:00
smihandler.c soc/intel/skylake: Enable power button SMI when jumping to payload 2017-08-19 00:33:04 +00:00
smmrelocate.c soc/intel/skylake: Wrap lines at 80 columns 2017-03-17 02:34:52 +01:00
spi.c soc/intel/common: Provide common block fast_spi_flash_ctrlr 2017-05-05 23:40:51 +02:00
systemagent.c soc/intel/skylake: Use common systemagent code 2017-06-09 17:06:26 +02:00
uart.c soc/intel/skylake: Add support for all UART port index 2017-08-21 16:29:55 +00:00
uart_debug.c soc/intel/skylake: Add support for all UART port index 2017-08-21 16:29:55 +00:00
vr_config.c intel/skylake: Support for setting AC/DC loadline 2017-03-15 19:45:55 +01:00