Aaron Durbin 2b3e0cdfc4 soc/intel/common/lpss_i2c: configure buses by rise/fall times ... The default register count calculations are leading to higher frequencies than expected. Provide an alternative method for calculating the register counts by utilizing the rise and fall times of the bus. If the rise time is supplied the rise/fall time values are used, but the register overrides take precedence over the rise/fall time calculation. This allows platforms to choose whichever method works the best. BUG=chrome-os-partner:58889 Change-Id: I7747613ce51d8151848acd916c09ae97bfc4b86a Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17350 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)		2016-11-12 00:19:22 +01:00
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acpi	soc/intel/skylake: Add _ACx methods for TSR0 sensor for fan control	2016-11-07 20:41:36 +01:00
bootblock	soc/intel/common/lpss_i2c: simplify API and use common config structure	2016-11-11 03:11:45 +01:00
include	soc/intel/skylake: Add device id for PCH-Y	2016-11-07 19:20:21 +01:00
nhlt
romstage	soc/intel/skylake: Add FSP 2.0 support in romstage	2016-09-15 00:46:11 +02:00
acpi.c	soc/intel/skylake: don't hardcode GPE0 standard reg	2016-10-28 19:01:48 +02:00
chip.c	soc/intel/skylake: move i2c voltage config to own variable	2016-11-11 03:11:31 +01:00
chip.h	soc/intel/common/lpss_i2c: simplify API and use common config structure	2016-11-11 03:11:45 +01:00
chip_fsp20.c	soc/intel/skylake: move i2c voltage config to own variable	2016-11-11 03:11:31 +01:00
cpu.c	soc/intel/skylake: Add Kabylake device Ids	2016-08-06 04:36:46 +02:00
cpu_info.c
dsp.c
elog.c	soc/intel/skylake: Cleanup patch for Skylake SoC	2016-08-08 18:18:57 +02:00
finalize.c	skylake: Do FspTempRamInit only for FSP1.1 & tidy up PCH early init	2016-08-18 06:26:40 +02:00
flash_controller.c	soc/intel/skylake: Use intel common support to write-protect SPI flash	2016-10-26 01:50:45 +02:00
gpio.c	soc/intel/skylake: Add function for gpio_t to ACPI pin translation	2016-07-02 01:20:02 +02:00
i2c.c	soc/intel/common/lpss_i2c: configure buses by rise/fall times	2016-11-12 00:19:22 +01:00
igd.c	soc/intel/skylake: Add FSP 2.0 support in ramstage	2016-09-19 21:32:22 +02:00
irq.c	soc/intel/skylake: Add FSP 2.0 support in ramstage	2016-09-19 21:32:22 +02:00
Kconfig	soc/intel/skylake: fix memory access beyond array bounds	2016-11-09 23:29:43 +01:00
lpc.c	soc/intel/skylake: Add device id for PCH-Y	2016-11-07 19:20:21 +01:00
Makefile.inc	soc/intel/skylake: Fix SATA booting to OS issue	2016-11-07 20:11:43 +01:00
me.c	soc/intel/skylake: Implement Global Reset MEI message	2016-10-16 02:50:26 +02:00
memmap.c	skylake: Add initial FSP2.0 support	2016-08-31 20:02:07 +02:00
monotonic_timer.c
opregion.c	skylake: Add initial FSP2.0 support	2016-08-31 20:02:07 +02:00
pch.c	soc/intel/skylake: Cleanup patch for Skylake SoC	2016-08-08 18:18:57 +02:00
pcie.c
pcr.c
pei_data.c
pmc.c	skylake: Prepare GPE for use in bootblock	2016-10-27 16:30:36 +02:00
pmutil.c	soc/intel/{sky,apollo}lake: Wait until GPE is clear when reading	2016-11-07 20:39:02 +01:00
reset.c	soc/intel/skylake: Handle platform global reset	2016-10-16 02:51:25 +02:00
sata.c	soc/intel/skylake: Fix SATA booting to OS issue	2016-11-07 20:11:43 +01:00
sd.c	acpi: Change device properties to work as a tree	2016-07-08 17:21:26 +02:00
smbus.c
smbus_common.c
smi.c	skylake: Add support for eSPI SMI events	2016-10-27 16:30:54 +02:00
smihandler.c	skylake: Add support for eSPI SMI events	2016-10-27 16:30:54 +02:00
smmrelocate.c	src/soc: Capitalize CPU, ACPI, RAM and ROM	2016-07-31 19:27:53 +02:00
systemagent.c	soc/intel/skylake: Add Kabylake device Ids	2016-08-06 04:36:46 +02:00
tsc_freq.c
uart.c
uart_debug.c
vr_config.c	skylake: Add initial FSP2.0 support	2016-08-31 20:02:07 +02:00
xhci.c