Kyösti Mälkki 3aff1a3208 Convert AOpen DXPL Plus mainboard to CAR ... Tested on real hardware, mainboard with dual Xeon P4 HT CPUs requires cache-as-ram init code with AP SIPI protocol. Also enable 2nd CPU and PATA and clean-up Kconfig and ACPI. Change-Id: I415482f3af22df79d82492c49aed83549f29aa56 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/886 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>		2012-04-12 10:27:34 +02:00
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arch/x86	Unify IO APIC address specification	2012-04-12 00:06:11 +02:00
boot	Add more timestamps in coreboot.	2012-03-30 17:45:20 +02:00
console	Add support to run SMM handler in TSEG instead of ASEG	2012-04-04 04:49:09 +02:00
cpu	S3 code in vendorcode folder.	2012-04-12 00:17:35 +02:00
devices	x86, oprom: ensure DF is always cleared	2012-04-02 19:50:22 +02:00
drivers	Detect whether the OXPCIE card is really present while in the ROM stage.	2012-03-29 23:04:06 +02:00
ec	Add EC component for SMSC MEC1308/1310	2012-04-02 18:42:40 +02:00
include	Add support for aligned allocation	2012-04-12 08:38:58 +02:00
lib	Add support for aligned allocation	2012-04-12 08:38:58 +02:00
mainboard	Convert AOpen DXPL Plus mainboard to CAR	2012-04-12 10:27:34 +02:00
northbridge	Unify IO APIC address specification	2012-04-12 00:06:11 +02:00
pc80	Move TPM code to romstage	2012-04-04 19:09:53 +02:00
southbridge	Add Southbridge support for S3.	2012-04-12 00:14:58 +02:00
superio	Add support for SMSC MEC1308/1310 SuperI/O EC	2012-04-06 21:24:01 +02:00
vendorcode	S3 code in vendorcode folder.	2012-04-12 00:17:35 +02:00
Kconfig	Add support for Intel Panther Point PCH	2012-04-04 19:10:51 +02:00
Kconfig.deprecated_options	Unify ID_SECTION_OFFSET and mark it deprecated	2012-01-18 11:21:39 +01:00