coreboot-kgpe-d16/src/northbridge/intel/ironlake
Angel Pons 3b264d0074 nb/intel/ironlake: Clean up DMIBAR/EPBAR registers
Several registers have been copy-pasted from i945 and do not exist on
Ironlake. Moreover, other register definitions were missing. Use the
newly-added definitions in existing code, in place of numerical offsets.

Tested with BUILD_TIMELESS=1, Packard Bell MS2290 remains identical.

Change-Id: I8ac99166a8029dcdbb59028b4a7ee297249de5db
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45380
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-10-10 19:30:56 +00:00
..
acpi nb/intel/ironlake/acpi/hostbridge.asl: Use ASL 2.0 syntax 2020-08-04 21:31:08 +00:00
acpi.c nb/intel/ironlake/acpi.c: Factor out PCIEXBAR decoding 2020-08-04 21:36:00 +00:00
bootblock.c nb/intel/ironlake: Correct PCIEXBAR definition 2020-08-03 05:30:59 +00:00
chip.h nb/intel/ironlake: Use an enum for gpu_panel_port_select 2020-09-08 05:27:26 +00:00
early_init.c nb/intel/ironlake: Add Generic Non-Core register definitions 2020-08-03 05:32:20 +00:00
finalize.c nb/intel/ironlake: Drop copy-pasted and unused macro 2020-07-01 18:15:58 +00:00
gma.c nb/intel/ironlake: Clean up code style (except raminit) 2020-07-02 19:29:10 +00:00
hostbridge_regs.h nb/intel/ironlake: Correct PCIEXBAR definition 2020-08-03 05:30:59 +00:00
ironlake.h nb/intel/ironlake: Clean up DMIBAR/EPBAR registers 2020-10-10 19:30:56 +00:00
Kconfig
Makefile.inc src: Remove leading blank lines from SPDX header 2020-05-18 07:00:27 +00:00
memmap.c nb/intel/ironlake: Drop unnecessary smm_region_start function 2020-10-05 09:19:28 +00:00
northbridge.c nb/intel/ironlake: Clean up DMIBAR/EPBAR registers 2020-10-10 19:30:56 +00:00
raminit.c nb/intel/ironlake: Clean up DMIBAR/EPBAR registers 2020-10-10 19:30:56 +00:00
raminit.h treewide: Remove "this file is part of" lines 2020-05-11 17:11:40 +00:00
raminit_tables.c
raminit_tables.h
romstage.c nb/intel/ironlake: Clean up code style (except raminit) 2020-07-02 19:29:10 +00:00
smi.c nb/intel/ironlake: Add definition for SAD PCI device 2020-08-03 05:30:50 +00:00