coreboot-kgpe-d16/src/mainboard/intel/shadowmountain
Jes B. Klinke c6b041a12e tpm: Refactor TPM Kconfig dimensions
Break TPM related Kconfig into the following dimensions:

TPM transport support:
config CRB_TPM
config I2C_TPM
config SPI_TPM
config MEMORY_MAPPED_TPM (new)

TPM brand, not defining any of these is valid, and result in "generic" support:
config TPM_ATMEL (new)
config TPM_GOOGLE (new)
config TPM_GOOGLE_CR50 (new, implies TPM_GOOGLE)
config TPM_GOOGLE_TI50 (new to be used later, implies TPM_GOOGLE)

What protocol the TPM chip supports:
config MAINBOARD_HAS_TPM1
config MAINBOARD_HAS_TPM2

What the user chooses to compile (restricted by the above):
config NO_TPM
config TPM1
config TPM2

The following Kconfigs will be replaced as indicated:
config TPM_CR50 -> TPM_GOOGLE
config MAINBOARD_HAS_CRB_TPM -> CRB_TPM
config MAINBOARD_HAS_I2C_TPM_ATMEL -> I2C_TPM && TPM_ATMEL
config MAINBOARD_HAS_I2C_TPM_CR50 -> I2C_TPM && TPM_GOOGLE
config MAINBOARD_HAS_I2C_TPM_GENERIC -> I2C_TPM && !TPM_GOOGLE && !TPM_ATMEL
config MAINBOARD_HAS_LPC_TPM -> MEMORY_MAPPED_TPM
config MAINBOARD_HAS_SPI_TPM -> SPI_TPM && !TPM_GOOGLE && !TPM_ATMEL
config MAINBOARD_HAS_SPI_TPM_CR50 -> SPI_TPM && TPM_GOOGLE

Signed-off-by: Jes B. Klinke <jbk@chromium.org>
Change-Id: I4656b2b90363b8dfd008dc281ad591862fe2cc9e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63424
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-04-21 23:07:20 +00:00
..
spd mb/intel/shadowmountain: Add the romstage code 2021-02-22 05:46:58 +00:00
variants/baseboard ChromeOS: Add DECLARE_x_CROS_GPIOS() 2022-04-07 20:38:12 +00:00
board_info.txt
bootblock.c mb/intel/shadowmountain: Add bootblock and verstage code 2021-02-06 09:09:16 +00:00
chromeos.c ChromeOS: Promote variant_cros_gpio() 2022-04-06 17:40:50 +00:00
chromeos.fmd mb/intel/shadowmountain: Add flash layout 2021-01-28 03:11:35 +00:00
dsdt.asl mb/intel/shadowmountain: Add the ASL code 2021-02-27 09:40:57 +00:00
ec.c mb/intel/shadowmountain: Add the ramstage code 2021-02-27 09:40:47 +00:00
Kconfig tpm: Refactor TPM Kconfig dimensions 2022-04-21 23:07:20 +00:00
Kconfig.name
mainboard.c ChromeOS: Refactor ACPI CNVS generation 2021-12-23 21:18:25 +00:00
Makefile.inc mb/intel/shadowmountain: Add the ramstage code 2021-02-27 09:40:47 +00:00
romstage.c {mb, soc}: Move mrc_cache invalidating logic into memory common code 2022-03-15 10:18:28 +00:00
smihandler.c mb/intel/shadowmountain: Add the ramstage code 2021-02-27 09:40:47 +00:00