Michael Niewöhner 71624cd94f soc/intel/*: drop broken LPC mmio code ... The code for setting the LPC generic memory range uses an array of fixed address ranges not needing explicit decoding, to decide if the address needs to be written to the LGMR register. Most platforms only mistakenly add the PCH reserved mmio range, that is not decoded generally, effectively breaking the mechanism. Only APL uses the array correctly. That code, in it's current state, does not work (except for APL) and currently, there is not a single user. Thus, drop it before people start using it. Change-Id: I723415fedd1b1d95c502badf7b0510a1338b11ac Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49588 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>		2021-01-20 18:29:06 +00:00
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acpi	soc/intel/common: Move gfx.asl to drivers/intel/gma	2020-12-30 16:35:21 +00:00
bootblock	soc/intel/alderlake: Add PCH ID 0x5182	2021-01-12 05:18:51 +00:00
include/soc	soc/intel/alderlake: Update PCH and CPU PCIe RP table	2021-01-18 07:28:51 +00:00
romstage	soc/intel/alderlake: Refactor SoC code to maintain CPU and PCH PCIE RPs	2021-01-10 17:49:19 +00:00
acpi.c	ACPI GNVS: Drop most dev_count_cpu()	2021-01-20 09:22:59 +00:00
chip.c	soc/intel/alderlake: Update PCH and CPU PCIe RP table	2021-01-18 07:28:51 +00:00
chip.h	soc/intel/common: Move L1_substates_control to pcie_rp.h	2021-01-18 07:28:32 +00:00
chipset.cb	soc/intel: hook up new gpio device in the soc chips	2020-12-30 00:30:04 +00:00
cpu.c	soc/intel: deduplicate ACPI timer emulation	2020-10-28 21:28:19 +00:00
elog.c	soc/intel/alderlake/ramstage: Do initial SoC commit till ramstage	2020-10-03 12:15:22 +00:00
espi.c	soc/intel/*: drop broken LPC mmio code	2021-01-20 18:29:06 +00:00
finalize.c	soc/intel/*: drop useless XTAL shutdown qualification code	2020-10-19 07:09:12 +00:00
fsp_params.c	soc/intel/alderlake: Refactor SoC code to maintain CPU and PCH PCIE RPs	2021-01-10 17:49:19 +00:00
gpio.c	soc/intel/alderlake: Add GPIOs for Alder Lake SOC	2020-09-27 03:03:25 +00:00
gspi.c	soc/intel/alderlake/ramstage: Do initial SoC commit till ramstage	2020-10-03 12:15:22 +00:00
i2c.c	soc/intel/alderlake/ramstage: Do initial SoC commit till ramstage	2020-10-03 12:15:22 +00:00
Kconfig	soc/intel/alderlake: Refactor SoC code to maintain CPU and PCH PCIE RPs	2021-01-10 17:49:19 +00:00
lockdown.c	soc/intel/alderlake/ramstage: Do initial SoC commit till ramstage	2020-10-03 12:15:22 +00:00
Makefile.inc	soc/intel/alderlake: Update PCH and CPU PCIe RP table	2021-01-18 07:28:51 +00:00
me.c	soc/intel/alderlake/ramstage: Do initial SoC commit till ramstage	2020-10-03 12:15:22 +00:00
meminit.c	soc/intel/alderlake: Add lp5_ccc_config to the board memory configuration	2020-11-29 14:39:06 +00:00
p2sb.c	soc/intel/alderlake/romstage: Do initial SoC commit till romstage	2020-09-15 15:13:50 +00:00
pcie_rp.c	soc/intel/alderlake: Update PCH and CPU PCIe RP table	2021-01-18 07:28:51 +00:00
pmc.c	soc/intel/alderlake/ramstage: Do initial SoC commit till ramstage	2020-10-03 12:15:22 +00:00
pmutil.c	soc/intel/alderlake/ramstage: Do initial SoC commit till ramstage	2020-10-03 12:15:22 +00:00
reset.c	soc/intel: Use of common reset code block	2020-11-02 10:43:53 +00:00
smihandler.c	soc/intel/alderlake/ramstage: Do initial SoC commit till ramstage	2020-10-03 12:15:22 +00:00
smmrelocate.c	soc/intel/alderlake/ramstage: Do initial SoC commit till ramstage	2020-10-03 12:15:22 +00:00
soundwire.c	mb/intel: Enable ALC711 Audio codec over SNDW0 link	2020-11-07 08:55:53 +00:00
spi.c	soc/intel/alderlake: Add SPI DMI Destination ID	2020-12-23 03:28:47 +00:00
systemagent.c	soc/intel/alderlake/ramstage: Do initial SoC commit till ramstage	2020-10-03 12:15:22 +00:00
uart.c	soc/intel: rename uart_max_index	2021-01-12 23:38:32 +00:00