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coreboot-kgpe-d16/src/soc/intel/tigerlake
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Rizwan Qureshi 789bdc3d9b src/soc/intel/tigerlake: Fix incorrect use of Field objects in ASL 
Method RAOW is assuming that the first argument is a Field object
and writing to it expecting the register to get updated. However,
the callers are passing in the value of the Field object instead.

This eventually is resulting the IMGCLK not getting enable/disabled on the
platform.

Fix this by sending the exact address of the register to be updated.

Also MCCT was setting the clock frequency in both case i.e, Clock Enable
and Disable. Split the MCCT method in two, MCON and MCOF to fix the sequencing
like below
MCON:
 Set frequency
 Enable clock
MCOF:
 Disable clock

Also, make use of MCON and MCOF methods for camera clock control in tglrvp.
This is to avoid the buildbot marking the patch unstable.

BUG=None
BRANCH=None
TEST=Build and Boot waddledoo board and verified that IMGCLKOUT for
world facing camera is enabled/disabled and able to capture images.
Build and Boot Tiger Lake RVP board and verified that IMGCLKOUT for
world facing camera is enabled/disabled and able to capture images.

Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Change-Id: I8b886255d5f38819502ae1f4af0851b5a0922b22
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39498
Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-17 08:25:57 +00:00
..
acpi src/soc/intel/tigerlake: Fix incorrect use of Field objects in ASL 2020-03-17 08:25:57 +00:00
bootblock soc/intel/common: Update Jasper Lake Device IDs 2020-02-25 10:13:36 +00:00
include/soc soc/intel/tigerlake: Enable VT-d and generate DMAR ACPI table 2020-03-12 21:36:57 +00:00
romstage soc/intel/tigerlake: Support ISH 2020-03-16 14:46:31 +00:00
acpi.c soc/intel/tigerlake: Enable VT-d and generate DMAR ACPI table 2020-03-12 21:36:57 +00:00
chip.c soc/intel/tigerlake: Support ISH 2020-03-16 14:46:31 +00:00
chip.h soc/intel/tigerlake: Enable CNVi through dev_enabled 2020-03-15 12:55:19 +00:00
cpu.c soc/intel: fix eist enabling 2020-03-10 20:29:10 +00:00
elog.c soc/intel/tigerlake: Do initial SoC commit till ramstage 2019-11-09 03:26:34 +00:00
espi.c soc/intel/tigerlake: Update PMC Register Base and platform check for JSP 2020-02-15 04:09:21 +00:00
finalize.c soc/intel/{cnl,icl,skl, tgl}: Move SOC_INTEL_COMMON_BLOCK_THERMAL into SoC specific Kconfig 2020-01-16 16:28:09 +00:00
fsp_params_jsl.c soc/intel/tigerlake: Fix stale device pointer usage 2020-03-11 14:37:28 +00:00
fsp_params_tgl.c soc/intel/tigerlake: Enable CNVi through dev_enabled 2020-03-15 12:55:19 +00:00
gpio_jsl.c soc/intel/tigerlake: Add Jasper lake GPIO support 2020-03-03 10:09:26 +00:00
gpio_tgl.c soc/intel/tigerlake: Add Jasper lake GPIO support 2020-03-03 10:09:26 +00:00
graphics.c soc/intel/tigerlake: Do initial SoC commit till ramstage 2019-11-09 03:26:34 +00:00
gspi.c soc/intel/tigerlake: Do initial SoC commit till ramstage 2019-11-09 03:26:34 +00:00
i2c.c soc/intel/tigerlake: Do initial SoC commit till ramstage 2019-11-09 03:26:34 +00:00
Kconfig soc/intel/{icl,jsl,tgl}: Enable PlatformDebugConsent by Kconfig 2020-03-01 07:21:41 +00:00
lockdown.c soc/intel/tigerlake: Do initial SoC commit till ramstage 2019-11-09 03:26:34 +00:00
Makefile.inc soc/intel/tigerlake: Add Jasper lake GPIO support 2020-03-03 10:09:26 +00:00
meminit_jsl.c src/soc/tigerlake: Add memory configuration support for Jasper Lake 2020-03-03 04:07:39 +00:00
meminit_tgl.c soc/intel/tigerlake: add memory configuration support 2020-02-09 19:26:36 +00:00
p2sb.c soc/intel/tigerlake: Do initial SoC commit till ramstage 2019-11-09 03:26:34 +00:00
pmc.c soc/intel/tigerlake: Do initial SoC commit till ramstage 2019-11-09 03:26:34 +00:00
pmutil.c soc/intel: Add get_pmbase 2020-02-04 18:54:01 +00:00
reset.c soc/intel/{cnl,icl,skl,tgl,common}: Make changes to send_heci_reset_req_message() 2020-02-09 19:20:44 +00:00
sd.c soc/intel/tigerlake: Do initial SoC commit till ramstage 2019-11-09 03:26:34 +00:00
smihandler.c soc/intel/*/smihandler: Only compile in TCO SMI handler if needed 2020-03-12 21:36:20 +00:00
smmrelocate.c src: Use '#include <smp/node.h>' when appropriate 2019-12-19 05:23:25 +00:00
spi.c soc/intel/tigerlake: Do initial SoC commit till ramstage 2019-11-09 03:26:34 +00:00
systemagent.c soc/intel/tigerlake: Enable VT-d and generate DMAR ACPI table 2020-03-12 21:36:57 +00:00
uart.c soc/intel/tigerlake: Do initial SoC commit till ramstage 2019-11-09 03:26:34 +00:00