Arthur Heymans 5cb24d4522 soc/intel/cache_as_ram.S: Fix CAR issues with Bootguard ... It looks like the 'clear_car' code does not properly fill the required cachelines so add code to fill cachelines explicitly. Change-Id: Id5d77295f6d24f9d2bc23f39f8772fd172ac8910 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55791 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Christopher Meis <christopher.meis@9elements.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>		2021-06-26 10:06:23 +00:00
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car	soc/intel/cache_as_ram.S: Fix CAR issues with Bootguard	2021-06-26 10:06:23 +00:00
cpulib.c	soc/intel/common,skl: set MSR LT_LOCK_MEMORY once, not per thread	2021-04-22 19:41:29 +00:00
Kconfig	soc/intel/cache_as_ram.S: Fix SOC_INTEL_APOLLOLAKE	2021-06-24 10:02:06 +00:00
Makefile.inc	soc/intel: Factor out common smmrelocate.c	2021-03-03 09:06:09 +00:00
mp_init.c	soc/intel/{common,alderlake}: Use generic name "Alderlake Platform"	2021-06-11 07:32:46 +00:00
pm_timer_emulation.c
smmrelocate.c	soc/intel: Factor out common smmrelocate.c	2021-03-03 09:06:09 +00:00