Subrata Banik 8e6d5f2937 {include,mb,soc,sb,vendorcode}: Make hexadecimal notation consistent ... Convert 0X -> 0x Signed-off-by: Subrata Banik <subrata.banik@intel.com> Change-Id: Iea3ca67908135d0e85083a05bad2ea176ca34095 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44926 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>		2020-09-01 03:06:04 +00:00
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apollolake	mrc_cache: Add mrc_cache fetch functions to support non-x86 platforms	2020-08-24 23:30:50 +00:00
baytrail	mrc_cache: Add mrc_cache fetch functions to support non-x86 platforms	2020-08-24 23:30:50 +00:00
braswell	SMM: Validate more user-provided pointers	2020-08-21 07:51:07 +00:00
broadwell	mrc_cache: Add mrc_cache fetch functions to support non-x86 platforms	2020-08-24 23:30:50 +00:00
cannonlake	soc/intel/cnl: Configure FSP option PcieRpSlotImplemented	2020-08-23 09:57:02 +00:00
common	PCI IDs: Add PCI ID for CML DPTF/DTT PCI device	2020-08-29 01:59:02 +00:00
denverton_ns	cpu,soc/intel: Drop select SMP	2020-07-26 20:59:52 +00:00
elkhartlake	soc/intel/elkhartlake/romstage: Do initial SoC commit till romstage	2020-08-31 12:37:11 +00:00
icelake	elog: rename ELOG_WAKE_SOURCE_GPIO to ELOG_WAKE_SOURCE_GPE	2020-08-18 15:57:40 +00:00
jasperlake	util: rename lp4x spds to include "lp4x-" in name	2020-08-28 04:36:18 +00:00
quark	{include,mb,soc,sb,vendorcode}: Make hexadecimal notation consistent	2020-09-01 03:06:04 +00:00
skylake	elog: rename ELOG_WAKE_SOURCE_GPIO to ELOG_WAKE_SOURCE_GPE	2020-08-18 15:57:40 +00:00
tigerlake	soc/intel/tigerlake: add ddr4-spd-empty.hex	2020-08-28 16:13:39 +00:00
xeon_sp	vendorcode/intel/fsp/fsp2_0/CPX-SP: update to ww34 release and adapt soc	2020-08-28 17:44:46 +00:00
Kconfig