Arthur Heymans 9d0b7b9021 arch/riscv: Make RISCV specific options depend on ARCH_RISCV ... Also don't define the default as this results in spurious lines in the .config. The only difference in the generated config.h is that for most board ARCH_RISCV_M goes from 1 to 0. This should not matter. Change-Id: I3e8c1cc5696d621e243696a3b5e34f62ab69a688 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31311 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>		2019-07-02 16:16:31 +00:00
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include	riscv: Fix MENTRY_FRAME_SIZE to fit different machine lengths	2019-06-23 12:14:30 +00:00
arch_timer.c	device/mmio.h: Add include file for MMIO ops	2019-03-04 15:57:39 +00:00
boot.c	riscv: workaround selfboot putting the coreboot table into prog_entry_arg	2019-06-23 12:15:23 +00:00
bootblock.S	riscv: Add initial support for 32bit boards	2019-02-13 04:49:14 +00:00
fp_asm.S	riscv: update misaligned memory access exception handling	2018-09-10 15:03:58 +00:00
Kconfig	arch/riscv: Make RISCV specific options depend on ARCH_RISCV	2019-07-02 16:16:31 +00:00
Makefile.inc	riscv: Add initial support for 32bit boards	2019-02-13 04:49:14 +00:00
mcall.c	arch/riscv/mcall: Drop debug code	2019-06-28 07:35:56 +00:00
misaligned.c	src/arch/riscv/misaligned.c: Fix an off-by-one error when loading the opcode	2018-10-30 02:07:58 +00:00
misc.c	arch/riscv: provide a monotonic timer	2018-09-14 09:28:06 +00:00
payload.c	riscv: use mret to invoke M-mode payload and disable interrupts	2019-06-23 12:14:54 +00:00
pmp.c	riscv: add physical memory protection (PMP) support	2018-10-11 10:56:54 +00:00
ramstage.S	riscv: Add initial support for 32bit boards	2019-02-13 04:49:14 +00:00
sbi.c	src: Use include <console/console.h> when appropriate	2019-04-23 10:01:21 +00:00
smp.c	riscv: Add initial support for 32bit boards	2019-02-13 04:49:14 +00:00
stages.c	riscv: Simplify payload handling	2019-02-02 16:53:21 +00:00
tables.c
trap_handler.c	src: Use 'include <string.h>' when appropriate	2019-03-20 20:27:51 +00:00
trap_util.S	arch/riscv: Align trap_entry to 4 bytes, as required by spec	2018-02-20 20:44:43 +00:00
virtual_memory.c	arch/riscv: Don't set FPU state to "dirty"	2018-12-19 05:46:07 +00:00