24ab1c5db6
It is a requirement for Firmware to have Firmware Interface Table (FIT), which contains pointers to each microcode update. The microcode update is loaded for all logical processors before reset vector. FSPT_UPD.MicrocodeRegionBase and FSPT_UPD.MicrocodeRegionLength are input parameters to TempRamInit API. If these values are 0, FSP will not attempt to update microcode. Since Gen-4 all IA-SoC has FIT loading ucode even before cpu reset in place hence skipping FSP-T loading ucode after CPU reset options. Also removed unused kconfig CONFIG_CPU_MICROCODE_CBFS_LOC and CONFIG_CPU_MICROCODE_CBFS_LEN Change-Id: I3a406fa0e2e62e3363c2960e173dc5f5f5ca0455 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37187 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: David Guckian Tested-by: build bot (Jenkins) <no-reply@coreboot.org> |
||
---|---|---|
.. | ||
acpi | ||
bootblock | ||
include/soc | ||
acpi.c | ||
chip.c | ||
chip.h | ||
cpu.c | ||
csme_ie_kt.c | ||
fiamux.c | ||
gpio.c | ||
gpio_dnv.c | ||
hob_display.c | ||
hob_mem.c | ||
Kconfig | ||
lpc.c | ||
Makefile.inc | ||
memmap.c | ||
npk.c | ||
pmc.c | ||
pmutil.c | ||
reset.c | ||
romstage.c | ||
sata.c | ||
smihandler.c | ||
smm.c | ||
soc_util.c | ||
spi.c | ||
systemagent.c | ||
tsc_freq.c | ||
uart.c | ||
uart_debug.c | ||
upd_display.c | ||
xhci.c |