coreboot-kgpe-d16/src/soc/intel/skylake
Aaron Durbin c5b91d6800 skylake: fill out gen_pmcon_* bitfields
Open coding bitfields is really annoying as no one knows
what they are unless you have a doc in front of you.
Fill in the bitfields for the GEN_PMCON_A and GEN_PMCON_B
registers.

BUG=chrome-os-partner:43522
BRANCH=None
TEST=Built and booted glados.

Original-Change-Id: Id48de68eaa3896c17d5da2ffb0bcf17062f73e5e
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/290336
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>

Change-Id: I968be9736419e26a771e0a0c3c964d540fbb1efe
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11182
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-08-14 15:15:12 +02:00
..
acpi skylake: remove whitespace from ASL files 2015-07-17 21:37:32 +02:00
bootblock skylake: fix garbled patch from upstream 2015-08-13 16:11:26 +02:00
include/soc skylake: fill out gen_pmcon_* bitfields 2015-08-14 15:15:12 +02:00
microcode skylake: Rework microcode include path 2015-07-29 18:25:01 +02:00
romstage skylake: use native gpio configuration for uart 2015-08-14 15:13:31 +02:00
acpi.c
chip.c skylake: remove the redundant fspNotify in chip final. 2015-07-29 19:13:36 +02:00
chip.h skylake: Add Deep Sx configuration for wake pins 2015-08-13 16:33:23 +02:00
cpu.c skylake: Update microcode reload in ramstage. 2015-07-29 20:26:35 +02:00
cpu_info.c
elog.c skylake: align power management names with hardware 2015-07-29 19:31:07 +02:00
finalize.c
flash_controller.c
gpio.c skylake: provide native gpio functionality 2015-08-14 15:13:15 +02:00
igd.c
Kconfig skylake: provide native gpio functionality 2015-08-14 15:13:15 +02:00
lpc.c
Makefile.inc skylake: fix serial port with new code base 2015-08-13 16:33:53 +02:00
memmap.c intel fsp: remove CHIPSET_RESERVED_MEM_BYTES 2015-07-21 20:09:31 +02:00
monotonic_timer.c
pch.c
pcie.c
pcr.c skylake: provide pcr helper to get a port's register space 2015-07-29 19:30:49 +02:00
pei_data.c skylake: clean-up pei_data 2015-07-29 19:31:31 +02:00
pmc.c skylake: fill out gen_pmcon_* bitfields 2015-08-14 15:15:12 +02:00
pmutil.c skylake: align power management names with hardware 2015-07-29 19:31:07 +02:00
ramstage.c
smbus.c
smbus_common.c
smi.c
smihandler.c
smmrelocate.c
systemagent.c intel fsp: remove CHIPSET_RESERVED_MEM_BYTES 2015-07-21 20:09:31 +02:00
tsc_freq.c
uart.c skylake: fix serial port with new code base 2015-08-13 16:33:53 +02:00
uart_debug.c skylake: fix serial port with new code base 2015-08-13 16:33:53 +02:00
xhci.c