coreboot-kgpe-d16/src/soc/intel
Tan, Lean Sheng cecd7af959 soc/intel/elkhartlake/romstage: Do initial SoC commit till romstage
Clone entirely from Jasperlake

List of changes on top off initial jasperlake clone
1. Replace "Jasperlake" with "Elkhartlake"
2. Replace "jsl" with "ehl"
3. Rename structure based on Jasperlake with Elkhartlake
4. Clean up upd override in fsp_params.c, will be added later
5. Temporarily remove _weak attributes in fsp_param & romstage.c
6. Add required headers into include/soc/ from jasperlake directory

Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com>
Change-Id: If2bbe0b8a12bb78b3650f9d0a60f002f7eacb513
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44801
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
2020-08-31 12:37:11 +00:00
..
apollolake mrc_cache: Add mrc_cache fetch functions to support non-x86 platforms 2020-08-24 23:30:50 +00:00
baytrail mrc_cache: Add mrc_cache fetch functions to support non-x86 platforms 2020-08-24 23:30:50 +00:00
braswell SMM: Validate more user-provided pointers 2020-08-21 07:51:07 +00:00
broadwell mrc_cache: Add mrc_cache fetch functions to support non-x86 platforms 2020-08-24 23:30:50 +00:00
cannonlake soc/intel/cnl: Configure FSP option PcieRpSlotImplemented 2020-08-23 09:57:02 +00:00
common PCI IDs: Add PCI ID for CML DPTF/DTT PCI device 2020-08-29 01:59:02 +00:00
denverton_ns cpu,soc/intel: Drop select SMP 2020-07-26 20:59:52 +00:00
elkhartlake soc/intel/elkhartlake/romstage: Do initial SoC commit till romstage 2020-08-31 12:37:11 +00:00
icelake elog: rename ELOG_WAKE_SOURCE_GPIO to ELOG_WAKE_SOURCE_GPE 2020-08-18 15:57:40 +00:00
jasperlake util: rename lp4x spds to include "lp4x-" in name 2020-08-28 04:36:18 +00:00
quark src: Make HAVE_CF9_RESET set the FADT reset register 2020-07-20 13:23:13 +00:00
skylake elog: rename ELOG_WAKE_SOURCE_GPIO to ELOG_WAKE_SOURCE_GPE 2020-08-18 15:57:40 +00:00
tigerlake soc/intel/tigerlake: add ddr4-spd-empty.hex 2020-08-28 16:13:39 +00:00
xeon_sp vendorcode/intel/fsp/fsp2_0/CPX-SP: update to ww34 release and adapt soc 2020-08-28 17:44:46 +00:00
Kconfig fsp2_0: Gather Kconfig declarations 2020-04-05 23:26:24 +00:00