d522db048b
8M was set in the assumption that at least 4M was needed for IED (Intel Enhanced Debug) , but this is not true. The SMRR MTRR's need to have TSEG aligned to its size which is easier when TSEG is only 2M. Also at most 6M of RAM more becomes available for use. Change-Id: I4b114c8dc13699b3c034f0a7060181d9d590737b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/27873 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> |
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|---|---|---|
| .. | ||
| acpi | ||
| acpi.c | ||
| bootblock.c | ||
| chip.h | ||
| early_init.c | ||
| early_reset.c | ||
| gm45.h | ||
| gma.c | ||
| igd.c | ||
| iommu.c | ||
| Kconfig | ||
| Makefile.inc | ||
| northbridge.c | ||
| pcie.c | ||
| pm.c | ||
| ram_calc.c | ||
| raminit.c | ||
| raminit_rcomp_calibration.c | ||
| raminit_read_write_training.c | ||
| raminit_receive_enable_calibration.c | ||
| thermal.c | ||