Eric Lai 7f1e9dbf3a soc/intel/cannonlake/acpi: Add board level s0ix call back ... Add board level s0ix call back. Since some driver doesn't care _ON/_OFF method. Add a control method for s0ix usage. BUG=b:129177593 TEST=NA Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I404f388b19355ae89b36d1fb07f9fb4f97eb3b2d Reviewed-on: https://review.coreboot.org/c/coreboot/+/32539 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>		2019-05-06 10:34:35 +00:00
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dptf.asl	soc/intel/cannonlake: Replace device name B0D4 with TCPU	2019-01-23 16:42:45 +00:00
globalnvs.asl	soc/intel/cannonlake: Fix DSDT compile remarks	2019-03-04 14:00:34 +00:00
gpio.asl	soc/intel/cannonlake: Update GPIO definitions for Virtual GPIO	2019-02-26 11:15:05 +00:00
gpio_cnp_h.asl	soc/intel/cannonlake: Add cannonlake ACPI GPIO op	2019-01-03 19:50:00 +00:00
gpio_op.asl	soc/intel/cannonlake: Add ASL functions to manipulate RX/TX buffers	2019-02-27 11:04:40 +00:00
ipu.asl
ish.asl	soc/intel/cnl/acpi: add ish ACPI device	2019-03-04 14:01:38 +00:00
lpc.asl
lpit.asl	soc/intel/cannonlake/acpi: Add board level s0ix call back	2019-05-06 10:34:35 +00:00
northbridge.asl	soc/intel/cannonlake: Fix DSDT compile remarks	2019-03-04 14:00:34 +00:00
pch_glan.asl
pch_hda.asl
pci_irqs.asl	soc/intel/cannonlake: Make static IRQ mapping for CNP PCH pci devices	2018-11-15 11:18:07 +00:00
pcie.asl	soc/intel/cannonlake: Make static IRQ mapping for CNP PCH pci devices	2018-11-15 11:18:07 +00:00
platform.asl
scs.asl	coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)	2019-03-08 08:33:24 +00:00
serialio.asl
sleepstates.asl	soc/intel/cannonlake: Enable S4 sleep state support	2018-10-25 09:21:24 +00:00
smbus.asl
southbridge.asl	coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)	2019-03-08 08:33:24 +00:00
xhci.asl