Kevin Chiu de20b28fe4 mb/google/zork: correct USB2 phy TXVREFTUNE0 parameter name ... From spec, [31:28] "HS DC Voltage Level Adjustment" is "TXVREFTUNE0". correct rx_vref_tune -> tx_vref_tune BUG=None BRANCH=zork TEST=emerge-zork coreboot Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Change-Id: I27003a952d8f8bdd8fe52af8a37010e23ee9cdfd Reviewed-on: https://review.coreboot.org/c/coreboot/+/47735 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>		2020-11-23 16:44:59 +00:00
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amd	mb/google/zork: correct USB2 phy TXVREFTUNE0 parameter name	2020-11-23 16:44:59 +00:00
cavium	soc/cavium: Drop unneeded empty lines	2020-09-22 17:14:49 +00:00
example	x86: Add a minimal example SoC along with a board	2020-10-30 21:34:18 +00:00
intel	soc/intel/cannonlake: Add ICC limits for CFL-S DT 4	2020-11-23 12:43:26 +00:00
mediatek	mediatek/mt8192: memlayout: Add DRAM DMA region	2020-11-20 08:40:58 +00:00
nvidia	soc/nvidia/tegra124/include/soc/clk_rst.h: Remove extra tab	2020-11-09 10:31:32 +00:00
qualcomm	src: Add missing 'include <console/console.h>'	2020-11-17 09:50:24 +00:00
rockchip	src: Change bare 'unsigned' to 'unsigned int'	2020-11-16 11:03:16 +00:00
samsung	src/soc/samsung: Move common headers to "common/include/soc"	2020-10-19 07:11:32 +00:00
sifive	include/console/uart: make index parameter unsigned	2020-09-12 14:59:33 +00:00
ti	soc/ti/am335x: Fix timer implementation	2020-11-22 22:32:46 +00:00
ucb	soc/ucb/riscv: Add chip_operations stub	2020-05-28 09:30:35 +00:00