Matt DeVillier e34a7705e6 soc/baytrail: fix scope for I2C ACPI devices ... For an unknown reason, the I2C ACPI devices were placed under \SB intead of \SB.PCI0, as with all other non-Atom based Intel platforms. While Linux is tolerant of this, Windows is not. Correct by moving I2C ACPI devices where they belong. Also, adjust I2C devices at board level for google/rambi as to not break compilation. Change-Id: I4ef978214aa36078dc04ee1c73b3e2b4bb22f692 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/20056 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>		2017-06-12 04:07:32 +02:00
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acpi	soc/baytrail: fix scope for I2C ACPI devices	2017-06-12 04:07:32 +02:00
bootblock	soc/intel: Unify timestamp.inc	2017-04-25 18:47:35 +02:00
include/soc	google/rambi: add explicit pull-down for ram-id	2017-02-14 13:03:53 +01:00
romstage	soc/intel/common: remove mrc cache assumptions	2016-12-15 07:51:35 +01:00
acpi.c
chip.c
chip.h
cpu.c
dptf.c
ehci.c
elog.c
emmc.c
gfx.c
gpio.c
hda.c
iosf.c
Kconfig	vboot: Select SoC-specific configuration for all Chrome OS boards	2017-03-28 22:12:54 +02:00
lpe.c
lpss.c
Makefile.inc
memmap.c
northcluster.c	soc/baytrail: fix ACPI table by recollecting TOLM	2017-06-09 16:57:13 +02:00
pcie.c	src/soc: Add required space before opening parenthesis '('	2016-08-31 20:09:42 +02:00
perf_power.c
placeholders.c
pmutil.c
ramstage.c
refcode.c
reset.c
sata.c	src/soc: Add required space before opening parenthesis '('	2016-08-31 20:09:42 +02:00
scc.c
sd.c
smihandler.c
smm.c
southcluster.c
spi.c	soc/intel: Move spi driver to use spi_bus_map	2017-05-24 04:41:21 +02:00
stage_cache.c
tsc_freq.c
xhci.c