Kyösti Mälkki 0d6ddf8da7 cpu/x86/tsc: Flip and rename TSC_CONSTANT_RATE to UNKNOWN_TSC_RATE ... The x86 timers are a bit of a mess. Cases where different stages use different counters and timestamps use different counters from udelays. The original intention was to only flip TSC_CONSTANT_RATE Kconfig to NOT_CONSTANT_TSC_RATE. The name would be incorrect though, those counters do run with a constant rate but we just lack tsc_freq_mhz() implementation for three platforms. Note that for boards with UNKNOWN_TSC_RATE=y, each stage will have a slow run of calibrate_tsc_with_pit(). This is easy enough to fix with followup implementation of tsc_freq_mhz() for the platforms. Implementations with LAPIC_MONOTONIC_TIMER typically will not have tsc_freq_mhz() implemented and default to UNKNOWN_TSC_RATE. However, as they don't use TSC for udelay() the slow calibrate_tsc_with_pit() is avoided. Because x86/tsc_delay.tsc was using two different guards and nb/via/vx900 claimed UDELAY_TSC, but pulled UDELAY_IO implementation, we also switch that romstage to use UDELAY_TSC. Change-Id: I1690cb80295d6b006b75ed69edea28899b674b68 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33928 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>		2019-11-03 06:15:35 +00:00
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acpi	soc/intel/{IA-CPU/SOC}: Move sleepstates.asl into southbridge/intel/common/acpi	2019-11-01 11:50:03 +00:00
bootblock	lib/bootblock: Add simplified entry with basetime	2019-08-26 21:11:31 +00:00
include/soc	soc/intel/{apl,cnl,dnv,icl,skl}: Move lpc.asl into common/block/acpi	2019-11-01 11:49:48 +00:00
acpi.c	soc/intel: Replace config_of_path() with config_of_soc()	2019-10-02 11:21:10 +00:00
car.c
chip.c	soc/intel/apollolake: set FSP param to enable or skip GOP	2019-10-30 08:31:43 +00:00
chip.h	soc/intel: Rename <intelblocks/chip.h>	2019-09-29 03:38:13 +00:00
cpu.c	soc/intel: common,apl,skl: remove orphaned memory locking API	2019-11-02 13:09:32 +00:00
cse.c	soc/intel/(apl,skl,cnl,common): Move mkhi_hdr structure definition to common	2019-09-25 06:26:14 +00:00
elog.c	soc/intel/common: Add SOC specific function to get XHCI USB info	2019-07-19 17:13:50 +00:00
fspcar.c
glk_page_map.txt
gpio_apl.c	soc/intel: Add GPI interrupt config register offset info	2019-04-29 12:18:27 +00:00
gpio_glk.c	soc/intel: Add GPI interrupt config register offset info	2019-04-29 12:18:27 +00:00
graphics.c	src/soc: Add missing 'include <types.h>'	2019-05-29 20:28:56 +00:00
gspi.c
heci.c
i2c.c
Kconfig	cpu/x86/tsc: Flip and rename TSC_CONSTANT_RATE to UNKNOWN_TSC_RATE	2019-11-03 06:15:35 +00:00
lpc.c	src/{device,drivers,mb,nb,soc,sb}: Remove unused 'include <console/console.h>'	2019-10-21 14:21:09 +00:00
Makefile.inc	soc,mb/intel: clean up remaining FSP2.0 socs/boards	2019-10-26 15:47:49 +00:00
meminit.c	soc/intel/apollolake: Don't use CAR_GLOBAL	2019-05-29 20:02:57 +00:00
meminit_util_apl.c	soc/intel: Provide SPD manufacturer ID and module type to SMBIOS	2019-06-21 09:17:16 +00:00
meminit_util_glk.c	soc/intel: Provide SPD manufacturer ID and module type to SMBIOS	2019-06-21 09:17:16 +00:00
memmap.c	lib/cbmem_top: Add a common cbmem_top implementation	2019-11-01 11:44:51 +00:00
mmap_boot.c	soc/intel/apollolake: Don't use CAR_GLOBAL	2019-05-29 20:02:57 +00:00
nhlt.c
pdpt.c
pmc.c	soc/intel: Drop pmc_soc_restore_power_failure()	2019-08-09 09:37:32 +00:00
pmutil.c	soc/intel: Replace config_of_path() with config_of_soc()	2019-10-02 11:21:10 +00:00
pnpconfig.c	soc/intel: Replace config_of_path() with config_of_soc()	2019-10-02 11:21:10 +00:00
pt.c
reset.c
romstage.c	soc/intel: Replace config_of_path() with config_of_soc()	2019-10-02 11:21:10 +00:00
sd.c	soc/intel: Use config_of()	2019-07-18 15:25:35 +00:00
smihandler.c	cpu/x86: Separate save_state struct headers	2019-08-13 13:59:05 +00:00
spi.c
systemagent.c
uart.c	soc/intel/common/block/uart: Update the UART PCI device reference	2019-08-04 15:16:50 +00:00
xdci.c
xhci.c	soc/intel/common: Add SOC specific function to get XHCI USB info	2019-07-19 17:13:50 +00:00