coreboot-kgpe-d16/src/soc/amd/cezanne
Martin Roth f3314c20de soc/amd/cezanne: Clear eSPI ranges before configuring eSPI
The Cezanne PSP configures the eSPI with the assumption that it's a
majolica, setting up both the serial port and the majolica EC IO decode
ranges.  Since guybrush is NOT a majolica, this doesn't work very well
there.  Clearing the decode ranges allows the guybrush platform to set
the decode ranges needed for its EC.

BUG=b:183524609
TEST=Set up eSPI on Guybrush

Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I77cfb948cb9ae6d1cf001bd9e66cede8d93f50b5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51749
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-04-05 00:44:19 +00:00
..
acpi soc/amd/cezanne: Comment the AOAC register access 2021-03-30 23:04:34 +00:00
include/soc soc/amd: move PM_RST_CTRL1 register definition to common acpimmio header 2021-03-29 18:56:36 +00:00
acpi.c soc/amd/cezanne/acpi: Generate MADT LAPIC NMI settings 2021-02-26 23:45:22 +00:00
aoac.c soc/amd/cezanne: add AOAC support 2021-01-14 15:42:34 +00:00
bootblock.c soc/amd/cezanne/bootblock: call write_resume_eip in bootblock_c_entry 2021-02-13 17:09:11 +00:00
chip.c soc/amd/cezanne: Add device tree support for I2C 2021-04-01 15:40:36 +00:00
chip.h soc/amd/cezanne: Get I2C specific code for cezanne 2021-03-22 03:43:25 +00:00
chipset.cb soc/amd/cezanne: Add i2c controllers to chipset.cb 2021-03-15 01:15:13 +00:00
config.c soc/amd/cezanne: add config.c and minimal chip.h 2020-12-06 19:05:47 +00:00
cpu.c soc/amd: move warm reset flag function prototypes to common code 2021-03-11 15:11:20 +00:00
data_fabric.c soc/amd/cezanne/data_fabric: add ACPI names and SSDT entries 2021-02-16 00:08:06 +00:00
early_fch.c soc/amd/cezanne: Clear eSPI ranges before configuring eSPI 2021-04-05 00:44:19 +00:00
fch.c soc/amd/cezanne: Initialize I2C 2021-03-22 03:44:30 +00:00
fsp_m_params.c soc/amd/cezanne: factor out UPD-M configuration from romstage 2021-03-29 19:52:22 +00:00
fsp_s_params.c soc/amd/cezanne,picasso: rename fsp_params.c to fsp_s_params.c 2021-03-29 19:52:01 +00:00
fw.cfg soc/amd/cezanne: Add PSP whitelist debug unlock support 2021-03-01 08:27:57 +00:00
gpio.c soc/amd/*/gpio: include types.h instead of stdint.h to have size_t 2021-03-29 18:47:59 +00:00
i2c.c soc/amd/cezanne: Get I2C specific code for cezanne 2021-03-22 03:43:25 +00:00
Kconfig soc/amd/cezanne: Enable GENERIC_GPIO_LIB 2021-04-01 15:40:47 +00:00
Makefile.inc soc/amd/cezanne: factor out UPD-M configuration from romstage 2021-03-29 19:52:22 +00:00
pcie_gpp.c soc/amd/cezanne/pci_gpp: Add ACPI names for GPP bridges 2021-03-18 02:33:28 +00:00
reset.c soc/amd: move warm reset flag function prototypes to common code 2021-03-11 15:11:20 +00:00
romstage.c soc/amd/cezanne: Add support to perform early EC sync 2021-04-02 16:25:03 +00:00
root_complex.c soc/amd/cezanne/acpi: Add pci0.asl 2021-02-22 07:29:31 +00:00
smihandler.c soc/amd/cezanne/smihandler: add ELOG and SMMSTORE support 2021-03-10 00:30:15 +00:00
smu.c soc/amd/cezanne: add SMU support 2021-03-04 19:55:27 +00:00
uart.c soc/amd/cezanne/uart: write ACPI tables 2021-02-17 10:35:26 +00:00
xhci.c soc/amd/cezanne: add XHCI SCI/GEVENT setup 2021-03-12 20:31:55 +00:00