coreboot-kgpe-d16/src/soc/intel/tigerlake
Tim Wawrzynczak 2dcca0f924 mb/google/volteer: Override power limits with SKU-specific limits
Using guidance from Intel, a new set of power limits (PL1, PL2 & PL4)
are available for TGL-U. They are dependent upon the SKU of the CPU
that the mainboard is running on. Volteer is updated here to use these
new limits.

To accomplish this, the SoC chip config's power_limits_config member
was expanded to an array, which can be indexed by POWER_LIMITS_*_CORE
macros. Just before power limits are applied, the correct set of them
is chosen from the array based on System Agent PCI ID. Therefore, a
TGL board should have two sets of power limits available in the
devicetree.

BUG=b:152639350
TEST=On a Volteer SKU4 (4-core), verified the following console output:
CPU PL1 = 15 Watts
CPU PL2 = 60 Watts
CPU PL4 = 105 Watts

Change-Id: I18a66fc3aacbb3ab594b2e3d6e2a4ad84c10d8f0
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42436
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
2020-06-22 12:24:11 +00:00
..
acpi soc/intel/tigerlake: Update platform.asl to ASL2.0 syntax 2020-06-22 11:59:39 +00:00
bootblock soc/intel/tigerlake: Add CPU ID for TGL B0 2020-06-06 09:38:34 +00:00
include/soc soc/intel/tigerlake: Disable VMD 2020-05-26 15:09:50 +00:00
romstage soc/intel/tigerlake: Configure TcssDma0En and TcssDma1En 2020-05-30 00:42:15 +00:00
spd/lp4x spd/lp4x: Set manufacturer part name to blank (0x20) 2020-06-08 06:42:19 +00:00
acpi.c treewide: Remove "this file is part of" lines 2020-05-11 17:11:40 +00:00
chip.c soc/intel/tigerlake: Add TCSS devices to soc_acpi_name() 2020-05-20 16:08:27 +00:00
chip.h mb/google/volteer: Override power limits with SKU-specific limits 2020-06-22 12:24:11 +00:00
cpu.c soc/intel/common: Replace smm_soutbridge_enable(SMI_FLAGS) 2020-06-16 08:03:44 +00:00
elog.c soc/intel/tigerlake: update elog to include CSME reset causes 2020-06-03 01:30:25 +00:00
espi.c soc/intel/tigerlake: Move PMC PCI resources under PMC device 2020-05-20 09:49:00 +00:00
finalize.c arch/x86: Create helper for APM_CNT SMI triggers 2020-06-16 08:02:18 +00:00
fsp_params.c soc/soch/intel/tigerlake: Integrate PCIe hot-plug config UPD 2020-06-17 09:18:45 +00:00
gpio.c treewide: Remove "this file is part of" lines 2020-05-11 17:11:40 +00:00
gspi.c treewide: Remove "this file is part of" lines 2020-05-11 17:11:40 +00:00
i2c.c treewide: Remove "this file is part of" lines 2020-05-11 17:11:40 +00:00
Kconfig soc/intel/tigerlake: Enable FSP-S compression 2020-06-18 08:33:09 +00:00
lockdown.c treewide: Remove "this file is part of" lines 2020-05-11 17:11:40 +00:00
Makefile.inc soc/intel/gma: Implement fsp_soc_get_igd_bar() in common code 2020-05-27 21:35:43 +00:00
me.c treewide: Remove "this file is part of" lines 2020-05-11 17:11:40 +00:00
meminit.c treewide: Remove "this file is part of" lines 2020-05-11 17:11:40 +00:00
p2sb.c treewide: Remove "this file is part of" lines 2020-05-11 17:11:40 +00:00
pmc.c src: Remove unused 'include <bootstate.h>' 2020-06-02 07:40:35 +00:00
pmutil.c soc/intel/tigerlake: Move pmc_soc_set_afterg3_en to pmutil 2020-05-20 09:49:26 +00:00
reset.c treewide: Remove "this file is part of" lines 2020-05-11 17:11:40 +00:00
smihandler.c treewide: Remove "this file is part of" lines 2020-05-11 17:11:40 +00:00
smmrelocate.c src: Remove unused '#include <cpu/x86/lapic.h>' 2020-06-02 07:38:45 +00:00
soundwire.c soc/intel/tigerlake: Provide SoundWire controller properties 2020-05-22 01:48:39 +00:00
spi.c treewide: Remove "this file is part of" lines 2020-05-11 17:11:40 +00:00
systemagent.c mb/google/volteer: Override power limits with SKU-specific limits 2020-06-22 12:24:11 +00:00
uart.c treewide: Remove "this file is part of" lines 2020-05-11 17:11:40 +00:00