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coreboot-kgpe-d16/src/soc/mediatek/mt8195/Makefile.inc

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soc/mediatek/mt8195: Add a stub implementation of the MT8195 SoC TEST=boot from SPI-NOR and show console message at bootblock stage. Change-Id: Ia93430006096b7410393ab31fee4ea40598d0b34 Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52258 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-01-07 13:25:54 +01:00
ifeq ($(CONFIG_SOC_MEDIATEK_MT8195),y)
soc/mediatek/mt8195: Enable mt8195 auxadc Enable auxadc on MediaTek mt8195 platform. Signed-off-by: Zhiqiang Ma <zhiqiang.ma@mediatek.com> Change-Id: Ie79420e20c9ed6155791b490e1b5e4b44a579a49 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55155 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-06-02 10:31:33 +02:00
bootblock-y += ../common/auxadc.c
soc/mediatek/mt8195: Add a stub implementation of the MT8195 SoC TEST=boot from SPI-NOR and show console message at bootblock stage. Change-Id: Ia93430006096b7410393ab31fee4ea40598d0b34 Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52258 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-01-07 13:25:54 +01:00
bootblock-y += bootblock.c
soc/mediatek/mt8195: Enable and initialize eint eint event mask register is used to mask eint wakeup source. All wakeup sources are masked by default. Since most MediaTek SoCs do not have this design, we can't modify the kernel eint upstream driver to solve the issue 'Can't wake using power button (cros_ec) or touchpad'. So we add a driver here to unmask all wakeup sources. Change-Id: I703d87e3dc49cf4e0b7ff0c75a6ea80245dd73d3 Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54007 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-19 07:59:51 +02:00
bootblock-y += ../common/eint_event.c
soc/mediatek/mt8195: Add NOR-Flash support TEST=boot to romstage on MT8195 EVB Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Change-Id: I450281fb4b1750e59cb76f6b2083f0e2889fd4cc Reviewed-on: https://review.coreboot.org/c/coreboot/+/52875 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-05-04 04:32:54 +02:00
bootblock-y += ../common/flash_controller.c
soc/mediatek/mt8195: Add GPIO driver Signed-off-by: Po Xu <jg_poxu@mediatek.corp-partner.google.com> Change-Id: Ica1b1c80a851075599442298bb6675caf5c72f57 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52598 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-02-05 09:12:29 +01:00
bootblock-y += ../common/gpio.c gpio.c
soc/mediatek/mt8195: Add i2c driver support TEST=write/read EEPROM on MT8195 EVB successfully Change-Id: Ia26e55512501e9758d7f5543d176730cf30ce03d Signed-off-by: kewei xu <kewei.xu@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/53894 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-01 04:04:20 +01:00
bootblock-y += ../common/i2c.c i2c.c
soc/mediatek/mt8195: Add a stub implementation of the MT8195 SoC TEST=boot from SPI-NOR and show console message at bootblock stage. Change-Id: Ia93430006096b7410393ab31fee4ea40598d0b34 Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52258 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-01-07 13:25:54 +01:00
bootblock-y += ../common/mmu_operations.c
soc/mediatek/mt8195: Add PLL and clock init support Add PLL and clock init code. Add frequency meter and API for raising little CPU/CCI frequency. Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com> Change-Id: I8ded0236d10826687f080bd5a213feb55d4bae03 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52667 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-03 09:20:57 +01:00
bootblock-y += ../common/pll.c pll.c
soc/mediatek/mt8195: Add SPI driver support Add SPI controller driver code. Signed-off-by: Qii Wang <qii.wang@mediatek.com> Change-Id: I674763cdb0f338e123c121ede52278cfe96df091 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52669 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-02-05 03:32:25 +01:00
bootblock-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c
soc/mediatek/mt8195: Add timer support TEST=emerge-{oak, kukui, asurada, cherry} coreboot; verified on Asurada and Cherry P0 Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Change-Id: Ic6a87e7d5983bf14ad123de82ed670a22a7be1aa Reviewed-on: https://review.coreboot.org/c/coreboot/+/52541 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-04 11:30:54 +01:00
bootblock-y += ../common/timer.c timer.c
soc/mediatek/mt8195: Add a stub implementation of the MT8195 SoC TEST=boot from SPI-NOR and show console message at bootblock stage. Change-Id: Ia93430006096b7410393ab31fee4ea40598d0b34 Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52258 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-01-07 13:25:54 +01:00
bootblock-y += ../common/uart.c
soc/mediatek/mt8195: Initialize watchdog MT8195 requires writing speical value to mode register to clear status register. This value is invalid on other platforms. We can do this safely in the common watchdog driver. Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Change-Id: Iba5b41f426fc38719bb343a220e0724bff229c79 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52542 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-04-22 07:34:04 +02:00
bootblock-y += ../common/wdt.c
soc/mediatek/mt8195: Add a stub implementation of the MT8195 SoC TEST=boot from SPI-NOR and show console message at bootblock stage. Change-Id: Ia93430006096b7410393ab31fee4ea40598d0b34 Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52258 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-01-07 13:25:54 +01:00
soc/mediatek/mt8195: Enable mt8195 auxadc Enable auxadc on MediaTek mt8195 platform. Signed-off-by: Zhiqiang Ma <zhiqiang.ma@mediatek.com> Change-Id: Ie79420e20c9ed6155791b490e1b5e4b44a579a49 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55155 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-06-02 10:31:33 +02:00
verstage-y += ../common/auxadc.c
soc/mediatek/mt8195: Add NOR-Flash support TEST=boot to romstage on MT8195 EVB Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Change-Id: I450281fb4b1750e59cb76f6b2083f0e2889fd4cc Reviewed-on: https://review.coreboot.org/c/coreboot/+/52875 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-05-04 04:32:54 +02:00
verstage-y += ../common/flash_controller.c
soc/mediatek/mt8195: Add GPIO driver Signed-off-by: Po Xu <jg_poxu@mediatek.corp-partner.google.com> Change-Id: Ica1b1c80a851075599442298bb6675caf5c72f57 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52598 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-02-05 09:12:29 +01:00
verstage-y += ../common/gpio.c gpio.c
soc/mediatek/mt8195: Add i2c driver support TEST=write/read EEPROM on MT8195 EVB successfully Change-Id: Ia26e55512501e9758d7f5543d176730cf30ce03d Signed-off-by: kewei xu <kewei.xu@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/53894 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-01 04:04:20 +01:00
verstage-y += ../common/i2c.c i2c.c
soc/mediatek/mt8195: Add SPI driver support Add SPI controller driver code. Signed-off-by: Qii Wang <qii.wang@mediatek.com> Change-Id: I674763cdb0f338e123c121ede52278cfe96df091 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52669 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-02-05 03:32:25 +01:00
verstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c
soc/mediatek/mt8195: Add timer support TEST=emerge-{oak, kukui, asurada, cherry} coreboot; verified on Asurada and Cherry P0 Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Change-Id: Ic6a87e7d5983bf14ad123de82ed670a22a7be1aa Reviewed-on: https://review.coreboot.org/c/coreboot/+/52541 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-04 11:30:54 +01:00
verstage-y += ../common/timer.c timer.c
soc/mediatek/mt8195: Add a stub implementation of the MT8195 SoC TEST=boot from SPI-NOR and show console message at bootblock stage. Change-Id: Ia93430006096b7410393ab31fee4ea40598d0b34 Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52258 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-01-07 13:25:54 +01:00
verstage-y += ../common/uart.c
soc/mediatek/mt8195: Initialize watchdog MT8195 requires writing speical value to mode register to clear status register. This value is invalid on other platforms. We can do this safely in the common watchdog driver. Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Change-Id: Iba5b41f426fc38719bb343a220e0724bff229c79 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52542 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-04-22 07:34:04 +02:00
verstage-y += ../common/wdt.c
soc/mediatek/mt8195: Add a stub implementation of the MT8195 SoC TEST=boot from SPI-NOR and show console message at bootblock stage. Change-Id: Ia93430006096b7410393ab31fee4ea40598d0b34 Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52258 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-01-07 13:25:54 +01:00
soc/mediatek/mt8195: Enable mt8195 auxadc Enable auxadc on MediaTek mt8195 platform. Signed-off-by: Zhiqiang Ma <zhiqiang.ma@mediatek.com> Change-Id: Ie79420e20c9ed6155791b490e1b5e4b44a579a49 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55155 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-06-02 10:31:33 +02:00
romstage-y += ../common/auxadc.c
soc/mediatek/mt8195: Add a stub implementation of the MT8195 SoC TEST=boot from SPI-NOR and show console message at bootblock stage. Change-Id: Ia93430006096b7410393ab31fee4ea40598d0b34 Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52258 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-01-07 13:25:54 +01:00
romstage-y += ../common/cbmem.c
soc/mediatek/mt8195: Add clk_buf driver Both mt8192 and mt8195 use mt6359p clk_buf. But mt8195 clk_buf uses legacy co-clock mode without srclken_rc. Signed-off-by: Yuchen Huang <yuchen.huang@mediatek.corp-partner.google.com> Change-Id: Ie9ee91449a7a14e77231493f807b321b2dbaa6a6 Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/53896 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-04-11 09:28:20 +02:00
romstage-y += ../common/clkbuf.c
soc/mediatek/mt8195: Initialize DRAM in romstage Initialize DRAM in romstage and configure to support fast calibration. Change-Id: I89b87be62c8e88ae4a620d56aa7a35e47f97952d Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Signed-off-by: Ryan Chuang <ryan.chuang@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54229 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-13 09:34:02 +02:00
romstage-y += ../common/dram_init.c
romstage-y += ../common/dramc_param.c
soc/mediatek/mt8195: Add a stub implementation of the MT8195 SoC TEST=boot from SPI-NOR and show console message at bootblock stage. Change-Id: Ia93430006096b7410393ab31fee4ea40598d0b34 Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52258 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-01-07 13:25:54 +01:00
romstage-y += emi.c
soc/mediatek/mt8195: Add NOR-Flash support TEST=boot to romstage on MT8195 EVB Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Change-Id: I450281fb4b1750e59cb76f6b2083f0e2889fd4cc Reviewed-on: https://review.coreboot.org/c/coreboot/+/52875 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-05-04 04:32:54 +02:00
romstage-y += ../common/flash_controller.c
soc/mediatek/mt8195: Add GPIO driver Signed-off-by: Po Xu <jg_poxu@mediatek.corp-partner.google.com> Change-Id: Ica1b1c80a851075599442298bb6675caf5c72f57 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52598 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-02-05 09:12:29 +01:00
romstage-y += ../common/gpio.c gpio.c
soc/mediatek/mt8195: Add i2c driver support TEST=write/read EEPROM on MT8195 EVB successfully Change-Id: Ia26e55512501e9758d7f5543d176730cf30ce03d Signed-off-by: kewei xu <kewei.xu@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/53894 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-01 04:04:20 +01:00
romstage-y += ../common/i2c.c i2c.c
soc/mediatek/mt8195: Initialize DRAM in romstage Initialize DRAM in romstage and configure to support fast calibration. Change-Id: I89b87be62c8e88ae4a620d56aa7a35e47f97952d Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Signed-off-by: Ryan Chuang <ryan.chuang@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54229 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-13 09:34:02 +02:00
romstage-y += ../common/memory.c
romstage-y += ../common/memory_test.c
soc/mediatek/mt8195: configure DMA buffer in DRAM Set DRAM DMA to be non-cacheable to load blob correctly. Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I819d40431fc7c9e7549686736d9e70de1c1982f0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54052 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-10 14:06:35 +02:00
romstage-y += ../common/mmu_operations.c mmu_operations.c
soc/mediatek/mt8195: Add PLL and clock init support Add PLL and clock init code. Add frequency meter and API for raising little CPU/CCI frequency. Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com> Change-Id: I8ded0236d10826687f080bd5a213feb55d4bae03 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52667 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-03 09:20:57 +01:00
romstage-y += ../common/pll.c pll.c
soc/mediatek/mt8195: Enable SCP SRAM Enable SCP SRAM to allow module in SCPSYS to access DRAM. TEST=AFE acess DRAM successfully Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I40862f8d74e5aa17361f1c91ea31a10b0a4ffb31 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54014 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-19 14:50:44 +02:00
romstage-y += scp.c
soc/mediatek/mt8195: Add SPI driver support Add SPI controller driver code. Signed-off-by: Qii Wang <qii.wang@mediatek.com> Change-Id: I674763cdb0f338e123c121ede52278cfe96df091 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52669 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-02-05 03:32:25 +01:00
romstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c
soc/mediatek/mt8195: Add timer support TEST=emerge-{oak, kukui, asurada, cherry} coreboot; verified on Asurada and Cherry P0 Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Change-Id: Ic6a87e7d5983bf14ad123de82ed670a22a7be1aa Reviewed-on: https://review.coreboot.org/c/coreboot/+/52541 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-04 11:30:54 +01:00
romstage-y += ../common/timer.c timer.c
soc/mediatek/mt8195: Add a stub implementation of the MT8195 SoC TEST=boot from SPI-NOR and show console message at bootblock stage. Change-Id: Ia93430006096b7410393ab31fee4ea40598d0b34 Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52258 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-01-07 13:25:54 +01:00
romstage-y += ../common/uart.c
soc/mediatek/mt8195: Initialize watchdog MT8195 requires writing speical value to mode register to clear status register. This value is invalid on other platforms. We can do this safely in the common watchdog driver. Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Change-Id: Iba5b41f426fc38719bb343a220e0724bff229c79 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52542 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-04-22 07:34:04 +02:00
romstage-y += ../common/wdt.c
soc/mediatek/mt8195: add pmif/spmi/pmic driver MT8195 also uses mt6359p so we can reuse most drivers. The only differences are IO configuaration, clock setting, and PMIC internal setting related to soc. Reference datasheet: MT6315 datasheet v1.4.2.pdf, RH-D-2019-0616. Reference datasheet: MT6359_PMIC_Data_Sheet_V1.5.docx, RH-D-2018-0205. Change-Id: I73f9c9bf92837f262c15758f16dacf52261dd3a3 Signed-off-by: Henry Chen <henryc.chen@mediatek.com> Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52668 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-05-03 10:25:49 +02:00
romstage-y += ../common/pmif.c ../common/pmif_clk.c pmif_clk.c
romstage-y += ../common/pmif_spi.c pmif_spi.c
romstage-y += ../common/pmif_spmi.c pmif_spmi.c
romstage-y += ../common/mt6315.c mt6315.c
romstage-y += ../common/mt6359p.c mt6359p.c
soc/mediatek/mt8195: add mt6691 driver Add mt6691 buck control for DRAM to run fast calibration test. It is needed to get and set voltage during testing. Signed-off-by: Henry Chen <henryc.chen@mediatek.com> Change-Id: I4fb9f7245d44383a6a3a0cf8d00f7f503cbdeb06 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55575 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-04 02:44:42 +01:00
romstage-y += mt6691.c
soc/mediatek/mt8195: Add mt6360 driver for PMIC access Signed-off-by: Andrew SH Cheng <andrew-sh.cheng@mediatek.com> Change-Id: Ieaf234f35f2b7d440bdf1e6ec4c455af7b311623 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55710 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-22 08:50:17 +02:00
romstage-y += mt6360.c
soc/mediatek/mt8195: Add RTC driver Both mt8192 and mt8195 use MT659P RTC. Move mt8192/rtc.c to common folder and rename to rtc_mt6359p.c. Signed-off-by: Yuchen Huang <yuchen.huang@mediatek.corp-partner.google.com> Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Change-Id: I73ea90512228a659657f2019249e7142c673e68e Reviewed-on: https://review.coreboot.org/c/coreboot/+/53897 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-01 07:39:33 +01:00
romstage-y += ../common/rtc.c ../common/rtc_osc_init.c ../common/rtc_mt6359p.c
soc/mediatek/mt8195: Add a stub implementation of the MT8195 SoC TEST=boot from SPI-NOR and show console message at bootblock stage. Change-Id: Ia93430006096b7410393ab31fee4ea40598d0b34 Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52258 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-01-07 13:25:54 +01:00
soc/mediatek/mt8195: Enable mt8195 auxadc Enable auxadc on MediaTek mt8195 platform. Signed-off-by: Zhiqiang Ma <zhiqiang.ma@mediatek.com> Change-Id: Ie79420e20c9ed6155791b490e1b5e4b44a579a49 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55155 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-06-02 10:31:33 +02:00
ramstage-y += ../common/auxadc.c
soc/mediatek/mt8195: Add ddp driver to support eDP output Add ddp (display controller) driver that supports overlay, read/write DMA, etc. The output goes to display interface DP_INTF0 directly. Add ddp gclast and output_clamp settings on mt8195 to support multi-layer display. BUG=b:189985956 Signed-off-by: Jason-JH.Lin <jason-jh.lin@mediatek.com> Change-Id: I9d5dd1025c4766218c2b1d86b9b1f97f2eab53d6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55509 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-17 18:15:23 +02:00
ramstage-y += ../common/ddp.c ddp.c
soc/mediatek/mt8195: add eDP support BUG=b:189985956 Signed-off-by: Jitao Shi <jitao.shi@mediatek.com> Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I37326ad053295aa4944c8291e4e7a7d69c8f3f63 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55573 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-29 10:26:00 +02:00
ramstage-y += dp_intf.c dptx.c dptx_hal.c
soc/mediatek/mt8195: Add a stub implementation of the MT8195 SoC TEST=boot from SPI-NOR and show console message at bootblock stage. Change-Id: Ia93430006096b7410393ab31fee4ea40598d0b34 Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52258 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-01-07 13:25:54 +01:00
ramstage-y += emi.c
soc/mediatek/mt8195: Add NOR-Flash support TEST=boot to romstage on MT8195 EVB Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Change-Id: I450281fb4b1750e59cb76f6b2083f0e2889fd4cc Reviewed-on: https://review.coreboot.org/c/coreboot/+/52875 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-05-04 04:32:54 +02:00
ramstage-y += ../common/flash_controller.c
soc/mediatek/mt8195: Add GPIO driver Signed-off-by: Po Xu <jg_poxu@mediatek.corp-partner.google.com> Change-Id: Ica1b1c80a851075599442298bb6675caf5c72f57 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52598 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-02-05 09:12:29 +01:00
ramstage-y += ../common/gpio.c gpio.c
soc/mediatek/mt8195: Add i2c driver support TEST=write/read EEPROM on MT8195 EVB successfully Change-Id: Ia26e55512501e9758d7f5543d176730cf30ce03d Signed-off-by: kewei xu <kewei.xu@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/53894 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-01 04:04:20 +01:00
ramstage-y += ../common/i2c.c i2c.c
soc/mediatek/mt8195: Initialize MCUPM Load MCUPM firmware and boot up MCUPM in ramstage. TEST=can see MCUPM log from AP console Signed-off-by: alex.miao <alex.miao@mediatek.corp-partner.google.com> Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I9e8c45ce7166644b94319ec2e7836d3d3c8008dc Reviewed-on: https://review.coreboot.org/c/coreboot/+/54899 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-05-17 15:58:55 +02:00
ramstage-y += ../common/mcu.c
ramstage-y += ../common/mcupm.c
soc/mediatek/mt8195: Turn off L2C SRAM and reconfigure as L2 cache Mediatek SoC uses part of the L2 cache as SRAM before DRAM is ready. After DRAM is ready, we should invoke disable_l2c_sram to reconfigure the L2C SRAM as L2 cache. Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Change-Id: I8777b0c8471fe17ffffdcb6ad5b7c00fb1d35db1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52925 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-25 10:50:14 +01:00
ramstage-y += ../common/mmu_operations.c mmu_operations.c
soc/mediatek/mt8195: Add mt6360 driver for PMIC access Signed-off-by: Andrew SH Cheng <andrew-sh.cheng@mediatek.com> Change-Id: Ieaf234f35f2b7d440bdf1e6ec4c455af7b311623 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55710 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-22 08:50:17 +02:00
ramstage-y += mt6360.c
soc/mediatek/mt8195: Add mtcmos init support Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com> Change-Id: If7cd1f596f1406fa21d6586510e9956bb9846a6f Reviewed-on: https://review.coreboot.org/c/coreboot/+/52882 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-02-09 10:59:26 +01:00
ramstage-y += ../common/mtcmos.c mtcmos.c
soc/mediatek/mt8195: add power and power control for eDP 1. Add API of TVD_PLL1 mt_pll_set_tvd_pll1_freq() for setting rate. 2. Add API of TVD_PLL1 edp_mux_set_sel() for mux sel. 3. Add eDP power domain control. BUG=b:189985956 Signed-off-by: Jitao Shi <jitao.shi@mediatek.com> Change-Id: I9e43e0ffeb7b8bcd1786a8d2f5acbf22d5ab501f Reviewed-on: https://review.coreboot.org/c/coreboot/+/55346 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-01 05:42:27 +02:00
ramstage-y += ../common/pll.c pll.c
soc/mediatek/mt8195: Add SPI driver support Add SPI controller driver code. Signed-off-by: Qii Wang <qii.wang@mediatek.com> Change-Id: I674763cdb0f338e123c121ede52278cfe96df091 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52669 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-02-05 03:32:25 +01:00
ramstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c
soc/mediatek/mt8195: Add a stub implementation of the MT8195 SoC TEST=boot from SPI-NOR and show console message at bootblock stage. Change-Id: Ia93430006096b7410393ab31fee4ea40598d0b34 Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52258 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-01-07 13:25:54 +01:00
ramstage-y += soc.c
soc/mediatek: Initialize SSPM Load SSPM firmware and boot up SSPM in ramstage. This adds 23ms to the boot time. TEST=Load SSPM blob ok, and we can see some logs of SSPM from AP. Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: Ia227ea9f7d58129068cb36ec2de7d9feb677006b Reviewed-on: https://review.coreboot.org/c/coreboot/+/55051 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-05-03 14:44:09 +02:00
ramstage-y += ../common/sspm.c
soc/mediatek/mt8195: add SPM loader This patch adds support for loading SPM firmware from CBFS to SPM SRAM. SPM needs its own firmware to enable SPM suspend/resume function which turns off several resources such as DRAM/mainpll/26M clk when linux system suspend. TEST=program counter of SPM is correct value after booting up. Change-Id: Ia0f9b9f86e44b293c1cc47213946304c64aea75e Signed-off-by: Dawei Chien <dawei.chien@mediatek.com> Signed-off-by: Edward-JW Yang <edward-jw.yang@mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55140 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-12 12:17:26 +02:00
ramstage-y += ../common/spm.c spm.c
soc/mediatek/mt8195: Add timer support TEST=emerge-{oak, kukui, asurada, cherry} coreboot; verified on Asurada and Cherry P0 Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Change-Id: Ic6a87e7d5983bf14ad123de82ed670a22a7be1aa Reviewed-on: https://review.coreboot.org/c/coreboot/+/52541 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-04 11:30:54 +01:00
ramstage-y += ../common/timer.c timer.c
soc/mediatek/mt8195: Add a stub implementation of the MT8195 SoC TEST=boot from SPI-NOR and show console message at bootblock stage. Change-Id: Ia93430006096b7410393ab31fee4ea40598d0b34 Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52258 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-01-07 13:25:54 +01:00
ramstage-y += ../common/uart.c
soc/mediatek/mt8195: Disable UFS reference clock UFS reference clock (refclk) is enabled by default, which will cause the UFSHCI to hold the SPM signal and lead to suspend failure. Since UFS kernel driver is not built-in, disable refclk in coreboot stage. Change UFSHCI base register to 0x11270000. Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Change-Id: I1386e59f802a9e3c938a7e8dbeea547fbcb02709 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54011 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-04-19 10:06:55 +02:00
ramstage-y += ../common/ufs.c
soc/mediatek/mt8195: Add RTC driver Both mt8192 and mt8195 use MT659P RTC. Move mt8192/rtc.c to common folder and rename to rtc_mt6359p.c. Signed-off-by: Yuchen Huang <yuchen.huang@mediatek.corp-partner.google.com> Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Change-Id: I73ea90512228a659657f2019249e7142c673e68e Reviewed-on: https://review.coreboot.org/c/coreboot/+/53897 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-01 07:39:33 +01:00
ramstage-y += ../common/usb.c usb.c
soc/mediatek/mt8195: Initialize watchdog MT8195 requires writing speical value to mode register to clear status register. This value is invalid on other platforms. We can do this safely in the common watchdog driver. Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Change-Id: Iba5b41f426fc38719bb343a220e0724bff229c79 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52542 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-04-22 07:34:04 +02:00
ramstage-y += ../common/wdt.c
soc/mediatek/mt8195: Add a stub implementation of the MT8195 SoC TEST=boot from SPI-NOR and show console message at bootblock stage. Change-Id: Ia93430006096b7410393ab31fee4ea40598d0b34 Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52258 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-01-07 13:25:54 +01:00
soc/mediatek/mt8195: enable ARM64_USE_ARM_TRUSTED_FIRMWARE Enable ATF configuration to support multi-core. TEST=boot to kernel with multi-core support. BUG=b:177593590 Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Change-Id: Id1ef29894fa3a6022574c3874dee62617133b12c Reviewed-on: https://review.coreboot.org/c/coreboot/+/53898 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-19 09:52:57 +01:00
BL31_MAKEARGS += PLAT=mt8195
soc/mediatek/mt8195: Initialize DRAM in romstage Initialize DRAM in romstage and configure to support fast calibration. Change-Id: I89b87be62c8e88ae4a620d56aa7a35e47f97952d Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Signed-off-by: Ryan Chuang <ryan.chuang@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54229 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-13 09:34:02 +02:00
MT8195_BLOB_DIR := 3rdparty/blobs/soc/mediatek/mt8195
soc/mediatek/mt8195: Initialize MCUPM Load MCUPM firmware and boot up MCUPM in ramstage. TEST=can see MCUPM log from AP console Signed-off-by: alex.miao <alex.miao@mediatek.corp-partner.google.com> Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I9e8c45ce7166644b94319ec2e7836d3d3c8008dc Reviewed-on: https://review.coreboot.org/c/coreboot/+/54899 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-05-17 15:58:55 +02:00
mcu-firmware-files := \
soc/mediatek: Initialize SSPM Load SSPM firmware and boot up SSPM in ramstage. This adds 23ms to the boot time. TEST=Load SSPM blob ok, and we can see some logs of SSPM from AP. Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: Ia227ea9f7d58129068cb36ec2de7d9feb677006b Reviewed-on: https://review.coreboot.org/c/coreboot/+/55051 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-05-03 14:44:09 +02:00
$(CONFIG_MCUPM_FIRMWARE) \
soc/mediatek/mt8195: add SPM loader This patch adds support for loading SPM firmware from CBFS to SPM SRAM. SPM needs its own firmware to enable SPM suspend/resume function which turns off several resources such as DRAM/mainpll/26M clk when linux system suspend. TEST=program counter of SPM is correct value after booting up. Change-Id: Ia0f9b9f86e44b293c1cc47213946304c64aea75e Signed-off-by: Dawei Chien <dawei.chien@mediatek.com> Signed-off-by: Edward-JW Yang <edward-jw.yang@mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55140 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-12 12:17:26 +02:00
$(CONFIG_SSPM_FIRMWARE) \
$(CONFIG_SPM_FIRMWARE)
soc/mediatek/mt8195: Initialize MCUPM Load MCUPM firmware and boot up MCUPM in ramstage. TEST=can see MCUPM log from AP console Signed-off-by: alex.miao <alex.miao@mediatek.corp-partner.google.com> Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I9e8c45ce7166644b94319ec2e7836d3d3c8008dc Reviewed-on: https://review.coreboot.org/c/coreboot/+/54899 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-05-17 15:58:55 +02:00
$(foreach fw, $(call strip_quotes,$(mcu-firmware-files)), \
$(eval $(fw)-file := $(MT8195_BLOB_DIR)/$(fw)) \
$(eval $(fw)-type := raw) \
$(eval $(fw)-compression := LZ4) \
$(if $(wildcard $($(fw)-file)), $(eval cbfs-files-y += $(fw)), ) \
)
soc/mediatek/mt8195: Initialize DRAM in romstage Initialize DRAM in romstage and configure to support fast calibration. Change-Id: I89b87be62c8e88ae4a620d56aa7a35e47f97952d Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Signed-off-by: Ryan Chuang <ryan.chuang@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54229 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-13 09:34:02 +02:00
DRAM_CBFS := $(CONFIG_CBFS_PREFIX)/dram
$(DRAM_CBFS)-file := $(MT8195_BLOB_DIR)/dram.elf
$(DRAM_CBFS)-type := stage
$(DRAM_CBFS)-compression := $(CBFS_PRERAM_COMPRESS_FLAG)
ifneq ($(wildcard $($(DRAM_CBFS)-file)),)
cbfs-files-y += $(DRAM_CBFS)
endif
soc/mediatek/mt8195: Add a stub implementation of the MT8195 SoC TEST=boot from SPI-NOR and show console message at bootblock stage. Change-Id: Ia93430006096b7410393ab31fee4ea40598d0b34 Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52258 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-01-07 13:25:54 +01:00
CPPFLAGS_common += -Isrc/soc/mediatek/mt8195/include
CPPFLAGS_common += -Isrc/soc/mediatek/common/include
soc/mediatek/mt8195: Initialize DRAM in romstage Initialize DRAM in romstage and configure to support fast calibration. Change-Id: I89b87be62c8e88ae4a620d56aa7a35e47f97952d Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Signed-off-by: Ryan Chuang <ryan.chuang@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54229 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-13 09:34:02 +02:00
CPPFLAGS_common += -Isrc/vendorcode/mediatek/mt8195/include
soc/mediatek/mt8195: Add a stub implementation of the MT8195 SoC TEST=boot from SPI-NOR and show console message at bootblock stage. Change-Id: Ia93430006096b7410393ab31fee4ea40598d0b34 Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52258 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-01-07 13:25:54 +01:00
$(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin
./util/mtkheader/gen-bl-img.py mt8183 sf $< $@
endif
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