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coreboot-kgpe-d16/src/soc/intel/skylake/acpi.c

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soc/intel/skylake: Use SPDX for GPL-2.0-only files Done with sed and God Lines. Only done for C-like code for now. Change-Id: I7354edb15ca9cbe181739bc2a148f16bb85ab118 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40218 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2020-04-05 15:47:17 +02:00
/* SPDX-License-Identifier: GPL-2.0-only */
soc/intel/skylake: Use Broadwell as comparision base for Skylake SOC Use the Broadwell implementation as the comparison base for Skylake. BRANCH=none BUG=None TEST=None Change-Id: I22eb55ea89eb0d6883f98e4c72a6d243e819e6d8 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10340 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-13 03:19:47 +02:00
acpi: Move ACPI table support out of arch/x86 (3/5) This change moves all ACPI table support in coreboot currently living under arch/x86 into common code to make it architecture independent. ACPI table generation is not really tied to any architecture and hence it makes sense to move this to its own directory. In order to make it easier to review, this change is being split into multiple CLs. This is change 3/5 which basically is generated by running the following command: $ git grep -iIl "arch/acpi" | xargs sed -i 's/arch\/acpi/acpi\/acpi/g' BUG=b:155428745 Change-Id: I16b1c45d954d6440fb9db1d3710063a47b582eae Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40938 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-05-02 19:24:23 +02:00
#include <acpi/acpi.h>
ACPI: Drop typedef global_nvs_t Bring all GNVS related initialisation function to global scope to force identical signatures. Followup work is likely to remove some as duplicates. Change-Id: Id4299c41d79c228f3d35bc7cb9bf427ce1e82ba1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42489 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-17 22:37:49 +02:00
#include <acpi/acpi_gnvs.h>
ACPI: Add helpers for CBMEM_ID_POWER_STATE Create uniform logging for the (unlikely) case of a CBMEM entry disappearing. Change-Id: I7c5414a03d869423c8ae5192a990fde5f9582f2d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49817 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-01-21 15:05:26 +01:00
#include <acpi/acpi_pm.h>
acpi: Move ACPI table support out of arch/x86 (3/5) This change moves all ACPI table support in coreboot currently living under arch/x86 into common code to make it architecture independent. ACPI table generation is not really tied to any architecture and hence it makes sense to move this to its own directory. In order to make it easier to review, this change is being split into multiple CLs. This is change 3/5 which basically is generated by running the following command: $ git grep -iIl "arch/acpi" | xargs sed -i 's/arch\/acpi/acpi\/acpi/g' BUG=b:155428745 Change-Id: I16b1c45d954d6440fb9db1d3710063a47b582eae Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40938 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-05-02 19:24:23 +02:00
#include <acpi/acpigen.h>
intel/skylake: Add support for Gfx PEIM (AKA GOP) This patch implements the igd_opregion using the write_acpi_tables mechanism to support GOP usage. BRANCH=none BUG=chrome-os-partner:44559 TEST=W/o GOP_SUPPORT in config, Built and boot on kunimitsu/glados. W/ GOP_SUPPORT enabled, build and boot on kunimitsu/glados, but on glados Dev screen can not be seen (OS display is fine). CQ-DEPEND=CL:303539 Change-Id: I4cd63dfe0d3f456c5f084e38db976425143f79e7 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 4db57463a69c6114b1e2ed4035d378ee3a82783f Original-Change-Id: I6f3c29c1b608eeaad8f2bf79d17394d49f8e412c Original-Signed-off-by: robbie zhang <robbie.zhang@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/303387 Original-Commit-Ready: Robbie Zhang <robbie.zhang@intel.com> Original-Tested-by: Robbie Zhang <robbie.zhang@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/12142 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-02 02:21:33 +02:00
#include <arch/cpu.h>
skylake: Move ACPI init to SOC instead of mainboard Move some remaining ACPI init code to the SOC instead of being done in each mainboard: - acpi_create_gnvs is now a local function - add a weak acpi_mainboard_gnvs() that can be used for mainboards to override or set additional NVS - add acpi_fill_madt() function for skylake - remove acpi_create_serialio_ssdt() function as it is unused BUG=chrome-os-partner:40635 BRANCH=none TEST=emerge-glados coreboot Change-Id: I52225e8d38ed846c29d44872e3f4d6ebaf4a7e52 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: c717bb418a0cb6002582572632e42b44b473f718 Original-Change-Id: I0910ac8ef25de265ae1fde16b68f6cbacedb4462 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/297800 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11581 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-04 23:19:35 +02:00
#include <arch/ioapic.h>
soc/intel/skylake: Use Broadwell as comparision base for Skylake SOC Use the Broadwell implementation as the comparison base for Skylake. BRANCH=none BUG=None TEST=None Change-Id: I22eb55ea89eb0d6883f98e4c72a6d243e819e6d8 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10340 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-13 03:19:47 +02:00
#include <arch/smp/mpspec.h>
#include <console/console.h>
#include <cpu/x86/smm.h>
#include <cpu/x86/msr.h>
soc/intel/skylake: add CPPC support ACPI 5.0 defines a method _CPC for "Continuous Performance Control" (CPPC). Linux has a driver that enables features like speed shift without consulting ACPI. Other OSes instead rely on this information and need a _CPC present. Prior to this change performance in Win10 never exceeds 80% and MSR 0x770 is 0, while with this change (and enabling eist) higher speeds can be achieved and the MSR value is now 1. Change-Id: Ib7e0ae13f4b664b51e42f963e53c71f8832be062 Signed-off-by: Matt Delco <delco@chromium.org> Reviewed-on: https://review.coreboot.org/27673 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2018-07-27 23:17:29 +02:00
#include <cpu/intel/common/common.h>
soc/intel/skylake: Use Broadwell as comparision base for Skylake SOC Use the Broadwell implementation as the comparison base for Skylake. BRANCH=none BUG=None TEST=None Change-Id: I22eb55ea89eb0d6883f98e4c72a6d243e819e6d8 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10340 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-13 03:19:47 +02:00
#include <cpu/intel/turbo.h>
soc/intel/skylake: Use CPU common library code This patch makes SOC files to use common/block/cpu/cpulib.c file's helper functions. Change-Id: I6af56564c6f488f58173ba0beda6912763706f9f Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/19566 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-05-04 14:32:17 +02:00
#include <intelblocks/cpulib.h>
soc/intel/skylake: Enable common LPC IP Enable Skylake to use the new common LPC code. This will help to reduce code duplication and streamline code bring up. Change-Id: I042e459fb7c07f024a7f6a5fe7da13eb5f0dd688 Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Reviewed-on: https://review.coreboot.org/20120 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-29 02:06:01 +02:00
#include <intelblocks/lpc_lib.h>
soc/intel/skylake: update GNVS with SGX data - Call sgx_fill_gnvs to update GNVS data, if CONFIG_SOC_INTEL_COMMON_BLOCK_SGX is set. - With this patch SGX ACPI device would get pached with enumaretd values of ECP device status, base address and length Change-Id: Ief0531fbab34838a3f8adb9cdc7d3fe19203c432 Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/21972 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-12 01:12:21 +02:00
#include <intelblocks/sgx.h>
soc/intel: Enable ACPI DBG2 table generation Enable the ACPI DBG2 table generation for Intel boards. This is a Microsoft defined ACPI extension that allows an OS to know what the debug port is on a system when it is not enabled by the firmware, so it does not show up in the coreboot tables and cannot be easily found by a payload. broadwell: Use byte access device, set up only when enabled since it relies on the port being put in byte access mode and using this serial port for debug was not standard in this generation. skylake: Enable for the configured debug port. Skylake uses intelblocks for UART but not ACPI. common: Enable for the configured debug port. This affects apollolake and cannonlake. Tested by compiling for apollolake/broadwell, tested by reading the DBG2 ACPI table on kabylake board and using IASL to dump: [000h 0000 4] Signature : "DBG2" [004h 0004 4] Table Length : 00000061 [008h 0008 1] Revision : 00 [009h 0009 1] Checksum : 3B [00Ah 0010 6] Oem ID : "CORE " [010h 0016 8] Oem Table ID : "COREBOOT" [018h 0024 4] Oem Revision : 00000000 [01Ch 0028 4] Asl Compiler ID : "CORE" [020h 0032 4] Asl Compiler Revision : 00000000 [024h 0036 4] Info Offset : 0000002C [028h 0040 4] Info Count : 00000001 [02Ch 0044 1] Revision : 00 [02Dh 0045 2] Length : 0035 [02Fh 0047 1] Register Count : 01 [030h 0048 2] Namepath Length : 000F [032h 0050 2] Namepath Offset : 0026 [034h 0052 2] OEM Data Length : 0000 [036h 0054 2] OEM Data Offset : 0000 [038h 0056 2] Port Type : 8000 [03Ah 0058 2] Port Subtype : 0000 [03Ch 0060 2] Reserved : 0000 [03Eh 0062 2] Base Address Offset : 0016 [040h 0064 2] Address Size Offset : 0022 [042h 0066 12] Base Address Register : [Generic Address Structure] [042h 0066 1] Space ID : 00 [SystemMemory] [043h 0067 1] Bit Width : 00 [044h 0068 1] Bit Offset : 00 [045h 0069 1] Encoded Access Width : 03 [DWord Access:32] [046h 0070 8] Address : 00000000FE034000 [04Eh 0078 4] Address Size : 00001000 [052h 0082 15] Namepath : "\_SB.PCI0.UAR2" Change-Id: If34a3d2252896e0b0f762136760ab981afc12a2f Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/22453 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-12 05:03:29 +01:00
#include <intelblocks/uart.h>
soc/intel/skylake: Generate ACPI DMAR table If the SoC is VT-d capable, write an ACPI DMAR table. The entry for the GFXVTBAR is only generated if the IGD is enabled. Change-Id: I8176401dd19aee7ad09a8a145b7a3801fe5b2ae1 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/21588 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Youness Alaoui <snifikino@gmail.com>
2017-09-18 20:03:46 +02:00
#include <intelblocks/systemagent.h>
skylake: Use common ACPI _SWS code Enable and use the common code for filling out the NVS data used by the _SWS methods. Add a function to provide the wake source data. With Deep S3 enabled skylake does not retain the contents of the PM1_EN register so instead just select the wake related events in PM1_STS. BUG=chrome-os-partner:40635 BRANCH=none TEST=tested on glados by checking for valid _SWS string in /sys/firmware/log after suspend/resume. Wake sources that were tested are RTC, power button, keypress, trackpad, and wifi. Change-Id: I93a4f740f2e2ef1c34e948db1d8e273332296921 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: cb4d4705b87ef7169f1979009c34a58de93c4ef0 Original-Change-Id: Ib6b4df09ea3090894f09290d00dcdc5aebc3eabb Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/298169 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11648 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-09 01:12:44 +02:00
#include <soc/intel/common/acpi.h>
soc/intel/skylake: Use Broadwell as comparision base for Skylake SOC Use the Broadwell implementation as the comparison base for Skylake. BRANCH=none BUG=None TEST=None Change-Id: I22eb55ea89eb0d6883f98e4c72a6d243e819e6d8 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10340 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-13 03:19:47 +02:00
#include <soc/acpi.h>
#include <soc/cpu.h>
#include <soc/iomap.h>
#include <soc/msr.h>
soc/intel: Drop indirect <soc/nvs.h> include Change-Id: Ia19018685749efdd543cb09c06df117690ab9d66 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48803 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-21 14:17:01 +01:00
#include <soc/nvs.h>
soc/intel/skylake: Use Broadwell as comparision base for Skylake SOC Use the Broadwell implementation as the comparison base for Skylake. BRANCH=none BUG=None TEST=None Change-Id: I22eb55ea89eb0d6883f98e4c72a6d243e819e6d8 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10340 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-13 03:19:47 +02:00
#include <soc/pci_devs.h>
#include <soc/pm.h>
soc/intel/skylake: Add FSP 2.0 support in ramstage Add FSP 2.0 support in ramstage. Populate required Fsp Silicon Init params and configure mainboard specific GPIOs. Define function fsp_soc_get_igd_bar needed by fsp2.0 driver for pre OS screens. Change-Id: Ib38ca7547b5d5ec2b268698b8886d5caa28d6497 Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/16592 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-08-30 17:17:13 +02:00
#include <soc/ramstage.h>
soc/intel/skylake: Generate ACPI DMAR table If the SoC is VT-d capable, write an ACPI DMAR table. The entry for the GFXVTBAR is only generated if the IGD is enabled. Change-Id: I8176401dd19aee7ad09a8a145b7a3801fe5b2ae1 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/21588 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Youness Alaoui <snifikino@gmail.com>
2017-09-18 20:03:46 +02:00
#include <soc/systemagent.h>
intel/skylake: Add support for Gfx PEIM (AKA GOP) This patch implements the igd_opregion using the write_acpi_tables mechanism to support GOP usage. BRANCH=none BUG=chrome-os-partner:44559 TEST=W/o GOP_SUPPORT in config, Built and boot on kunimitsu/glados. W/ GOP_SUPPORT enabled, build and boot on kunimitsu/glados, but on glados Dev screen can not be seen (OS display is fine). CQ-DEPEND=CL:303539 Change-Id: I4cd63dfe0d3f456c5f084e38db976425143f79e7 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 4db57463a69c6114b1e2ed4035d378ee3a82783f Original-Change-Id: I6f3c29c1b608eeaad8f2bf79d17394d49f8e412c Original-Signed-off-by: robbie zhang <robbie.zhang@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/303387 Original-Commit-Ready: Robbie Zhang <robbie.zhang@intel.com> Original-Tested-by: Robbie Zhang <robbie.zhang@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/12142 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-02 02:21:33 +02:00
#include <string.h>
#include <types.h>
skylake: Add and fill out CID1 NVS field Add a country identifier field to NVS and populate it with the call to wifi_regulatory_domain() which will (by default) do a lookup for the 'region' identifier in VPD on a Chrome OS device. BUG=chrome-os-partner:50516 BRANCH=glados TEST=build and boot on chell Change-Id: Ie7531848e620095732772c22156a85b7f8a6df5c Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: dafdb3760a0302e3effdc0e83977c1bfd5c9d3b2 Original-Change-Id: Ic83ab008045a469d0e0756f7e4d42f1b3894c529 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/329295 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13839 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-25 17:45:43 +01:00
#include <wrdd.h>
pci: Move inline PCI functions to pci_ops.h Move inline function where they belong to. Fixes compilation on non x86 platforms. Change-Id: Ia05391c43b8d501bd68df5654bcfb587f8786f71 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/25720 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-18 10:11:59 +02:00
#include <device/pci_ops.h>
soc/intel/skylake: Use Broadwell as comparision base for Skylake SOC Use the Broadwell implementation as the comparison base for Skylake. BRANCH=none BUG=None TEST=None Change-Id: I22eb55ea89eb0d6883f98e4c72a6d243e819e6d8 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10340 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-13 03:19:47 +02:00
soc/{amd,intel}/chip: Use local include for chip.h Change-Id: Ic1fcbf4b54b7d0b5cda04ca9f7fc145050c867b8 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32014 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-03-21 15:38:06 +01:00
#include "chip.h"
soc/intel/skl: replace conditional on dt option reading CPUID for CPPC Check ISST (Intel SpeedShift) availability via CPUID.06H:EAX[7], instead of relying on the devicetree option `speed_shift_enable`, that is going to be dropped. Test: GCPC and _CPC entries still get generated on Supermicro X11SSM-F Change-Id: I5f9bf09385627fb6a1d8e566a80370f7ddd8605e Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46461 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-15 00:27:59 +02:00
#define CPUID_6_EAX_ISST (1 << 7)
soc/intel/skylake: Use Broadwell as comparision base for Skylake SOC Use the Broadwell implementation as the comparison base for Skylake. BRANCH=none BUG=None TEST=None Change-Id: I22eb55ea89eb0d6883f98e4c72a6d243e819e6d8 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10340 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-13 03:19:47 +02:00
/*
soc/intel: Add Skylake SOC support Add the files to support the Skylake SOC. Matches chromium tree at 927026db BRANCH=none BUG=None TEST=Build and run on a Skylake platform Change-Id: I80248f7e47eaf13b52e3c7ff951eb1976edbaa15 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10341 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-05-13 03:23:27 +02:00
* List of suported C-states in this processor.
soc/intel/skylake: Use Broadwell as comparision base for Skylake SOC Use the Broadwell implementation as the comparison base for Skylake. BRANCH=none BUG=None TEST=None Change-Id: I22eb55ea89eb0d6883f98e4c72a6d243e819e6d8 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10340 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-13 03:19:47 +02:00
*/
enum {
soc/intel: Add Skylake SOC support Add the files to support the Skylake SOC. Matches chromium tree at 927026db BRANCH=none BUG=None TEST=Build and run on a Skylake platform Change-Id: I80248f7e47eaf13b52e3c7ff951eb1976edbaa15 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10341 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-05-13 03:23:27 +02:00
C_STATE_C0, /* 0 */
C_STATE_C1, /* 1 */
C_STATE_C1E, /* 2 */
C_STATE_C3, /* 3 */
C_STATE_C6_SHORT_LAT, /* 4 */
C_STATE_C6_LONG_LAT, /* 5 */
C_STATE_C7_SHORT_LAT, /* 6 */
C_STATE_C7_LONG_LAT, /* 7 */
C_STATE_C7S_SHORT_LAT, /* 8 */
C_STATE_C7S_LONG_LAT, /* 9 */
C_STATE_C8, /* 10 */
C_STATE_C9, /* 11 */
C_STATE_C10, /* 12 */
soc/intel/skylake: Use Broadwell as comparision base for Skylake SOC Use the Broadwell implementation as the comparison base for Skylake. BRANCH=none BUG=None TEST=None Change-Id: I22eb55ea89eb0d6883f98e4c72a6d243e819e6d8 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10340 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-13 03:19:47 +02:00
NUM_C_STATES
};
soc/intel: Add Skylake SOC support Add the files to support the Skylake SOC. Matches chromium tree at 927026db BRANCH=none BUG=None TEST=Build and run on a Skylake platform Change-Id: I80248f7e47eaf13b52e3c7ff951eb1976edbaa15 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10341 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-05-13 03:23:27 +02:00
#define MWAIT_RES(state, sub_state) \
{ \
.addrl = (((state) << 4) | (sub_state)), \
.space_id = ACPI_ADDRESS_SPACE_FIXED, \
.bit_width = ACPI_FFIXEDHW_VENDOR_INTEL, \
.bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT, \
.access_size = ACPI_FFIXEDHW_FLAG_HW_COORD, \
soc/intel/skylake: Use Broadwell as comparision base for Skylake SOC Use the Broadwell implementation as the comparison base for Skylake. BRANCH=none BUG=None TEST=None Change-Id: I22eb55ea89eb0d6883f98e4c72a6d243e819e6d8 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10340 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-13 03:19:47 +02:00
}
static acpi_cstate_t cstate_map[NUM_C_STATES] = {
[C_STATE_C0] = { },
[C_STATE_C1] = {
.latency = 0,
Skylake: update C state latency and power numbers The values are taken from latest BWG as well fsp src. BRANCH=none BUG=chrome-os-partner:45208 TEST=Built and boot on kunimitsu Signed-off-by: Robbie Zhang <robbie.zhang@intel.com> Change-Id: Ia6bd336a71b0313801b59990c78822fa0d789e36 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: c955ab43245153d76932daa527f1b5ebea859164 Original-Change-Id: I3f7307951753c2bbe6319f627a82a93359c4e61b Original-Reviewed-on: https://chromium-review.googlesource.com/299480 Original-Commit-Ready: Wenkai Du <wenkai.du@intel.com> Original-Tested-by: Wenkai Du <wenkai.du@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11659 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-11 23:25:15 +02:00
.power = C1_POWER,
soc/intel: Add Skylake SOC support Add the files to support the Skylake SOC. Matches chromium tree at 927026db BRANCH=none BUG=None TEST=Build and run on a Skylake platform Change-Id: I80248f7e47eaf13b52e3c7ff951eb1976edbaa15 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10341 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-05-13 03:23:27 +02:00
.resource = MWAIT_RES(0, 0),
soc/intel/skylake: Use Broadwell as comparision base for Skylake SOC Use the Broadwell implementation as the comparison base for Skylake. BRANCH=none BUG=None TEST=None Change-Id: I22eb55ea89eb0d6883f98e4c72a6d243e819e6d8 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10340 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-13 03:19:47 +02:00
},
[C_STATE_C1E] = {
.latency = 0,
Skylake: update C state latency and power numbers The values are taken from latest BWG as well fsp src. BRANCH=none BUG=chrome-os-partner:45208 TEST=Built and boot on kunimitsu Signed-off-by: Robbie Zhang <robbie.zhang@intel.com> Change-Id: Ia6bd336a71b0313801b59990c78822fa0d789e36 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: c955ab43245153d76932daa527f1b5ebea859164 Original-Change-Id: I3f7307951753c2bbe6319f627a82a93359c4e61b Original-Reviewed-on: https://chromium-review.googlesource.com/299480 Original-Commit-Ready: Wenkai Du <wenkai.du@intel.com> Original-Tested-by: Wenkai Du <wenkai.du@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11659 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-11 23:25:15 +02:00
.power = C1_POWER,
soc/intel: Add Skylake SOC support Add the files to support the Skylake SOC. Matches chromium tree at 927026db BRANCH=none BUG=None TEST=Build and run on a Skylake platform Change-Id: I80248f7e47eaf13b52e3c7ff951eb1976edbaa15 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10341 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-05-13 03:23:27 +02:00
.resource = MWAIT_RES(0, 1),
soc/intel/skylake: Use Broadwell as comparision base for Skylake SOC Use the Broadwell implementation as the comparison base for Skylake. BRANCH=none BUG=None TEST=None Change-Id: I22eb55ea89eb0d6883f98e4c72a6d243e819e6d8 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10340 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-13 03:19:47 +02:00
},
[C_STATE_C3] = {
.latency = C_STATE_LATENCY_FROM_LAT_REG(0),
Skylake: update C state latency and power numbers The values are taken from latest BWG as well fsp src. BRANCH=none BUG=chrome-os-partner:45208 TEST=Built and boot on kunimitsu Signed-off-by: Robbie Zhang <robbie.zhang@intel.com> Change-Id: Ia6bd336a71b0313801b59990c78822fa0d789e36 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: c955ab43245153d76932daa527f1b5ebea859164 Original-Change-Id: I3f7307951753c2bbe6319f627a82a93359c4e61b Original-Reviewed-on: https://chromium-review.googlesource.com/299480 Original-Commit-Ready: Wenkai Du <wenkai.du@intel.com> Original-Tested-by: Wenkai Du <wenkai.du@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11659 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-11 23:25:15 +02:00
.power = C3_POWER,
soc/intel/skylake: Use Broadwell as comparision base for Skylake SOC Use the Broadwell implementation as the comparison base for Skylake. BRANCH=none BUG=None TEST=None Change-Id: I22eb55ea89eb0d6883f98e4c72a6d243e819e6d8 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10340 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-13 03:19:47 +02:00
.resource = MWAIT_RES(1, 0),
},
[C_STATE_C6_SHORT_LAT] = {
.latency = C_STATE_LATENCY_FROM_LAT_REG(1),
Skylake: update C state latency and power numbers The values are taken from latest BWG as well fsp src. BRANCH=none BUG=chrome-os-partner:45208 TEST=Built and boot on kunimitsu Signed-off-by: Robbie Zhang <robbie.zhang@intel.com> Change-Id: Ia6bd336a71b0313801b59990c78822fa0d789e36 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: c955ab43245153d76932daa527f1b5ebea859164 Original-Change-Id: I3f7307951753c2bbe6319f627a82a93359c4e61b Original-Reviewed-on: https://chromium-review.googlesource.com/299480 Original-Commit-Ready: Wenkai Du <wenkai.du@intel.com> Original-Tested-by: Wenkai Du <wenkai.du@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11659 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-11 23:25:15 +02:00
.power = C6_POWER,
soc/intel/skylake: Use Broadwell as comparision base for Skylake SOC Use the Broadwell implementation as the comparison base for Skylake. BRANCH=none BUG=None TEST=None Change-Id: I22eb55ea89eb0d6883f98e4c72a6d243e819e6d8 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10340 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-13 03:19:47 +02:00
.resource = MWAIT_RES(2, 0),
},
[C_STATE_C6_LONG_LAT] = {
.latency = C_STATE_LATENCY_FROM_LAT_REG(2),
Skylake: update C state latency and power numbers The values are taken from latest BWG as well fsp src. BRANCH=none BUG=chrome-os-partner:45208 TEST=Built and boot on kunimitsu Signed-off-by: Robbie Zhang <robbie.zhang@intel.com> Change-Id: Ia6bd336a71b0313801b59990c78822fa0d789e36 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: c955ab43245153d76932daa527f1b5ebea859164 Original-Change-Id: I3f7307951753c2bbe6319f627a82a93359c4e61b Original-Reviewed-on: https://chromium-review.googlesource.com/299480 Original-Commit-Ready: Wenkai Du <wenkai.du@intel.com> Original-Tested-by: Wenkai Du <wenkai.du@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11659 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-11 23:25:15 +02:00
.power = C6_POWER,
soc/intel/skylake: Use Broadwell as comparision base for Skylake SOC Use the Broadwell implementation as the comparison base for Skylake. BRANCH=none BUG=None TEST=None Change-Id: I22eb55ea89eb0d6883f98e4c72a6d243e819e6d8 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10340 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-13 03:19:47 +02:00
.resource = MWAIT_RES(2, 1),
},
[C_STATE_C7_SHORT_LAT] = {
.latency = C_STATE_LATENCY_FROM_LAT_REG(1),
Skylake: update C state latency and power numbers The values are taken from latest BWG as well fsp src. BRANCH=none BUG=chrome-os-partner:45208 TEST=Built and boot on kunimitsu Signed-off-by: Robbie Zhang <robbie.zhang@intel.com> Change-Id: Ia6bd336a71b0313801b59990c78822fa0d789e36 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: c955ab43245153d76932daa527f1b5ebea859164 Original-Change-Id: I3f7307951753c2bbe6319f627a82a93359c4e61b Original-Reviewed-on: https://chromium-review.googlesource.com/299480 Original-Commit-Ready: Wenkai Du <wenkai.du@intel.com> Original-Tested-by: Wenkai Du <wenkai.du@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11659 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-11 23:25:15 +02:00
.power = C7_POWER,
soc/intel/skylake: Use Broadwell as comparision base for Skylake SOC Use the Broadwell implementation as the comparison base for Skylake. BRANCH=none BUG=None TEST=None Change-Id: I22eb55ea89eb0d6883f98e4c72a6d243e819e6d8 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10340 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-13 03:19:47 +02:00
.resource = MWAIT_RES(3, 0),
},
[C_STATE_C7_LONG_LAT] = {
.latency = C_STATE_LATENCY_FROM_LAT_REG(2),
Skylake: update C state latency and power numbers The values are taken from latest BWG as well fsp src. BRANCH=none BUG=chrome-os-partner:45208 TEST=Built and boot on kunimitsu Signed-off-by: Robbie Zhang <robbie.zhang@intel.com> Change-Id: Ia6bd336a71b0313801b59990c78822fa0d789e36 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: c955ab43245153d76932daa527f1b5ebea859164 Original-Change-Id: I3f7307951753c2bbe6319f627a82a93359c4e61b Original-Reviewed-on: https://chromium-review.googlesource.com/299480 Original-Commit-Ready: Wenkai Du <wenkai.du@intel.com> Original-Tested-by: Wenkai Du <wenkai.du@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11659 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-11 23:25:15 +02:00
.power = C7_POWER,
soc/intel/skylake: Use Broadwell as comparision base for Skylake SOC Use the Broadwell implementation as the comparison base for Skylake. BRANCH=none BUG=None TEST=None Change-Id: I22eb55ea89eb0d6883f98e4c72a6d243e819e6d8 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10340 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-13 03:19:47 +02:00
.resource = MWAIT_RES(3, 1),
},
[C_STATE_C7S_SHORT_LAT] = {
.latency = C_STATE_LATENCY_FROM_LAT_REG(1),
Skylake: update C state latency and power numbers The values are taken from latest BWG as well fsp src. BRANCH=none BUG=chrome-os-partner:45208 TEST=Built and boot on kunimitsu Signed-off-by: Robbie Zhang <robbie.zhang@intel.com> Change-Id: Ia6bd336a71b0313801b59990c78822fa0d789e36 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: c955ab43245153d76932daa527f1b5ebea859164 Original-Change-Id: I3f7307951753c2bbe6319f627a82a93359c4e61b Original-Reviewed-on: https://chromium-review.googlesource.com/299480 Original-Commit-Ready: Wenkai Du <wenkai.du@intel.com> Original-Tested-by: Wenkai Du <wenkai.du@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11659 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-11 23:25:15 +02:00
.power = C7_POWER,
soc/intel/skylake: Use Broadwell as comparision base for Skylake SOC Use the Broadwell implementation as the comparison base for Skylake. BRANCH=none BUG=None TEST=None Change-Id: I22eb55ea89eb0d6883f98e4c72a6d243e819e6d8 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10340 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-13 03:19:47 +02:00
.resource = MWAIT_RES(3, 2),
},
[C_STATE_C7S_LONG_LAT] = {
.latency = C_STATE_LATENCY_FROM_LAT_REG(2),
Skylake: update C state latency and power numbers The values are taken from latest BWG as well fsp src. BRANCH=none BUG=chrome-os-partner:45208 TEST=Built and boot on kunimitsu Signed-off-by: Robbie Zhang <robbie.zhang@intel.com> Change-Id: Ia6bd336a71b0313801b59990c78822fa0d789e36 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: c955ab43245153d76932daa527f1b5ebea859164 Original-Change-Id: I3f7307951753c2bbe6319f627a82a93359c4e61b Original-Reviewed-on: https://chromium-review.googlesource.com/299480 Original-Commit-Ready: Wenkai Du <wenkai.du@intel.com> Original-Tested-by: Wenkai Du <wenkai.du@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11659 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-11 23:25:15 +02:00
.power = C7_POWER,
soc/intel/skylake: Use Broadwell as comparision base for Skylake SOC Use the Broadwell implementation as the comparison base for Skylake. BRANCH=none BUG=None TEST=None Change-Id: I22eb55ea89eb0d6883f98e4c72a6d243e819e6d8 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10340 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-13 03:19:47 +02:00
.resource = MWAIT_RES(3, 3),
},
[C_STATE_C8] = {
.latency = C_STATE_LATENCY_FROM_LAT_REG(3),
Skylake: update C state latency and power numbers The values are taken from latest BWG as well fsp src. BRANCH=none BUG=chrome-os-partner:45208 TEST=Built and boot on kunimitsu Signed-off-by: Robbie Zhang <robbie.zhang@intel.com> Change-Id: Ia6bd336a71b0313801b59990c78822fa0d789e36 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: c955ab43245153d76932daa527f1b5ebea859164 Original-Change-Id: I3f7307951753c2bbe6319f627a82a93359c4e61b Original-Reviewed-on: https://chromium-review.googlesource.com/299480 Original-Commit-Ready: Wenkai Du <wenkai.du@intel.com> Original-Tested-by: Wenkai Du <wenkai.du@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11659 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-11 23:25:15 +02:00
.power = C8_POWER,
soc/intel/skylake: Use Broadwell as comparision base for Skylake SOC Use the Broadwell implementation as the comparison base for Skylake. BRANCH=none BUG=None TEST=None Change-Id: I22eb55ea89eb0d6883f98e4c72a6d243e819e6d8 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10340 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-13 03:19:47 +02:00
.resource = MWAIT_RES(4, 0),
},
[C_STATE_C9] = {
.latency = C_STATE_LATENCY_FROM_LAT_REG(4),
Skylake: update C state latency and power numbers The values are taken from latest BWG as well fsp src. BRANCH=none BUG=chrome-os-partner:45208 TEST=Built and boot on kunimitsu Signed-off-by: Robbie Zhang <robbie.zhang@intel.com> Change-Id: Ia6bd336a71b0313801b59990c78822fa0d789e36 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: c955ab43245153d76932daa527f1b5ebea859164 Original-Change-Id: I3f7307951753c2bbe6319f627a82a93359c4e61b Original-Reviewed-on: https://chromium-review.googlesource.com/299480 Original-Commit-Ready: Wenkai Du <wenkai.du@intel.com> Original-Tested-by: Wenkai Du <wenkai.du@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11659 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-11 23:25:15 +02:00
.power = C9_POWER,
soc/intel/skylake: Use Broadwell as comparision base for Skylake SOC Use the Broadwell implementation as the comparison base for Skylake. BRANCH=none BUG=None TEST=None Change-Id: I22eb55ea89eb0d6883f98e4c72a6d243e819e6d8 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10340 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-13 03:19:47 +02:00
.resource = MWAIT_RES(5, 0),
},
[C_STATE_C10] = {
.latency = C_STATE_LATENCY_FROM_LAT_REG(5),
Skylake: update C state latency and power numbers The values are taken from latest BWG as well fsp src. BRANCH=none BUG=chrome-os-partner:45208 TEST=Built and boot on kunimitsu Signed-off-by: Robbie Zhang <robbie.zhang@intel.com> Change-Id: Ia6bd336a71b0313801b59990c78822fa0d789e36 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: c955ab43245153d76932daa527f1b5ebea859164 Original-Change-Id: I3f7307951753c2bbe6319f627a82a93359c4e61b Original-Reviewed-on: https://chromium-review.googlesource.com/299480 Original-Commit-Ready: Wenkai Du <wenkai.du@intel.com> Original-Tested-by: Wenkai Du <wenkai.du@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11659 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-11 23:25:15 +02:00
.power = C10_POWER,
soc/intel/skylake: Use Broadwell as comparision base for Skylake SOC Use the Broadwell implementation as the comparison base for Skylake. BRANCH=none BUG=None TEST=None Change-Id: I22eb55ea89eb0d6883f98e4c72a6d243e819e6d8 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10340 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-13 03:19:47 +02:00
.resource = MWAIT_RES(6, 0),
},
};
soc/intel: Add Skylake SOC support Add the files to support the Skylake SOC. Matches chromium tree at 927026db BRANCH=none BUG=None TEST=Build and run on a Skylake platform Change-Id: I80248f7e47eaf13b52e3c7ff951eb1976edbaa15 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10341 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-05-13 03:23:27 +02:00
static int cstate_set_s0ix[] = {
soc/intel/skylake: Use Broadwell as comparision base for Skylake SOC Use the Broadwell implementation as the comparison base for Skylake. BRANCH=none BUG=None TEST=None Change-Id: I22eb55ea89eb0d6883f98e4c72a6d243e819e6d8 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10340 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-13 03:19:47 +02:00
C_STATE_C1E,
C_STATE_C7S_LONG_LAT,
C_STATE_C10
};
soc/intel: Add Skylake SOC support Add the files to support the Skylake SOC. Matches chromium tree at 927026db BRANCH=none BUG=None TEST=Build and run on a Skylake platform Change-Id: I80248f7e47eaf13b52e3c7ff951eb1976edbaa15 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10341 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-05-13 03:23:27 +02:00
static int cstate_set_non_s0ix[] = {
soc/intel/skylake: Use Broadwell as comparision base for Skylake SOC Use the Broadwell implementation as the comparison base for Skylake. BRANCH=none BUG=None TEST=None Change-Id: I22eb55ea89eb0d6883f98e4c72a6d243e819e6d8 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10340 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-13 03:19:47 +02:00
C_STATE_C1E,
C_STATE_C3,
soc/intel: Add Skylake SOC support Add the files to support the Skylake SOC. Matches chromium tree at 927026db BRANCH=none BUG=None TEST=Build and run on a Skylake platform Change-Id: I80248f7e47eaf13b52e3c7ff951eb1976edbaa15 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10341 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-05-13 03:23:27 +02:00
C_STATE_C7S_LONG_LAT,
soc/intel/skylake: Use Broadwell as comparision base for Skylake SOC Use the Broadwell implementation as the comparison base for Skylake. BRANCH=none BUG=None TEST=None Change-Id: I22eb55ea89eb0d6883f98e4c72a6d243e819e6d8 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10340 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-13 03:19:47 +02:00
};
static int get_cores_per_package(void)
{
struct cpuinfo_x86 c;
struct cpuid_result result;
int cores = 1;
get_fms(&c, cpuid_eax(1));
if (c.x86 != 6)
return 1;
result = cpuid_ext(0xb, 1);
cores = result.ebx & 0xff;
return cores;
}
soc/intel: Rename to soc_fill_gnvs() Replace acpi_create_gnvs() under soc/ to reflect their changed funcionality. Change-Id: I7bdbe0d6f795252e713e9785ada2b6320e6604b9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48717 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-28 21:39:59 +02:00
void soc_fill_gnvs(struct global_nvs *gnvs)
soc/intel/skylake: Use Broadwell as comparision base for Skylake SOC Use the Broadwell implementation as the comparison base for Skylake. BRANCH=none BUG=None TEST=None Change-Id: I22eb55ea89eb0d6883f98e4c72a6d243e819e6d8 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10340 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-13 03:19:47 +02:00
{
soc/intel: Replace config_of_path() with config_of_soc() The previously provided device path made no difference, all integrated PCI devices point back to the same chip_info structure. Change reduces the exposure of various SA_DEVFN_xx and PCH_DEVFN_xx from (ugly) soc/pci_devs.h. Change-Id: Ibf13645fdd3ef7fd3d5c8217bb24d7ede045c790 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35656 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-09-27 23:20:27 +02:00
const struct soc_intel_skylake_config *config = config_of_soc();
skylake: Enable DPTF based on devicetree setting Enable DPTF flag in ACPI NVS based on devicetree setting for the mainboard. BUG=chrome-os-partner:40635 BRANCH=none TEST=emerge-glaods coreboot Change-Id: I06ec6b050eb83c6a7ee1e48f2bd9f5920f7bfa51 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 5728a8a37b1a50a483aa211563fb7ad312002ce5 Original-Change-Id: I08d61416c24b3c8857205cf88931f0bb2b38896c Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/297755 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11565 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-04 22:53:14 +02:00
soc/intel/skylake: Use Broadwell as comparision base for Skylake SOC Use the Broadwell implementation as the comparison base for Skylake. BRANCH=none BUG=None TEST=None Change-Id: I22eb55ea89eb0d6883f98e4c72a6d243e819e6d8 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10340 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-13 03:19:47 +02:00
/* Set unknown wake source */
gnvs->pm1i = -1;
skylake: Enable DPTF based on devicetree setting Enable DPTF flag in ACPI NVS based on devicetree setting for the mainboard. BUG=chrome-os-partner:40635 BRANCH=none TEST=emerge-glaods coreboot Change-Id: I06ec6b050eb83c6a7ee1e48f2bd9f5920f7bfa51 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 5728a8a37b1a50a483aa211563fb7ad312002ce5 Original-Change-Id: I08d61416c24b3c8857205cf88931f0bb2b38896c Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/297755 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11565 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-04 22:53:14 +02:00
/* Enable DPTF based on mainboard configuration */
gnvs->dpte = config->dptf_enable;
skylake: Add and fill out CID1 NVS field Add a country identifier field to NVS and populate it with the call to wifi_regulatory_domain() which will (by default) do a lookup for the 'region' identifier in VPD on a Chrome OS device. BUG=chrome-os-partner:50516 BRANCH=glados TEST=build and boot on chell Change-Id: Ie7531848e620095732772c22156a85b7f8a6df5c Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: dafdb3760a0302e3effdc0e83977c1bfd5c9d3b2 Original-Change-Id: Ic83ab008045a469d0e0756f7e4d42f1b3894c529 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/329295 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13839 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-25 17:45:43 +01:00
/* Fill in the Wifi Region id */
gnvs->cid1 = wifi_regulatory_domain();
intel/skylake: Add support to enable wake-on-usb attach/detach Three things are required to enable wake-on-usb: 1. 5V to USB ports should be enabled in S3. 2. ASL file needs to have appropriate wake bit set. 3. XHCI controller should have the wake on attach/detach bit set for the corresponding port in PORTSCN register. Only part missing was #3. This CL adds support to allow mainboard to define a bitmap in devicetree corresponding to the ports that it wants to enable wake-on-usb feature. Based on the bitmap, wake on attach/detach bits in PORTSCN would be set by xhci.asl for the appropriate ports. BUG=chrome-os-partner:58734 BRANCH=None TEST=Verified that with port 5 enabled, chell wakes up from S3 on usb attach/detach. Change-Id: I40a22a450e52f74a0ab93ebb8170555d834ebdaf Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17056 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-10-18 23:25:25 +02:00
/* Set USB2/USB3 wake enable bitmaps. */
gnvs->u2we = config->usb2_wake_enable_bitmap;
gnvs->u3we = config->usb3_wake_enable_bitmap;
soc/intel/skylake: update GNVS with SGX data - Call sgx_fill_gnvs to update GNVS data, if CONFIG_SOC_INTEL_COMMON_BLOCK_SGX is set. - With this patch SGX ACPI device would get pached with enumaretd values of ECP device status, base address and length Change-Id: Ief0531fbab34838a3f8adb9cdc7d3fe19203c432 Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/21972 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-12 01:12:21 +02:00
soc/intel/sgx: convert SGX and PRMRR devicetree options to Kconfig The devicetree is not made for user-choosable options, thus introduce Kconfig options for both SGX and the corresponding PRMRR size. The PRMRR size Kconfig has been implemented as a maximum value. At runtime the final PRMRR size gets selected by checking the supported values in MSR_PRMRR_VALID_CONFIG and trying to select the value nearest to the chosen one. When "Maximum" is chosen, the highest possibly value from the MSR gets used. When a too strict limit is set, coreboot will die, printing an error message. Tested successfully on X11SSM-F Change-Id: I5f08e85898304bba6680075ca5d6bce26aef9a4d Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35799 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-10-22 23:05:06 +02:00
if (CONFIG(SOC_INTEL_COMMON_BLOCK_SGX_ENABLE))
soc/intel/skylake: update GNVS with SGX data - Call sgx_fill_gnvs to update GNVS data, if CONFIG_SOC_INTEL_COMMON_BLOCK_SGX is set. - With this patch SGX ACPI device would get pached with enumaretd values of ECP device status, base address and length Change-Id: Ief0531fbab34838a3f8adb9cdc7d3fe19203c432 Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/21972 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-12 01:12:21 +02:00
sgx_fill_gnvs(gnvs);
soc/intel/{apl,cnl,icl,skl,tgl}: Make above 4GB MMIO resource proper This patch ensures coreboot is not publishing above 4GB mmio resource if soc common config "enable_above_4GB_mmio" not enable. Publishing unnecessary 4GB above MMIO resource with wrong base and size is causing problem while working with discrete GPU. Unable to boot with dGPU on IA platform with below error: [ 2.297425] pcieport 0000:00:1c.0: PCI bridge to [bus 05] [ 2.302858] pcieport 0000:00:1c.0: bridge window [io 0x2000-0x2fff] [ 2.309427] pcieport 0000:00:1c.0: bridge window [mem 0xb2000000-0xb20fffff] [ 2.316679] pcieport 0000:00:1c.0: bridge window [mem 0x840000000-0x8c01fffff 64bit pref] [ 2.325072] pcieport 0000:00:1c.0: PCI bridge to [bus 05] [ 2.330502] pcieport 0000:00:1c.0: bridge window [io 0x2000-0x2fff] [ 2.337062] pcieport 0000:00:1c.0: bridge window [mem 0xb2000000-0xb20fffff] [ 2.344317] pcieport 0000:00:1c.0: bridge window [mem 0xa0000000-0xb01fffff 64bit pref] [ 2.352541] [drm] Not enough PCI address space for a large BAR. Change-Id: I77b3a0e44582b047d7fbe679d3000d616f7e6111 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38125 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
2020-01-03 10:59:02 +01:00
/* Fill in Above 4GB MMIO resource */
sa_fill_gnvs(gnvs);
soc/intel/skylake: Use Broadwell as comparision base for Skylake SOC Use the Broadwell implementation as the comparison base for Skylake. BRANCH=none BUG=None TEST=None Change-Id: I22eb55ea89eb0d6883f98e4c72a6d243e819e6d8 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10340 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-13 03:19:47 +02:00
}
unsigned long acpi_fill_mcfg(unsigned long current)
{
current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current,
soc/intel/skylake: Remove MCFG constants The MMCONF base address and length are set in Kconfig so it does not need to be redefined by the SOC as the code can just use the Kconfig variable directly. Tested on a fizz board to ensure MCFG is still created properly. Change-Id: I5fd472b1afc8264823a2b9db0f296fbfb6b1ecc0 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/24975 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-02 23:56:38 +01:00
CONFIG_MMCONF_BASE_ADDRESS, 0, 0,
soc/intel: Fix MCFG end bus number The ACPI MCFG table is generated with a static end bus number of 255, which expects that the reserved range in E820 is 256MB. However the actual MCFG range is configurable with Kconfig, so these two values may not match when the OS tries to determine the range: PCI: MMCONFIG for domain 0000 [bus 00-ff] at [mem 0xe0000000-0xefffffff] (base 0xe0000000) PCI: MMCONFIG 0000 [bus 00-3f] at [mem 0xe0000000-0xe3ffffff] (base 0xe0000000) (size reduced!) acpi PNP0A08:00: [Firmware Info]: MMCONFIG for domain 0000 [bus 00-3f] only partially covers this bridge Instead of forcing the end bus number to be 255 use the Kconfig value to set it based on the current configuration. Tested on a fizz device to ensure that the kernel no longer complains: PCI: MMCONFIG for domain 0000 [bus 00-3f] at [mem 0xe0000000-0xe3ffffff] (base 0xe0000000) Change-Id: I999ea9b72b9deba5f27dd692faa0408427a0bf89 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/24974 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-02 23:47:11 +01:00
(CONFIG_SA_PCIEX_LENGTH >> 20) - 1);
soc/intel/skylake: Use Broadwell as comparision base for Skylake SOC Use the Broadwell implementation as the comparison base for Skylake. BRANCH=none BUG=None TEST=None Change-Id: I22eb55ea89eb0d6883f98e4c72a6d243e819e6d8 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10340 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-13 03:19:47 +02:00
return current;
}
skylake: Move ACPI init to SOC instead of mainboard Move some remaining ACPI init code to the SOC instead of being done in each mainboard: - acpi_create_gnvs is now a local function - add a weak acpi_mainboard_gnvs() that can be used for mainboards to override or set additional NVS - add acpi_fill_madt() function for skylake - remove acpi_create_serialio_ssdt() function as it is unused BUG=chrome-os-partner:40635 BRANCH=none TEST=emerge-glados coreboot Change-Id: I52225e8d38ed846c29d44872e3f4d6ebaf4a7e52 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: c717bb418a0cb6002582572632e42b44b473f718 Original-Change-Id: I0910ac8ef25de265ae1fde16b68f6cbacedb4462 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/297800 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11581 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-04 23:19:35 +02:00
unsigned long acpi_fill_madt(unsigned long current)
{
/* Local APICs */
current = acpi_create_madt_lapics(current);
/* IOAPIC */
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
2, IO_APIC_ADDR, 0);
return acpi_madt_irq_overrides(current);
}
src: Remove variable length arrays Variable length arrays were a feature added in C99 that allows the length of an array to be determined at runtime. Eg. int sum(size_t n) { int arr[n]; ... } This adds a small amount of runtime overhead, but is also very dangerous, since it allows use of an unlimited amount of stack memory, potentially leading to stack overflow. This is only worsened in coreboot, which often has very little stack space to begin with. Citing concerns like this, all instances of VLA's were recently removed from the Linux kernel. In the immortal words of Linus Torvalds [0], AND USING VLA'S IS ACTIVELY STUPID! It generates much more code, and much _slower_ code (and more fragile code), than just using a fixed key size would have done. [...] Anyway, some of these are definitely easy to just fix, and using VLA's is actively bad not just for security worries, but simply because VLA's are a really horribly bad idea in general in the kernel. This patch follows suit and zaps all VLA's in coreboot. Some of the existing VLA's are accidental ones, and all but one can be replaced with small fixed-size buffers. The single tricky exception is in the SPI controller interface, which will require a rewrite of old drivers to remove [1]. [0] https://lkml.org/lkml/2018/3/7/621 [1] https://ticket.coreboot.org/issues/217 Change-Id: I7d9d1ddadbf1cee5f695165bbe3f0effb7bd32b9 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33821 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-06-27 00:18:16 +02:00
static void write_c_state_entries(acpi_cstate_t *map, const int *set, size_t max_c_state)
soc/intel/skylake: Use Broadwell as comparision base for Skylake SOC Use the Broadwell implementation as the comparison base for Skylake. BRANCH=none BUG=None TEST=None Change-Id: I22eb55ea89eb0d6883f98e4c72a6d243e819e6d8 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10340 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-13 03:19:47 +02:00
{
src: Remove variable length arrays Variable length arrays were a feature added in C99 that allows the length of an array to be determined at runtime. Eg. int sum(size_t n) { int arr[n]; ... } This adds a small amount of runtime overhead, but is also very dangerous, since it allows use of an unlimited amount of stack memory, potentially leading to stack overflow. This is only worsened in coreboot, which often has very little stack space to begin with. Citing concerns like this, all instances of VLA's were recently removed from the Linux kernel. In the immortal words of Linus Torvalds [0], AND USING VLA'S IS ACTIVELY STUPID! It generates much more code, and much _slower_ code (and more fragile code), than just using a fixed key size would have done. [...] Anyway, some of these are definitely easy to just fix, and using VLA's is actively bad not just for security worries, but simply because VLA's are a really horribly bad idea in general in the kernel. This patch follows suit and zaps all VLA's in coreboot. Some of the existing VLA's are accidental ones, and all but one can be replaced with small fixed-size buffers. The single tricky exception is in the SPI controller interface, which will require a rewrite of old drivers to remove [1]. [0] https://lkml.org/lkml/2018/3/7/621 [1] https://ticket.coreboot.org/issues/217 Change-Id: I7d9d1ddadbf1cee5f695165bbe3f0effb7bd32b9 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33821 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-06-27 00:18:16 +02:00
for (size_t i = 0; i < max_c_state; i++) {
soc/intel/skylake: Use Broadwell as comparision base for Skylake SOC Use the Broadwell implementation as the comparison base for Skylake. BRANCH=none BUG=None TEST=None Change-Id: I22eb55ea89eb0d6883f98e4c72a6d243e819e6d8 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10340 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-13 03:19:47 +02:00
memcpy(&map[i], &cstate_map[set[i]], sizeof(acpi_cstate_t));
map[i].ctype = i + 1;
}
/* Generate C-state tables */
src: Remove variable length arrays Variable length arrays were a feature added in C99 that allows the length of an array to be determined at runtime. Eg. int sum(size_t n) { int arr[n]; ... } This adds a small amount of runtime overhead, but is also very dangerous, since it allows use of an unlimited amount of stack memory, potentially leading to stack overflow. This is only worsened in coreboot, which often has very little stack space to begin with. Citing concerns like this, all instances of VLA's were recently removed from the Linux kernel. In the immortal words of Linus Torvalds [0], AND USING VLA'S IS ACTIVELY STUPID! It generates much more code, and much _slower_ code (and more fragile code), than just using a fixed key size would have done. [...] Anyway, some of these are definitely easy to just fix, and using VLA's is actively bad not just for security worries, but simply because VLA's are a really horribly bad idea in general in the kernel. This patch follows suit and zaps all VLA's in coreboot. Some of the existing VLA's are accidental ones, and all but one can be replaced with small fixed-size buffers. The single tricky exception is in the SPI controller interface, which will require a rewrite of old drivers to remove [1]. [0] https://lkml.org/lkml/2018/3/7/621 [1] https://ticket.coreboot.org/issues/217 Change-Id: I7d9d1ddadbf1cee5f695165bbe3f0effb7bd32b9 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33821 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-06-27 00:18:16 +02:00
acpigen_write_CST_package(map, max_c_state);
}
static void generate_c_state_entries(int s0ix_enable)
{
if (s0ix_enable) {
acpi_cstate_t map[ARRAY_SIZE(cstate_set_s0ix)];
write_c_state_entries(map, cstate_set_s0ix, ARRAY_SIZE(map));
} else {
acpi_cstate_t map[ARRAY_SIZE(cstate_set_non_s0ix)];
write_c_state_entries(map, cstate_set_non_s0ix, ARRAY_SIZE(map));
}
soc/intel/skylake: Use Broadwell as comparision base for Skylake SOC Use the Broadwell implementation as the comparison base for Skylake. BRANCH=none BUG=None TEST=None Change-Id: I22eb55ea89eb0d6883f98e4c72a6d243e819e6d8 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10340 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-13 03:19:47 +02:00
}
static int calculate_power(int tdp, int p1_ratio, int ratio)
{
u32 m;
u32 power;
/*
* M = ((1.1 - ((p1_ratio - ratio) * 0.00625)) / 1.1) ^ 2
*
* Power = (ratio / p1_ratio) * m * tdp
*/
m = (110000 - ((p1_ratio - ratio) * 625)) / 11;
m = (m * m) / 1000;
power = ((ratio * 100000 / p1_ratio) / 100);
power *= (m / 100) * (tdp / 1000);
power /= 1000;
return (int)power;
}
soc/intel: Add Skylake SOC support Add the files to support the Skylake SOC. Matches chromium tree at 927026db BRANCH=none BUG=None TEST=Build and run on a Skylake platform Change-Id: I80248f7e47eaf13b52e3c7ff951eb1976edbaa15 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10341 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-05-13 03:23:27 +02:00
static void generate_p_state_entries(int core, int cores_per_package)
soc/intel/skylake: Use Broadwell as comparision base for Skylake SOC Use the Broadwell implementation as the comparison base for Skylake. BRANCH=none BUG=None TEST=None Change-Id: I22eb55ea89eb0d6883f98e4c72a6d243e819e6d8 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10340 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-13 03:19:47 +02:00
{
int ratio_min, ratio_max, ratio_turbo, ratio_step;
int coord_type, power_max, power_unit, num_entries;
int ratio, power, clock, clock_max;
msr_t msr;
/* Determine P-state coordination type from MISC_PWR_MGMT[0] */
msr = rdmsr(MSR_MISC_PWR_MGMT);
if (msr.lo & MISC_PWR_MGMT_EIST_HW_DIS)
coord_type = SW_ANY;
else
coord_type = HW_ALL;
/* Get bus ratio limits and calculate clock speeds */
msr = rdmsr(MSR_PLATFORM_INFO);
ratio_min = (msr.hi >> (40-32)) & 0xff; /* Max Efficiency Ratio */
/* Determine if this CPU has configurable TDP */
if (cpu_config_tdp_levels()) {
/* Set max ratio to nominal TDP ratio */
msr = rdmsr(MSR_CONFIG_TDP_NOMINAL);
ratio_max = msr.lo & 0xff;
} else {
/* Max Non-Turbo Ratio */
ratio_max = (msr.lo >> 8) & 0xff;
}
soc/intel/skylake: Add config for cpu base clock frequency Add config for cpu base clock frequency(Mhz) and replace current refrence from soc/cpu.h with config option. Change-Id: Idf8e85f7ae6d965fa987a4f5c4905503ee354d69 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/20016 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-06-02 08:26:14 +02:00
clock_max = ratio_max * CONFIG_CPU_BCLK_MHZ;
soc/intel/skylake: Use Broadwell as comparision base for Skylake SOC Use the Broadwell implementation as the comparison base for Skylake. BRANCH=none BUG=None TEST=None Change-Id: I22eb55ea89eb0d6883f98e4c72a6d243e819e6d8 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10340 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-13 03:19:47 +02:00
/* Calculate CPU TDP in mW */
msr = rdmsr(MSR_PKG_POWER_SKU_UNIT);
power_unit = 2 << ((msr.lo & 0xf) - 1);
msr = rdmsr(MSR_PKG_POWER_SKU);
power_max = ((msr.lo & 0x7fff) / power_unit) * 1000;
/* Write _PCT indicating use of FFixedHW */
acpigen_write_empty_PCT();
/* Write _PPC with no limit on supported P-state */
acpigen_write_PPC_NVS();
/* Write PSD indicating configured coordination type */
acpigen_write_PSD_package(core, 1, coord_type);
/* Add P-state entries in _PSS table */
acpigen_write_name("_PSS");
/* Determine ratio points */
ratio_step = PSS_RATIO_STEP;
soc/intel: Add Skylake SOC support Add the files to support the Skylake SOC. Matches chromium tree at 927026db BRANCH=none BUG=None TEST=Build and run on a Skylake platform Change-Id: I80248f7e47eaf13b52e3c7ff951eb1976edbaa15 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10341 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-05-13 03:23:27 +02:00
num_entries = ((ratio_max - ratio_min) / ratio_step) + 1;
if (num_entries > PSS_MAX_ENTRIES) {
ratio_step += 1;
num_entries = ((ratio_max - ratio_min) / ratio_step) + 1;
soc/intel/skylake: Use Broadwell as comparision base for Skylake SOC Use the Broadwell implementation as the comparison base for Skylake. BRANCH=none BUG=None TEST=None Change-Id: I22eb55ea89eb0d6883f98e4c72a6d243e819e6d8 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10340 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-13 03:19:47 +02:00
}
/* P[T] is Turbo state if enabled */
if (get_turbo_state() == TURBO_ENABLED) {
/* _PSS package count including Turbo */
acpigen_write_package(num_entries + 2);
msr = rdmsr(MSR_TURBO_RATIO_LIMIT);
ratio_turbo = msr.lo & 0xff;
/* Add entry for Turbo ratio */
acpigen_write_PSS_package(
soc/intel: Add Skylake SOC support Add the files to support the Skylake SOC. Matches chromium tree at 927026db BRANCH=none BUG=None TEST=Build and run on a Skylake platform Change-Id: I80248f7e47eaf13b52e3c7ff951eb1976edbaa15 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10341 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-05-13 03:23:27 +02:00
clock_max + 1, /* MHz */
power_max, /* mW */
PSS_LATENCY_TRANSITION, /* lat1 */
PSS_LATENCY_BUSMASTER, /* lat2 */
ratio_turbo << 8, /* control */
ratio_turbo << 8); /* status */
soc/intel/skylake: Use Broadwell as comparision base for Skylake SOC Use the Broadwell implementation as the comparison base for Skylake. BRANCH=none BUG=None TEST=None Change-Id: I22eb55ea89eb0d6883f98e4c72a6d243e819e6d8 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10340 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-13 03:19:47 +02:00
} else {
/* _PSS package count without Turbo */
acpigen_write_package(num_entries + 1);
}
/* First regular entry is max non-turbo ratio */
acpigen_write_PSS_package(
soc/intel: Add Skylake SOC support Add the files to support the Skylake SOC. Matches chromium tree at 927026db BRANCH=none BUG=None TEST=Build and run on a Skylake platform Change-Id: I80248f7e47eaf13b52e3c7ff951eb1976edbaa15 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10341 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-05-13 03:23:27 +02:00
clock_max, /* MHz */
power_max, /* mW */
PSS_LATENCY_TRANSITION, /* lat1 */
PSS_LATENCY_BUSMASTER, /* lat2 */
ratio_max << 8, /* control */
ratio_max << 8); /* status */
soc/intel/skylake: Use Broadwell as comparision base for Skylake SOC Use the Broadwell implementation as the comparison base for Skylake. BRANCH=none BUG=None TEST=None Change-Id: I22eb55ea89eb0d6883f98e4c72a6d243e819e6d8 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10340 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-13 03:19:47 +02:00
/* Generate the remaining entries */
for (ratio = ratio_min + ((num_entries - 1) * ratio_step);
ratio >= ratio_min; ratio -= ratio_step) {
/* Calculate power at this ratio */
power = calculate_power(power_max, ratio_max, ratio);
soc/intel/skylake: Add config for cpu base clock frequency Add config for cpu base clock frequency(Mhz) and replace current refrence from soc/cpu.h with config option. Change-Id: Idf8e85f7ae6d965fa987a4f5c4905503ee354d69 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/20016 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-06-02 08:26:14 +02:00
clock = ratio * CONFIG_CPU_BCLK_MHZ;
soc/intel/skylake: Use Broadwell as comparision base for Skylake SOC Use the Broadwell implementation as the comparison base for Skylake. BRANCH=none BUG=None TEST=None Change-Id: I22eb55ea89eb0d6883f98e4c72a6d243e819e6d8 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10340 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-13 03:19:47 +02:00
acpigen_write_PSS_package(
soc/intel: Add Skylake SOC support Add the files to support the Skylake SOC. Matches chromium tree at 927026db BRANCH=none BUG=None TEST=Build and run on a Skylake platform Change-Id: I80248f7e47eaf13b52e3c7ff951eb1976edbaa15 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10341 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-05-13 03:23:27 +02:00
clock, /* MHz */
power, /* mW */
PSS_LATENCY_TRANSITION, /* lat1 */
PSS_LATENCY_BUSMASTER, /* lat2 */
ratio << 8, /* control */
ratio << 8); /* status */
soc/intel/skylake: Use Broadwell as comparision base for Skylake SOC Use the Broadwell implementation as the comparison base for Skylake. BRANCH=none BUG=None TEST=None Change-Id: I22eb55ea89eb0d6883f98e4c72a6d243e819e6d8 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10340 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-13 03:19:47 +02:00
}
/* Fix package length */
acpigen_pop_len();
}
soc/intel/skl,acpi/acpigen: convert global CPPC package to local one Move the global CPPC package \GCPC to the first logical core CP00 and adapt the reference in the other cores. This is cleaner and avoids confusion. Test: dumped SSDT on Supermicro X11SSM-F and verified decompiled version Change-Id: I40b9fd644622196da434128895eb6fb96fdf254d Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46465 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-10-14 19:30:46 +02:00
static void generate_cppc_entries(int core_id)
{
/* Generate GCPC table in first logical core */
if (core_id == 0) {
struct cppc_config cppc_config;
cpu_init_cppc_config(&cppc_config, CPPC_VERSION_2);
acpigen_write_CPPC_package(&cppc_config);
}
/* Write _CST entry for each logical core */
acpigen_write_CPPC_method();
}
device: Constify struct device * parameter to acpi_fill_ssdt() .acpi_fill_ssdt() does not need to modify the device structure. This change makes the struct device * parameter to acpi_fill_ssdt() as const. Change-Id: I110f4c67c3b6671c9ac0a82e02609902a8ee5d5c Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40710 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-25 06:59:21 +02:00
void generate_cpu_entries(const struct device *device)
soc/intel/skylake: Use Broadwell as comparision base for Skylake SOC Use the Broadwell implementation as the comparison base for Skylake. BRANCH=none BUG=None TEST=None Change-Id: I22eb55ea89eb0d6883f98e4c72a6d243e819e6d8 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10340 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-13 03:19:47 +02:00
{
soc/intel: Add Skylake SOC support Add the files to support the Skylake SOC. Matches chromium tree at 927026db BRANCH=none BUG=None TEST=Build and run on a Skylake platform Change-Id: I80248f7e47eaf13b52e3c7ff951eb1976edbaa15 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10341 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-05-13 03:23:27 +02:00
int core_id, cpu_id, pcontrol_blk = ACPI_BASE_ADDRESS, plen = 6;
soc/intel/skylake: Use Broadwell as comparision base for Skylake SOC Use the Broadwell implementation as the comparison base for Skylake. BRANCH=none BUG=None TEST=None Change-Id: I22eb55ea89eb0d6883f98e4c72a6d243e819e6d8 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10340 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-13 03:19:47 +02:00
int totalcores = dev_count_cpu();
int cores_per_package = get_cores_per_package();
int numcpus = totalcores/cores_per_package;
soc/intel: Replace config_of_path() with config_of_soc() The previously provided device path made no difference, all integrated PCI devices point back to the same chip_info structure. Change reduces the exposure of various SA_DEVFN_xx and PCH_DEVFN_xx from (ugly) soc/pci_devs.h. Change-Id: Ibf13645fdd3ef7fd3d5c8217bb24d7ede045c790 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35656 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-09-27 23:20:27 +02:00
config_t *config = config_of_soc();
soc/intel: Add Skylake SOC support Add the files to support the Skylake SOC. Matches chromium tree at 927026db BRANCH=none BUG=None TEST=Build and run on a Skylake platform Change-Id: I80248f7e47eaf13b52e3c7ff951eb1976edbaa15 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10341 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-05-13 03:23:27 +02:00
int is_s0ix_enable = config->s0ix_enable;
soc/intel/skl,acpi/acpigen: convert global CPPC package to local one Move the global CPPC package \GCPC to the first logical core CP00 and adapt the reference in the other cores. This is cleaner and avoids confusion. Test: dumped SSDT on Supermicro X11SSM-F and verified decompiled version Change-Id: I40b9fd644622196da434128895eb6fb96fdf254d Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46465 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-10-14 19:30:46 +02:00
const bool isst_supported = cpuid_eax(6) & CPUID_6_EAX_ISST;
soc/intel/skylake: Use Broadwell as comparision base for Skylake SOC Use the Broadwell implementation as the comparison base for Skylake. BRANCH=none BUG=None TEST=None Change-Id: I22eb55ea89eb0d6883f98e4c72a6d243e819e6d8 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10340 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-13 03:19:47 +02:00
printk(BIOS_DEBUG, "Found %d CPU(s) with %d core(s) each.\n",
numcpus, cores_per_package);
soc/intel: Add Skylake SOC support Add the files to support the Skylake SOC. Matches chromium tree at 927026db BRANCH=none BUG=None TEST=Build and run on a Skylake platform Change-Id: I80248f7e47eaf13b52e3c7ff951eb1976edbaa15 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10341 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-05-13 03:23:27 +02:00
for (cpu_id = 0; cpu_id < numcpus; cpu_id++) {
for (core_id = 0; core_id < cores_per_package; core_id++) {
if (core_id > 0) {
soc/intel/skylake: Use Broadwell as comparision base for Skylake SOC Use the Broadwell implementation as the comparison base for Skylake. BRANCH=none BUG=None TEST=None Change-Id: I22eb55ea89eb0d6883f98e4c72a6d243e819e6d8 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10340 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-13 03:19:47 +02:00
pcontrol_blk = 0;
plen = 0;
}
acpi: Change Processor ACPI Name (Intel only) The ACPI Spec 2.0 states, that Processor declarations should be made within the ACPI namespace \_SB and not \_PR anymore. \_PR is deprecated and is removed here for Intel CPUs only. Tested on: * X11SSH (Kabylake) * CFL Platform * Asus P8Z77-V LX2 and Windows 10 FWTS does not return FAIL anymore on ACPI tests Tested-by: Angel Pons <th3fanbus@gmail.com> Change-Id: Ib101ed718f90f9056d2ecbc31b13b749ed1fc438 Signed-off-by: Christian Walter <christian.walter@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37814 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-12-18 15:07:59 +01:00
/* Generate processor \_SB.CPUx */
soc/intel/skylake: Use Broadwell as comparision base for Skylake SOC Use the Broadwell implementation as the comparison base for Skylake. BRANCH=none BUG=None TEST=None Change-Id: I22eb55ea89eb0d6883f98e4c72a6d243e819e6d8 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10340 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-13 03:19:47 +02:00
acpigen_write_processor(
soc/intel: Add Skylake SOC support Add the files to support the Skylake SOC. Matches chromium tree at 927026db BRANCH=none BUG=None TEST=Build and run on a Skylake platform Change-Id: I80248f7e47eaf13b52e3c7ff951eb1976edbaa15 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10341 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-05-13 03:23:27 +02:00
cpu_id*cores_per_package+core_id,
soc/intel/skylake: Use Broadwell as comparision base for Skylake SOC Use the Broadwell implementation as the comparison base for Skylake. BRANCH=none BUG=None TEST=None Change-Id: I22eb55ea89eb0d6883f98e4c72a6d243e819e6d8 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10340 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-13 03:19:47 +02:00
pcontrol_blk, plen);
/* Generate C-state tables */
src: Remove variable length arrays Variable length arrays were a feature added in C99 that allows the length of an array to be determined at runtime. Eg. int sum(size_t n) { int arr[n]; ... } This adds a small amount of runtime overhead, but is also very dangerous, since it allows use of an unlimited amount of stack memory, potentially leading to stack overflow. This is only worsened in coreboot, which often has very little stack space to begin with. Citing concerns like this, all instances of VLA's were recently removed from the Linux kernel. In the immortal words of Linus Torvalds [0], AND USING VLA'S IS ACTIVELY STUPID! It generates much more code, and much _slower_ code (and more fragile code), than just using a fixed key size would have done. [...] Anyway, some of these are definitely easy to just fix, and using VLA's is actively bad not just for security worries, but simply because VLA's are a really horribly bad idea in general in the kernel. This patch follows suit and zaps all VLA's in coreboot. Some of the existing VLA's are accidental ones, and all but one can be replaced with small fixed-size buffers. The single tricky exception is in the SPI controller interface, which will require a rewrite of old drivers to remove [1]. [0] https://lkml.org/lkml/2018/3/7/621 [1] https://ticket.coreboot.org/issues/217 Change-Id: I7d9d1ddadbf1cee5f695165bbe3f0effb7bd32b9 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33821 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-06-27 00:18:16 +02:00
generate_c_state_entries(is_s0ix_enable);
soc/intel/skylake: Use Broadwell as comparision base for Skylake SOC Use the Broadwell implementation as the comparison base for Skylake. BRANCH=none BUG=None TEST=None Change-Id: I22eb55ea89eb0d6883f98e4c72a6d243e819e6d8 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10340 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-13 03:19:47 +02:00
soc/intel/skylake: add CPPC support ACPI 5.0 defines a method _CPC for "Continuous Performance Control" (CPPC). Linux has a driver that enables features like speed shift without consulting ACPI. Other OSes instead rely on this information and need a _CPC present. Prior to this change performance in Win10 never exceeds 80% and MSR 0x770 is 0, while with this change (and enabling eist) higher speeds can be achieved and the MSR value is now 1. Change-Id: Ib7e0ae13f4b664b51e42f963e53c71f8832be062 Signed-off-by: Matt Delco <delco@chromium.org> Reviewed-on: https://review.coreboot.org/27673 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2018-07-27 23:17:29 +02:00
if (config->eist_enable) {
soc/intel/skylake: Add option to enable/disable EIST Set MSR 0x1A0 bit[16] based on EIST config option. Default Hardware Managed P-state (HWP) also known as Intel Speed Shift is enabled on SKL hence disable EIST and ACPI P-state table. Change-Id: I2b7374a8a04b596edcc88165b64980b7aa09e2a7 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/19676 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-05-12 08:13:57 +02:00
/* Generate P-state tables */
generate_p_state_entries(core_id,
cores_per_package);
soc/intel/skylake: add CPPC support ACPI 5.0 defines a method _CPC for "Continuous Performance Control" (CPPC). Linux has a driver that enables features like speed shift without consulting ACPI. Other OSes instead rely on this information and need a _CPC present. Prior to this change performance in Win10 never exceeds 80% and MSR 0x770 is 0, while with this change (and enabling eist) higher speeds can be achieved and the MSR value is now 1. Change-Id: Ib7e0ae13f4b664b51e42f963e53c71f8832be062 Signed-off-by: Matt Delco <delco@chromium.org> Reviewed-on: https://review.coreboot.org/27673 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2018-07-27 23:17:29 +02:00
}
soc/intel/skylake: acpi: drop HWP's dependency on EIST Enhanced Intel SpeedStep Technology (EIST) and Intel Speed Shift Technology (ISST) - also know as HWP - are two independent mechanisms for controlling voltage and frequency based on performance hints. When HWP is enabled, it overrides the software-based EIST. It does not depend on EIST, though, but can be enabled on its own. Break up that currently existing dependency in ACPI generation code. It was tested that HWP can be enabled and gets used by the Linux pstate cpufreq driver. With HWP disabled, the frequency does not decrease, even not in powersave mode. After enabling HWP the frequency changed in relation to the current workload. (Test device: Acer ES1-572) Change-Id: I93d888ddce7b54e91b54e5b4fdd4d9cf16630eda Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44137 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-03 15:01:18 +02:00
soc/intel/skl,acpi/acpigen: convert global CPPC package to local one Move the global CPPC package \GCPC to the first logical core CP00 and adapt the reference in the other cores. This is cleaner and avoids confusion. Test: dumped SSDT on Supermicro X11SSM-F and verified decompiled version Change-Id: I40b9fd644622196da434128895eb6fb96fdf254d Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46465 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-10-14 19:30:46 +02:00
if (isst_supported)
generate_cppc_entries(core_id);
soc/intel/skylake: acpi: drop HWP's dependency on EIST Enhanced Intel SpeedStep Technology (EIST) and Intel Speed Shift Technology (ISST) - also know as HWP - are two independent mechanisms for controlling voltage and frequency based on performance hints. When HWP is enabled, it overrides the software-based EIST. It does not depend on EIST, though, but can be enabled on its own. Break up that currently existing dependency in ACPI generation code. It was tested that HWP can be enabled and gets used by the Linux pstate cpufreq driver. With HWP disabled, the frequency does not decrease, even not in powersave mode. After enabling HWP the frequency changed in relation to the current workload. (Test device: Acer ES1-572) Change-Id: I93d888ddce7b54e91b54e5b4fdd4d9cf16630eda Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44137 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-03 15:01:18 +02:00
soc/intel/skylake: Use Broadwell as comparision base for Skylake SOC Use the Broadwell implementation as the comparison base for Skylake. BRANCH=none BUG=None TEST=None Change-Id: I22eb55ea89eb0d6883f98e4c72a6d243e819e6d8 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10340 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-13 03:19:47 +02:00
acpigen_pop_len();
}
}
soc/intel/skylake: Rework acpi/cpu.asl Use acpigen_write_processor_cnot to implement notifications to the CPU. Change-Id: I182585fd09e4ce848c860d00eb612e8f5fdde35e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/29884 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-28 12:07:19 +01:00
/* PPKG is usually used for thermal management
of the first and only package. */
acpigen_write_processor_package("PPKG", 0, cores_per_package);
/* Add a method to notify processor nodes */
acpigen_write_processor_cnot(cores_per_package);
soc/intel/skylake: Use Broadwell as comparision base for Skylake SOC Use the Broadwell implementation as the comparison base for Skylake. BRANCH=none BUG=None TEST=None Change-Id: I22eb55ea89eb0d6883f98e4c72a6d243e819e6d8 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10340 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-13 03:19:47 +02:00
}
soc/intel/skylake: Generate ACPI DMAR table If the SoC is VT-d capable, write an ACPI DMAR table. The entry for the GFXVTBAR is only generated if the IGD is enabled. Change-Id: I8176401dd19aee7ad09a8a145b7a3801fe5b2ae1 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/21588 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Youness Alaoui <snifikino@gmail.com>
2017-09-18 20:03:46 +02:00
static unsigned long acpi_fill_dmar(unsigned long current)
{
soc/intel: Replace uses of dev_find_slot() To call dev_find_slot(0, xx) in romstage can produce invalid results since PCI bus enumeration has not been progressed yet. Replace this with method that relies on bus topology that walks the root bus only. Change-Id: I2883610059bb9fa860bba01179e7d5c58cae00e5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33996 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-07-03 06:25:59 +02:00
struct device *const igfx_dev = pcidev_path_on_root(SA_DEVFN_IGD);
soc/intel/skylake: Generate ACPI DMAR table If the SoC is VT-d capable, write an ACPI DMAR table. The entry for the GFXVTBAR is only generated if the IGD is enabled. Change-Id: I8176401dd19aee7ad09a8a145b7a3801fe5b2ae1 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/21588 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Youness Alaoui <snifikino@gmail.com>
2017-09-18 20:03:46 +02:00
const u32 gfx_vtbar = MCHBAR32(GFXVTBAR) & ~0xfff;
const bool gfxvten = MCHBAR32(GFXVTBAR) & 1;
/* iGFX has to be enabled, GFXVTBAR set and in 32-bit space. */
soc/intel/skylake: Add RMRRs after all DRHDs The VT-d architecture specification (Doc. D51397-011, Rev. 3.1) says: BIOS implementations must report these remapping structure types in numerical order. i.e., All remapping structures of type 0 (DRHD) enumerated before remapping structures of type 1 (RMRR), and so forth. So, update the corresponding code to adhere to the specification. Change-Id: I2446d536603559f637f3f8b1b44e9d712aa35492 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44112 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-08-03 12:29:41 +02:00
const bool emit_igd =
igfx_dev && igfx_dev->enabled &&
gfx_vtbar && gfxvten &&
!MCHBAR32(GFXVTBAR + 4);
/* First, add DRHD entries */
if (emit_igd) {
const unsigned long tmp = current;
soc/intel/skylake: Generate ACPI DMAR table If the SoC is VT-d capable, write an ACPI DMAR table. The entry for the GFXVTBAR is only generated if the IGD is enabled. Change-Id: I8176401dd19aee7ad09a8a145b7a3801fe5b2ae1 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/21588 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Youness Alaoui <snifikino@gmail.com>
2017-09-18 20:03:46 +02:00
current += acpi_create_dmar_drhd(current, 0, 0, gfx_vtbar);
arch/x86/acpi: Add DMAR RMRR helper functions Add DMAR RMRR table entry and helper functions, using the existing DRHD functions as a model. As the DRHD device scope (DS) functions aren't DRHD-specific, genericize them to be used with RMRR tables as well. Correct DRHD bar size to match table entry in creator function, as noted in comments from patchset below. Adapted from/supersedes https://review.coreboot.org/25445 Change-Id: I912b1d7244ca4dd911bb6629533d453b1b4a06be Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/27269 Reviewed-by: Youness Alaoui <snifikino@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-29 14:59:57 +02:00
current += acpi_create_dmar_ds_pci(current, 0, 2, 0);
soc/intel/skylake: Generate ACPI DMAR table If the SoC is VT-d capable, write an ACPI DMAR table. The entry for the GFXVTBAR is only generated if the IGD is enabled. Change-Id: I8176401dd19aee7ad09a8a145b7a3801fe5b2ae1 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/21588 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Youness Alaoui <snifikino@gmail.com>
2017-09-18 20:03:46 +02:00
acpi_dmar_drhd_fixup(tmp, current);
}
const u32 vtvc0bar = MCHBAR32(VTVC0BAR) & ~0xfff;
const bool vtvc0en = MCHBAR32(VTVC0BAR) & 1;
/* General VTBAR has to be set and in 32-bit space. */
soc/skylake: do not rely on P2SB data to generate DRHD The P2SB PCI device can be "hidden", which causes all sorts of nightmares and bugs. Moreover, FSP tends to hide it, so finding a good solution to this problem is impossible with FSP into the mix. Since the values for IBDF and HBDF were already hardcoded as FSP parameters, define them as macros and use these values directly to generate the DRHD. Change-Id: I7eb20182380b953a1842083e7a3c67919d6971b9 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35108 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mimoja <coreboot@mimoja.de> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-08-30 19:42:23 +02:00
if (vtvc0bar && vtvc0en && !MCHBAR32(VTVC0BAR + 4)) {
soc/intel/skylake: Generate ACPI DMAR table If the SoC is VT-d capable, write an ACPI DMAR table. The entry for the GFXVTBAR is only generated if the IGD is enabled. Change-Id: I8176401dd19aee7ad09a8a145b7a3801fe5b2ae1 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/21588 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Youness Alaoui <snifikino@gmail.com>
2017-09-18 20:03:46 +02:00
const unsigned long tmp = current;
soc/skylake: do not rely on P2SB data to generate DRHD The P2SB PCI device can be "hidden", which causes all sorts of nightmares and bugs. Moreover, FSP tends to hide it, so finding a good solution to this problem is impossible with FSP into the mix. Since the values for IBDF and HBDF were already hardcoded as FSP parameters, define them as macros and use these values directly to generate the DRHD. Change-Id: I7eb20182380b953a1842083e7a3c67919d6971b9 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35108 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mimoja <coreboot@mimoja.de> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-08-30 19:42:23 +02:00
current += acpi_create_dmar_drhd(current, DRHD_INCLUDE_PCI_ALL, 0, vtvc0bar);
soc/intel/skylake: Generate ACPI DMAR table If the SoC is VT-d capable, write an ACPI DMAR table. The entry for the GFXVTBAR is only generated if the IGD is enabled. Change-Id: I8176401dd19aee7ad09a8a145b7a3801fe5b2ae1 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/21588 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Youness Alaoui <snifikino@gmail.com>
2017-09-18 20:03:46 +02:00
soc/skylake: do not rely on P2SB data to generate DRHD The P2SB PCI device can be "hidden", which causes all sorts of nightmares and bugs. Moreover, FSP tends to hide it, so finding a good solution to this problem is impossible with FSP into the mix. Since the values for IBDF and HBDF were already hardcoded as FSP parameters, define them as macros and use these values directly to generate the DRHD. Change-Id: I7eb20182380b953a1842083e7a3c67919d6971b9 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35108 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mimoja <coreboot@mimoja.de> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-08-30 19:42:23 +02:00
current += acpi_create_dmar_ds_ioapic(current, 2, V_P2SB_IBDF_BUS,
V_P2SB_IBDF_DEV, V_P2SB_IBDF_FUN);
soc/intel/skylake: Generate ACPI DMAR table If the SoC is VT-d capable, write an ACPI DMAR table. The entry for the GFXVTBAR is only generated if the IGD is enabled. Change-Id: I8176401dd19aee7ad09a8a145b7a3801fe5b2ae1 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/21588 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Youness Alaoui <snifikino@gmail.com>
2017-09-18 20:03:46 +02:00
soc/skylake: do not rely on P2SB data to generate DRHD The P2SB PCI device can be "hidden", which causes all sorts of nightmares and bugs. Moreover, FSP tends to hide it, so finding a good solution to this problem is impossible with FSP into the mix. Since the values for IBDF and HBDF were already hardcoded as FSP parameters, define them as macros and use these values directly to generate the DRHD. Change-Id: I7eb20182380b953a1842083e7a3c67919d6971b9 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35108 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mimoja <coreboot@mimoja.de> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-08-30 19:42:23 +02:00
current += acpi_create_dmar_ds_msi_hpet(current, 0, V_P2SB_HBDF_BUS,
V_P2SB_HBDF_DEV, V_P2SB_HBDF_FUN);
soc/intel/skylake: Generate ACPI DMAR table If the SoC is VT-d capable, write an ACPI DMAR table. The entry for the GFXVTBAR is only generated if the IGD is enabled. Change-Id: I8176401dd19aee7ad09a8a145b7a3801fe5b2ae1 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/21588 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Youness Alaoui <snifikino@gmail.com>
2017-09-18 20:03:46 +02:00
acpi_dmar_drhd_fixup(tmp, current);
}
soc/intel/skylake: Add RMRRs after all DRHDs The VT-d architecture specification (Doc. D51397-011, Rev. 3.1) says: BIOS implementations must report these remapping structure types in numerical order. i.e., All remapping structures of type 0 (DRHD) enumerated before remapping structures of type 1 (RMRR), and so forth. So, update the corresponding code to adhere to the specification. Change-Id: I2446d536603559f637f3f8b1b44e9d712aa35492 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44112 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-08-03 12:29:41 +02:00
/* Then, add RMRR entries after all DRHD entries */
if (emit_igd) {
const unsigned long tmp = current;
current += acpi_create_dmar_rmrr(current, 0,
sa_get_gsm_base(), sa_get_tolud_base() - 1);
current += acpi_create_dmar_ds_pci(current, 0, 2, 0);
acpi_dmar_rmrr_fixup(tmp, current);
}
soc/intel/skylake: Generate ACPI DMAR table If the SoC is VT-d capable, write an ACPI DMAR table. The entry for the GFXVTBAR is only generated if the IGD is enabled. Change-Id: I8176401dd19aee7ad09a8a145b7a3801fe5b2ae1 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/21588 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Youness Alaoui <snifikino@gmail.com>
2017-09-18 20:03:46 +02:00
return current;
}
device: Constify struct device * parameter to write_acpi_tables .write_acpi_tables() should not be updating the device structure. This change makes the struct device * argument to it as const. Change-Id: I50d013e83a404e0a0e3837ca16fa75c7eaa0e14a Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40701 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-04-24 15:41:18 +02:00
unsigned long northbridge_write_acpi_tables(const struct device *const dev,
soc/intel/skylake: Generate ACPI DMAR table If the SoC is VT-d capable, write an ACPI DMAR table. The entry for the GFXVTBAR is only generated if the IGD is enabled. Change-Id: I8176401dd19aee7ad09a8a145b7a3801fe5b2ae1 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/21588 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Youness Alaoui <snifikino@gmail.com>
2017-09-18 20:03:46 +02:00
unsigned long current,
struct acpi_rsdp *const rsdp)
{
soc/intel: Use config_of_path(SA_DEVFN_ROOT) We do not want to disguise somewhat complex function calls as simple macros. Change-Id: I53324603c9ece1334c6e09d51338084166f7a585 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34299 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: David Guckian Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-12 12:10:19 +02:00
const struct soc_intel_skylake_config *const config = config_of(dev);
soc/intel/skylake: Generate ACPI DMAR table If the SoC is VT-d capable, write an ACPI DMAR table. The entry for the GFXVTBAR is only generated if the IGD is enabled. Change-Id: I8176401dd19aee7ad09a8a145b7a3801fe5b2ae1 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/21588 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Youness Alaoui <snifikino@gmail.com>
2017-09-18 20:03:46 +02:00
acpi_dmar_t *const dmar = (acpi_dmar_t *)current;
/* Create DMAR table only if we have VT-d capability. */
soc/intel: Use config_of_path(SA_DEVFN_ROOT) We do not want to disguise somewhat complex function calls as simple macros. Change-Id: I53324603c9ece1334c6e09d51338084166f7a585 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34299 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: David Guckian Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-12 12:10:19 +02:00
if (config->ignore_vtd || !soc_is_vtd_capable())
soc/intel/skylake: Generate ACPI DMAR table If the SoC is VT-d capable, write an ACPI DMAR table. The entry for the GFXVTBAR is only generated if the IGD is enabled. Change-Id: I8176401dd19aee7ad09a8a145b7a3801fe5b2ae1 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/21588 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Youness Alaoui <snifikino@gmail.com>
2017-09-18 20:03:46 +02:00
return current;
printk(BIOS_DEBUG, "ACPI: * DMAR\n");
acpi_create_dmar(dmar, DMAR_INTR_REMAP, acpi_fill_dmar);
current += dmar->header.length;
current = acpi_align_current(current);
acpi_add_table(rsdp, dmar);
return current;
}
soc/intel/skylake: Use Broadwell as comparision base for Skylake SOC Use the Broadwell implementation as the comparison base for Skylake. BRANCH=none BUG=None TEST=None Change-Id: I22eb55ea89eb0d6883f98e4c72a6d243e819e6d8 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10340 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-13 03:19:47 +02:00
unsigned long acpi_madt_irq_overrides(unsigned long current)
{
int sci = acpi_sci_irq();
acpi_madt_irqoverride_t *irqovr;
uint16_t flags = MP_IRQ_TRIGGER_LEVEL;
/* INT_SRC_OVR */
irqovr = (void *)current;
current += acpi_create_madt_irqoverride(irqovr, 0, 0, 2, 0);
if (sci >= 20)
flags |= MP_IRQ_POLARITY_LOW;
else
flags |= MP_IRQ_POLARITY_HIGH;
/* SCI */
irqovr = (void *)current;
current += acpi_create_madt_irqoverride(irqovr, 0, sci, sci, flags);
soc/intel/common/block/gpio: add code for NMI enabling Especially server boards, like the Supermicro X11SSM-F, often have a NMI button and NMI functionality that can be triggered via IPMI. The purpose of this is to cause the OS to create a system crashdump from a hang system or for debugging. Add code for enabling NMI interrupts on GPIOs configured with PAD_CFG_GPI_NMI. The enabling mechanism is the same as SMI, so the SMI function was copied and adapted. The `pad_community` struct gained two variables for the registers. Also register the NMI for LINT1 in the MADT in accordance to ACPI spec. Test: Linux detects the NMI correctly in dmesg: [ 0.053734] ACPI: LAPIC_NMI (acpi_id[0xff] high edge lint[0x1]) Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Change-Id: I4fc1a35c99c6a28b20e08a80b97bb4b8624935c9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48090 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-23 15:53:28 +01:00
/* NMI */
current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 0xff, 5, 1);
soc/intel/skylake: Use Broadwell as comparision base for Skylake SOC Use the Broadwell implementation as the comparison base for Skylake. BRANCH=none BUG=None TEST=None Change-Id: I22eb55ea89eb0d6883f98e4c72a6d243e819e6d8 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10340 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-13 03:19:47 +02:00
return current;
}
soc/intel: Add Skylake SOC support Add the files to support the Skylake SOC. Matches chromium tree at 927026db BRANCH=none BUG=None TEST=Build and run on a Skylake platform Change-Id: I80248f7e47eaf13b52e3c7ff951eb1976edbaa15 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10341 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-05-13 03:23:27 +02:00
device: Constify struct device * parameter to write_acpi_tables .write_acpi_tables() should not be updating the device structure. This change makes the struct device * argument to it as const. Change-Id: I50d013e83a404e0a0e3837ca16fa75c7eaa0e14a Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40701 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-04-24 15:41:18 +02:00
unsigned long southbridge_write_acpi_tables(const struct device *device,
soc/intel: Add Skylake SOC support Add the files to support the Skylake SOC. Matches chromium tree at 927026db BRANCH=none BUG=None TEST=Build and run on a Skylake platform Change-Id: I80248f7e47eaf13b52e3c7ff951eb1976edbaa15 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10341 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-05-13 03:23:27 +02:00
unsigned long current,
struct acpi_rsdp *rsdp)
{
soc/intel: Enable ACPI DBG2 table generation Enable the ACPI DBG2 table generation for Intel boards. This is a Microsoft defined ACPI extension that allows an OS to know what the debug port is on a system when it is not enabled by the firmware, so it does not show up in the coreboot tables and cannot be easily found by a payload. broadwell: Use byte access device, set up only when enabled since it relies on the port being put in byte access mode and using this serial port for debug was not standard in this generation. skylake: Enable for the configured debug port. Skylake uses intelblocks for UART but not ACPI. common: Enable for the configured debug port. This affects apollolake and cannonlake. Tested by compiling for apollolake/broadwell, tested by reading the DBG2 ACPI table on kabylake board and using IASL to dump: [000h 0000 4] Signature : "DBG2" [004h 0004 4] Table Length : 00000061 [008h 0008 1] Revision : 00 [009h 0009 1] Checksum : 3B [00Ah 0010 6] Oem ID : "CORE " [010h 0016 8] Oem Table ID : "COREBOOT" [018h 0024 4] Oem Revision : 00000000 [01Ch 0028 4] Asl Compiler ID : "CORE" [020h 0032 4] Asl Compiler Revision : 00000000 [024h 0036 4] Info Offset : 0000002C [028h 0040 4] Info Count : 00000001 [02Ch 0044 1] Revision : 00 [02Dh 0045 2] Length : 0035 [02Fh 0047 1] Register Count : 01 [030h 0048 2] Namepath Length : 000F [032h 0050 2] Namepath Offset : 0026 [034h 0052 2] OEM Data Length : 0000 [036h 0054 2] OEM Data Offset : 0000 [038h 0056 2] Port Type : 8000 [03Ah 0058 2] Port Subtype : 0000 [03Ch 0060 2] Reserved : 0000 [03Eh 0062 2] Base Address Offset : 0016 [040h 0064 2] Address Size Offset : 0022 [042h 0066 12] Base Address Register : [Generic Address Structure] [042h 0066 1] Space ID : 00 [SystemMemory] [043h 0067 1] Bit Width : 00 [044h 0068 1] Bit Offset : 00 [045h 0069 1] Encoded Access Width : 03 [DWord Access:32] [046h 0070 8] Address : 00000000FE034000 [04Eh 0078 4] Address Size : 00001000 [052h 0082 15] Namepath : "\_SB.PCI0.UAR2" Change-Id: If34a3d2252896e0b0f762136760ab981afc12a2f Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/22453 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-12 05:03:29 +01:00
current = acpi_write_dbg2_pci_uart(rsdp, current,
soc/intel/common/block: Move common uart function to block/uart This patch moves uart functions which are common across multiple soc to block/uart. This will remove redundant code copy from soc {skylake/apollolake/cannonlake}. BUG=b:78109109 BRANCH=none TEST=Build and boot on KBL/APL/CNL platform. Change-Id: I109d0e5c942e499cb763bde47cb7d53dfbf5cef6 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/26164 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-05-24 08:51:06 +02:00
uart_get_device(),
soc/intel: Enable ACPI DBG2 table generation Enable the ACPI DBG2 table generation for Intel boards. This is a Microsoft defined ACPI extension that allows an OS to know what the debug port is on a system when it is not enabled by the firmware, so it does not show up in the coreboot tables and cannot be easily found by a payload. broadwell: Use byte access device, set up only when enabled since it relies on the port being put in byte access mode and using this serial port for debug was not standard in this generation. skylake: Enable for the configured debug port. Skylake uses intelblocks for UART but not ACPI. common: Enable for the configured debug port. This affects apollolake and cannonlake. Tested by compiling for apollolake/broadwell, tested by reading the DBG2 ACPI table on kabylake board and using IASL to dump: [000h 0000 4] Signature : "DBG2" [004h 0004 4] Table Length : 00000061 [008h 0008 1] Revision : 00 [009h 0009 1] Checksum : 3B [00Ah 0010 6] Oem ID : "CORE " [010h 0016 8] Oem Table ID : "COREBOOT" [018h 0024 4] Oem Revision : 00000000 [01Ch 0028 4] Asl Compiler ID : "CORE" [020h 0032 4] Asl Compiler Revision : 00000000 [024h 0036 4] Info Offset : 0000002C [028h 0040 4] Info Count : 00000001 [02Ch 0044 1] Revision : 00 [02Dh 0045 2] Length : 0035 [02Fh 0047 1] Register Count : 01 [030h 0048 2] Namepath Length : 000F [032h 0050 2] Namepath Offset : 0026 [034h 0052 2] OEM Data Length : 0000 [036h 0054 2] OEM Data Offset : 0000 [038h 0056 2] Port Type : 8000 [03Ah 0058 2] Port Subtype : 0000 [03Ch 0060 2] Reserved : 0000 [03Eh 0062 2] Base Address Offset : 0016 [040h 0064 2] Address Size Offset : 0022 [042h 0066 12] Base Address Register : [Generic Address Structure] [042h 0066 1] Space ID : 00 [SystemMemory] [043h 0067 1] Bit Width : 00 [044h 0068 1] Bit Offset : 00 [045h 0069 1] Encoded Access Width : 03 [DWord Access:32] [046h 0070 8] Address : 00000000FE034000 [04Eh 0078 4] Address Size : 00001000 [052h 0082 15] Namepath : "\_SB.PCI0.UAR2" Change-Id: If34a3d2252896e0b0f762136760ab981afc12a2f Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/22453 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-12 05:03:29 +01:00
ACPI_ACCESS_SIZE_DWORD_ACCESS);
soc/intel: Add Skylake SOC support Add the files to support the Skylake SOC. Matches chromium tree at 927026db BRANCH=none BUG=None TEST=Build and run on a Skylake platform Change-Id: I80248f7e47eaf13b52e3c7ff951eb1976edbaa15 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10341 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-05-13 03:23:27 +02:00
current = acpi_write_hpet(device, current, rsdp);
x86 acpi: remove ALIGN_CURRENT macro The ALIGN_CURRENT macro relied on a local variable name as well as being defined in numerous compilation units. Replace those instances with an acpi_align_current() inline function. Change-Id: Iab453f2eda1addefad8a1c37d265f917bd803202 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12707 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-12-11 00:07:38 +01:00
return acpi_align_current(current);
soc/intel: Add Skylake SOC support Add the files to support the Skylake SOC. Matches chromium tree at 927026db BRANCH=none BUG=None TEST=Build and run on a Skylake platform Change-Id: I80248f7e47eaf13b52e3c7ff951eb1976edbaa15 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10341 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-05-13 03:23:27 +02:00
}
skylake: Use common ACPI _SWS code Enable and use the common code for filling out the NVS data used by the _SWS methods. Add a function to provide the wake source data. With Deep S3 enabled skylake does not retain the contents of the PM1_EN register so instead just select the wake related events in PM1_STS. BUG=chrome-os-partner:40635 BRANCH=none TEST=tested on glados by checking for valid _SWS string in /sys/firmware/log after suspend/resume. Wake sources that were tested are RTC, power button, keypress, trackpad, and wifi. Change-Id: I93a4f740f2e2ef1c34e948db1d8e273332296921 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: cb4d4705b87ef7169f1979009c34a58de93c4ef0 Original-Change-Id: Ib6b4df09ea3090894f09290d00dcdc5aebc3eabb Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/298169 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11648 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-09 01:12:44 +02:00
/* Save wake source information for calculating ACPI _SWS values */
soc/intel: Refactor fill_acpi_wake() Change-Id: I7fcc2b36cfe57adf8ae3a6acf8b54e19504202a5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49878 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-22 18:59:07 +01:00
int soc_fill_acpi_wake(const struct chipset_power_state *ps, uint32_t *pm1, uint32_t **gpe0)
skylake: Use common ACPI _SWS code Enable and use the common code for filling out the NVS data used by the _SWS methods. Add a function to provide the wake source data. With Deep S3 enabled skylake does not retain the contents of the PM1_EN register so instead just select the wake related events in PM1_STS. BUG=chrome-os-partner:40635 BRANCH=none TEST=tested on glados by checking for valid _SWS string in /sys/firmware/log after suspend/resume. Wake sources that were tested are RTC, power button, keypress, trackpad, and wifi. Change-Id: I93a4f740f2e2ef1c34e948db1d8e273332296921 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: cb4d4705b87ef7169f1979009c34a58de93c4ef0 Original-Change-Id: Ib6b4df09ea3090894f09290d00dcdc5aebc3eabb Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/298169 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11648 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-09 01:12:44 +02:00
{
soc/intel: Replace config_of_path() with config_of_soc() The previously provided device path made no difference, all integrated PCI devices point back to the same chip_info structure. Change reduces the exposure of various SA_DEVFN_xx and PCH_DEVFN_xx from (ugly) soc/pci_devs.h. Change-Id: Ibf13645fdd3ef7fd3d5c8217bb24d7ede045c790 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35656 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-09-27 23:20:27 +02:00
const struct soc_intel_skylake_config *config = config_of_soc();
skylake: Use common ACPI _SWS code Enable and use the common code for filling out the NVS data used by the _SWS methods. Add a function to provide the wake source data. With Deep S3 enabled skylake does not retain the contents of the PM1_EN register so instead just select the wake related events in PM1_STS. BUG=chrome-os-partner:40635 BRANCH=none TEST=tested on glados by checking for valid _SWS string in /sys/firmware/log after suspend/resume. Wake sources that were tested are RTC, power button, keypress, trackpad, and wifi. Change-Id: I93a4f740f2e2ef1c34e948db1d8e273332296921 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: cb4d4705b87ef7169f1979009c34a58de93c4ef0 Original-Change-Id: Ib6b4df09ea3090894f09290d00dcdc5aebc3eabb Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/298169 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11648 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-09 01:12:44 +02:00
static uint32_t gpe0_sts[GPE0_REG_MAX];
uint32_t pm1_en;
skylake: Fix wake source reporting with Deep S3 The Deep S3 state will lose a lot of register contents that we used to rely on for determining wake source. In order to make use of this override the enable bit for wake sources that are enabled for Deep S3 in devicetree.cb. BUG=chrome-os-partner:58666 TEST=check for _SWS reporting wake source on S3 resume on skylake Change-Id: If5113d6890f6cbecc32f92af67a29952266fe0ac Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/17137 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-10-26 05:07:22 +02:00
uint32_t gpe0_std;
skylake: Use common ACPI _SWS code Enable and use the common code for filling out the NVS data used by the _SWS methods. Add a function to provide the wake source data. With Deep S3 enabled skylake does not retain the contents of the PM1_EN register so instead just select the wake related events in PM1_STS. BUG=chrome-os-partner:40635 BRANCH=none TEST=tested on glados by checking for valid _SWS string in /sys/firmware/log after suspend/resume. Wake sources that were tested are RTC, power button, keypress, trackpad, and wifi. Change-Id: I93a4f740f2e2ef1c34e948db1d8e273332296921 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: cb4d4705b87ef7169f1979009c34a58de93c4ef0 Original-Change-Id: Ib6b4df09ea3090894f09290d00dcdc5aebc3eabb Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/298169 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11648 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-09 01:12:44 +02:00
int i;
soc/intel/skylake: don't hardcode GPE0 standard reg While using '3' is fine for the standard gpe0 for skylake, I want to make sure anyone that copies this code doesn't tweak GPE0_REG_MAX without the hard coded index. If that does happen now things will still work, but it may just not match the hardware proper. BUG=chrome-os-partner:58666 Change-Id: I434b9a765a0a2f263490bb2b4ecb3635292d46c9 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17160 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-10-27 16:53:17 +02:00
const int last_index = GPE0_REG_MAX - 1;
skylake: Use common ACPI _SWS code Enable and use the common code for filling out the NVS data used by the _SWS methods. Add a function to provide the wake source data. With Deep S3 enabled skylake does not retain the contents of the PM1_EN register so instead just select the wake related events in PM1_STS. BUG=chrome-os-partner:40635 BRANCH=none TEST=tested on glados by checking for valid _SWS string in /sys/firmware/log after suspend/resume. Wake sources that were tested are RTC, power button, keypress, trackpad, and wifi. Change-Id: I93a4f740f2e2ef1c34e948db1d8e273332296921 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: cb4d4705b87ef7169f1979009c34a58de93c4ef0 Original-Change-Id: Ib6b4df09ea3090894f09290d00dcdc5aebc3eabb Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/298169 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11648 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-09 01:12:44 +02:00
skylake: Fix wake source reporting with Deep S3 The Deep S3 state will lose a lot of register contents that we used to rely on for determining wake source. In order to make use of this override the enable bit for wake sources that are enabled for Deep S3 in devicetree.cb. BUG=chrome-os-partner:58666 TEST=check for _SWS reporting wake source on S3 resume on skylake Change-Id: If5113d6890f6cbecc32f92af67a29952266fe0ac Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/17137 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-10-26 05:07:22 +02:00
pm1_en = ps->pm1_en;
gpe0_std = ps->gpe0_en[3];
/*
* Chipset state in the suspend well (but not RTC) is lost in Deep S3
* so enable Deep S3 wake events that are configured by the mainboard
*/
soc/intel/skylake: Split AC/DC settings for Deep Sx config Currently when enabling Deep S3 or Deep S5 it unconditionally gets enabled in both DC and AC states. However since using Deep S3 disables some expected features like wake-on-USB it is not always desired to enable the same state in both modes. To address this split the setting and add a separate config for Deep Sx in AC and DC states. All motherboards that set this config were updated, but there is no actual change in behavior in this commit. BUG=b:36723679 BRANCH=none TEST=This commit has no runtime visible changes, I verified on Eve that the Deep SX config registers are unchanged, and it compiles for all affected boards. Change-Id: I590f145847785b5a7687f235304e988888fcea8a Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/19239 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-04-11 06:02:13 +02:00
if (ps->prev_sleep_state == ACPI_S3 &&
(config->deep_s3_enable_ac || config->deep_s3_enable_dc)) {
skylake: Fix wake source reporting with Deep S3 The Deep S3 state will lose a lot of register contents that we used to rely on for determining wake source. In order to make use of this override the enable bit for wake sources that are enabled for Deep S3 in devicetree.cb. BUG=chrome-os-partner:58666 TEST=check for _SWS reporting wake source on S3 resume on skylake Change-Id: If5113d6890f6cbecc32f92af67a29952266fe0ac Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/17137 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-10-26 05:07:22 +02:00
pm1_en |= PWRBTN_STS; /* Always enabled as wake source */
if (config->deep_sx_config & DSX_EN_LAN_WAKE_PIN)
gpe0_std |= LAN_WAK_EN;
if (config->deep_sx_config & DSX_EN_WAKE_PIN)
pm1_en |= PCIEXPWAK_STS;
}
skylake: Use common ACPI _SWS code Enable and use the common code for filling out the NVS data used by the _SWS methods. Add a function to provide the wake source data. With Deep S3 enabled skylake does not retain the contents of the PM1_EN register so instead just select the wake related events in PM1_STS. BUG=chrome-os-partner:40635 BRANCH=none TEST=tested on glados by checking for valid _SWS string in /sys/firmware/log after suspend/resume. Wake sources that were tested are RTC, power button, keypress, trackpad, and wifi. Change-Id: I93a4f740f2e2ef1c34e948db1d8e273332296921 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: cb4d4705b87ef7169f1979009c34a58de93c4ef0 Original-Change-Id: Ib6b4df09ea3090894f09290d00dcdc5aebc3eabb Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/298169 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11648 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-09 01:12:44 +02:00
*pm1 = ps->pm1_sts & pm1_en;
/* Mask off GPE0 status bits that are not enabled */
*gpe0 = &gpe0_sts[0];
soc/intel/skylake: don't hardcode GPE0 standard reg While using '3' is fine for the standard gpe0 for skylake, I want to make sure anyone that copies this code doesn't tweak GPE0_REG_MAX without the hard coded index. If that does happen now things will still work, but it may just not match the hardware proper. BUG=chrome-os-partner:58666 Change-Id: I434b9a765a0a2f263490bb2b4ecb3635292d46c9 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17160 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-10-27 16:53:17 +02:00
for (i = 0; i < last_index; i++)
skylake: Use common ACPI _SWS code Enable and use the common code for filling out the NVS data used by the _SWS methods. Add a function to provide the wake source data. With Deep S3 enabled skylake does not retain the contents of the PM1_EN register so instead just select the wake related events in PM1_STS. BUG=chrome-os-partner:40635 BRANCH=none TEST=tested on glados by checking for valid _SWS string in /sys/firmware/log after suspend/resume. Wake sources that were tested are RTC, power button, keypress, trackpad, and wifi. Change-Id: I93a4f740f2e2ef1c34e948db1d8e273332296921 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: cb4d4705b87ef7169f1979009c34a58de93c4ef0 Original-Change-Id: Ib6b4df09ea3090894f09290d00dcdc5aebc3eabb Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/298169 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11648 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-09 01:12:44 +02:00
gpe0_sts[i] = ps->gpe0_sts[i] & ps->gpe0_en[i];
soc/intel/skylake: don't hardcode GPE0 standard reg While using '3' is fine for the standard gpe0 for skylake, I want to make sure anyone that copies this code doesn't tweak GPE0_REG_MAX without the hard coded index. If that does happen now things will still work, but it may just not match the hardware proper. BUG=chrome-os-partner:58666 Change-Id: I434b9a765a0a2f263490bb2b4ecb3635292d46c9 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17160 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-10-27 16:53:17 +02:00
gpe0_sts[last_index] = ps->gpe0_sts[last_index] & gpe0_std;
skylake: Use common ACPI _SWS code Enable and use the common code for filling out the NVS data used by the _SWS methods. Add a function to provide the wake source data. With Deep S3 enabled skylake does not retain the contents of the PM1_EN register so instead just select the wake related events in PM1_STS. BUG=chrome-os-partner:40635 BRANCH=none TEST=tested on glados by checking for valid _SWS string in /sys/firmware/log after suspend/resume. Wake sources that were tested are RTC, power button, keypress, trackpad, and wifi. Change-Id: I93a4f740f2e2ef1c34e948db1d8e273332296921 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: cb4d4705b87ef7169f1979009c34a58de93c4ef0 Original-Change-Id: Ib6b4df09ea3090894f09290d00dcdc5aebc3eabb Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/298169 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11648 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-09 01:12:44 +02:00
return GPE0_REG_MAX;
}
device: acpi_name() should take a const struct device There's no reason to mutate the struct device when determining the ACPI name for a device. Adjust the function pointer signature and the respective implementations to use const struct device. Change-Id: If5e1f4de36a53646616581b01f47c4e86822c42e Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/21527 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-09-14 00:01:52 +02:00
const char *soc_acpi_name(const struct device *dev)
soc/intel/skylake: Add FSP 2.0 support in ramstage Add FSP 2.0 support in ramstage. Populate required Fsp Silicon Init params and configure mainboard specific GPIOs. Define function fsp_soc_get_igd_bar needed by fsp2.0 driver for pre OS screens. Change-Id: Ib38ca7547b5d5ec2b268698b8886d5caa28d6497 Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/16592 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-08-30 17:17:13 +02:00
{
if (dev->path.type == DEVICE_PATH_DOMAIN)
return "PCI0";
soc/intel: Add support for USB ACPI code generation To support generating USB devices in ACPI the platform needs to know how to determine a device name for each USB port, and for any root hubs that may be present. Recent Intel platforms route all ports to an XHCI controller through a root hub. This is supported by considering the root hub to be USB port type 0, the USB 2.0 ports to be type 2, and the USB 3.0 ports to be type 3. This was tested with a Kaby Lake platform by adding entries to the devicetree and checking the resulting SSDT. Change-Id: I527a63bdc64f9243fe57487363ee6d5f60be84ca Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/26174 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-05-08 00:33:18 +02:00
if (dev->path.type == DEVICE_PATH_USB) {
switch (dev->path.usb.port_type) {
case 0:
/* Root Hub */
return "RHUB";
case 2:
/* USB2 ports */
switch (dev->path.usb.port_id) {
case 0: return "HS01";
case 1: return "HS02";
case 2: return "HS03";
case 3: return "HS04";
case 4: return "HS05";
case 5: return "HS06";
case 6: return "HS07";
case 7: return "HS08";
case 8: return "HS09";
case 9: return "HS10";
}
break;
case 3:
/* USB3 ports */
switch (dev->path.usb.port_id) {
case 0: return "SS01";
case 1: return "SS02";
case 2: return "SS03";
case 3: return "SS04";
case 4: return "SS05";
case 5: return "SS06";
}
break;
}
return NULL;
}
soc/intel/skylake: Add FSP 2.0 support in ramstage Add FSP 2.0 support in ramstage. Populate required Fsp Silicon Init params and configure mainboard specific GPIOs. Define function fsp_soc_get_igd_bar needed by fsp2.0 driver for pre OS screens. Change-Id: Ib38ca7547b5d5ec2b268698b8886d5caa28d6497 Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/16592 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-08-30 17:17:13 +02:00
if (dev->path.type != DEVICE_PATH_PCI)
return NULL;
soc/intel/skylake/acpi.c: Name devices on secondary bus Naming a device allows an ACPI _ROM method to be written for it. GPUs may require this to make the configuration data contained within available to an OS driver. This may be required for GPUs that do not contain their vBIOS, or perhaps the drivers require it in this form/fashion. Working on an Acer Aspire VN7-572G (Skylake-U). nouveau successfully obtains the vBIOS via ACPI (kernel 5.7.11). Change-Id: Ida87aebf8fdf341ab350c2bb3704d2ef695cf8f0 Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43074 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-08-06 21:13:09 +02:00
/* Match functions 0 and 1 for possible GPUs on a secondary bus */
if (dev->bus && dev->bus->secondary > 0) {
switch (PCI_FUNC(dev->path.pci.devfn)) {
case 0: return "DEV0";
case 1: return "DEV1";
}
soc/intel/skylake: Fix ACPI exception AE_NOT_FOUND Make sure to match devices on the root bus only. This fixes an issue where the SoC returned "MCHC" as ACPI name for devices behind bridge devices, as the DEVFN matched. Fixes observed "ACPI exception: AE_NOT_FOUND" in dmesg, as the ACPI path no longer contains invalid names. Tested on Supermicro X11SSH-TF. Change-Id: I6eca37a1792287502a46a90144f2f0d8e12ae5d4 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35621 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-09-26 14:45:29 +02:00
return NULL;
soc/intel/skylake/acpi.c: Name devices on secondary bus Naming a device allows an ACPI _ROM method to be written for it. GPUs may require this to make the configuration data contained within available to an OS driver. This may be required for GPUs that do not contain their vBIOS, or perhaps the drivers require it in this form/fashion. Working on an Acer Aspire VN7-572G (Skylake-U). nouveau successfully obtains the vBIOS via ACPI (kernel 5.7.11). Change-Id: Ida87aebf8fdf341ab350c2bb3704d2ef695cf8f0 Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43074 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-08-06 21:13:09 +02:00
}
soc/intel/skylake: Fix ACPI exception AE_NOT_FOUND Make sure to match devices on the root bus only. This fixes an issue where the SoC returned "MCHC" as ACPI name for devices behind bridge devices, as the DEVFN matched. Fixes observed "ACPI exception: AE_NOT_FOUND" in dmesg, as the ACPI path no longer contains invalid names. Tested on Supermicro X11SSH-TF. Change-Id: I6eca37a1792287502a46a90144f2f0d8e12ae5d4 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35621 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-09-26 14:45:29 +02:00
soc/intel/skylake: Add FSP 2.0 support in ramstage Add FSP 2.0 support in ramstage. Populate required Fsp Silicon Init params and configure mainboard specific GPIOs. Define function fsp_soc_get_igd_bar needed by fsp2.0 driver for pre OS screens. Change-Id: Ib38ca7547b5d5ec2b268698b8886d5caa28d6497 Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/16592 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-08-30 17:17:13 +02:00
switch (dev->path.pci.devfn) {
case SA_DEVFN_ROOT: return "MCHC";
soc/intel/skylake/acpi.c: Name devices on secondary bus Naming a device allows an ACPI _ROM method to be written for it. GPUs may require this to make the configuration data contained within available to an OS driver. This may be required for GPUs that do not contain their vBIOS, or perhaps the drivers require it in this form/fashion. Working on an Acer Aspire VN7-572G (Skylake-U). nouveau successfully obtains the vBIOS via ACPI (kernel 5.7.11). Change-Id: Ida87aebf8fdf341ab350c2bb3704d2ef695cf8f0 Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43074 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-08-06 21:13:09 +02:00
case SA_DEVFN_PEG0: return "PEGP";
soc/intel/skylake: Add FSP 2.0 support in ramstage Add FSP 2.0 support in ramstage. Populate required Fsp Silicon Init params and configure mainboard specific GPIOs. Define function fsp_soc_get_igd_bar needed by fsp2.0 driver for pre OS screens. Change-Id: Ib38ca7547b5d5ec2b268698b8886d5caa28d6497 Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/16592 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-08-30 17:17:13 +02:00
case SA_DEVFN_IGD: return "GFX0";
case PCH_DEVFN_ISH: return "ISHB";
case PCH_DEVFN_XHCI: return "XHCI";
case PCH_DEVFN_USBOTG: return "XDCI";
case PCH_DEVFN_THERMAL: return "THRM";
case PCH_DEVFN_CIO: return "ICIO";
case PCH_DEVFN_I2C0: return "I2C0";
case PCH_DEVFN_I2C1: return "I2C1";
case PCH_DEVFN_I2C2: return "I2C2";
case PCH_DEVFN_I2C3: return "I2C3";
soc/pci_devs.h: Use consistent naming in soc/pci_devs.h This patch to make common PCI device name between APL and SKL. Change-Id: I5e4c7502e9678c0a367e9c7a96cf848d5b24f68e Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/18576 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-05 08:07:00 +01:00
case PCH_DEVFN_CSE: return "CSE1";
case PCH_DEVFN_CSE_2: return "CSE2";
case PCH_DEVFN_CSE_IDER: return "CSED";
case PCH_DEVFN_CSE_KT: return "CSKT";
case PCH_DEVFN_CSE_3: return "CSE3";
soc/intel/skylake: Add FSP 2.0 support in ramstage Add FSP 2.0 support in ramstage. Populate required Fsp Silicon Init params and configure mainboard specific GPIOs. Define function fsp_soc_get_igd_bar needed by fsp2.0 driver for pre OS screens. Change-Id: Ib38ca7547b5d5ec2b268698b8886d5caa28d6497 Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/16592 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-08-30 17:17:13 +02:00
case PCH_DEVFN_SATA: return "SATA";
case PCH_DEVFN_UART2: return "UAR2";
case PCH_DEVFN_I2C4: return "I2C4";
case PCH_DEVFN_I2C5: return "I2C5";
case PCH_DEVFN_PCIE1: return "RP01";
case PCH_DEVFN_PCIE2: return "RP02";
case PCH_DEVFN_PCIE3: return "RP03";
case PCH_DEVFN_PCIE4: return "RP04";
case PCH_DEVFN_PCIE5: return "RP05";
case PCH_DEVFN_PCIE6: return "RP06";
case PCH_DEVFN_PCIE7: return "RP07";
case PCH_DEVFN_PCIE8: return "RP08";
case PCH_DEVFN_PCIE9: return "RP09";
case PCH_DEVFN_PCIE10: return "RP10";
case PCH_DEVFN_PCIE11: return "RP11";
case PCH_DEVFN_PCIE12: return "RP12";
soc/intel/skl/acpi: add description for missing PCIe ports According to the documentation, Sunrise PCH-H [1,2] and Lewisburg PCH [3] supports up to 16 PCIe ports. However, ACPI contains a description for only 12 ports. This patch adds ACPI code for missing ports [1] page 182, Intel (R) 100 Series and Intel (R) C230 Series PCH Family Platform Controller Hub (PCH), Datasheet, Vol 1 of 2, December 2018, Document Number: 332690-005EN [2] page 180, Intel (R) 200 Series and Intel (R) Z370 Series PCH Family Platform Controller Hub (PCH), Datasheet, Vol 1 of 2, October 2017, Document Number: 335192-003 [3] page 39, Intel(R) C620 Series Chipset Platform Controller Hub (PCH) Datasheet, May 2019. Document Number: 336067-007US Change-Id: I954870136e0c8e5ff5d7ff623c7a6432b829abaf Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35072 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-08-23 14:22:21 +02:00
case PCH_DEVFN_PCIE13: return "RP13";
case PCH_DEVFN_PCIE14: return "RP14";
case PCH_DEVFN_PCIE15: return "RP15";
case PCH_DEVFN_PCIE16: return "RP16";
soc/intel/skylake: Add FSP 2.0 support in ramstage Add FSP 2.0 support in ramstage. Populate required Fsp Silicon Init params and configure mainboard specific GPIOs. Define function fsp_soc_get_igd_bar needed by fsp2.0 driver for pre OS screens. Change-Id: Ib38ca7547b5d5ec2b268698b8886d5caa28d6497 Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/16592 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-08-30 17:17:13 +02:00
case PCH_DEVFN_UART0: return "UAR0";
case PCH_DEVFN_UART1: return "UAR1";
case PCH_DEVFN_GSPI0: return "SPI0";
case PCH_DEVFN_GSPI1: return "SPI1";
case PCH_DEVFN_EMMC: return "EMMC";
case PCH_DEVFN_SDIO: return "SDIO";
case PCH_DEVFN_SDCARD: return "SDXC";
case PCH_DEVFN_P2SB: return "P2SB";
case PCH_DEVFN_PMC: return "PMC_";
case PCH_DEVFN_HDA: return "HDAS";
case PCH_DEVFN_SMBUS: return "SBUS";
case PCH_DEVFN_SPI: return "FSPI";
case PCH_DEVFN_GBE: return "IGBE";
case PCH_DEVFN_TRACEHUB:return "THUB";
}
return NULL;
}
soc/intel/skylake: Implement GPIO ACPI AML generating functions Implement GPIO ACPI AML generating functions that can be called by coreboot drivers to generate GPIO manipulation code in AML. Following API functions are implemented: 1. acpigen_soc_read_rx_gpio 2. acpigen_soc_get_tx_gpio 3. acpigen_soc_set_tx_gpio 4. acpigen_soc_clear_tx_gpio In addition to the API functions above, helper functions are added to gpio.asl to set/clear/get Tx value of GPIO. BUG=b:62028489 Change-Id: I77e5d0decd8929a922d06b02312378f092551667 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19828 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-05-23 20:53:47 +02:00
static int acpigen_soc_gpio_op(const char *op, unsigned int gpio_num)
{
/* op (gpio_num) */
acpigen_emit_namestring(op);
acpigen_write_integer(gpio_num);
return 0;
}
static int acpigen_soc_get_gpio_state(const char *op, unsigned int gpio_num)
{
/* Store (op (gpio_num), Local0) */
acpigen_write_store();
acpigen_soc_gpio_op(op, gpio_num);
acpigen_emit_byte(LOCAL0_OP);
return 0;
}
int acpigen_soc_read_rx_gpio(unsigned int gpio_num)
{
return acpigen_soc_get_gpio_state("\\_SB.PCI0.GRXS", gpio_num);
}
int acpigen_soc_get_tx_gpio(unsigned int gpio_num)
{
return acpigen_soc_get_gpio_state("\\_SB.PCI0.GTXS", gpio_num);
}
int acpigen_soc_set_tx_gpio(unsigned int gpio_num)
{
return acpigen_soc_gpio_op("\\_SB.PCI0.STXS", gpio_num);
}
int acpigen_soc_clear_tx_gpio(unsigned int gpio_num)
{
return acpigen_soc_gpio_op("\\_SB.PCI0.CTXS", gpio_num);
}
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