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coreboot-kgpe-d16/src/soc/intel/apollolake/pmutil.c

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soc/apollolake: Add helper functions to access Power Management Registers Change-Id: I928efea33030e03cbbaead6812c617d20446f7c9 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/14289 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-02-05 05:13:34 +01:00
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2013 Google Inc.
* Copyright (C) 2015-2016 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
soc/apollolake/pmutil: Get PMC base address dynamically Instead of using a hardcoded address for PMC device BAR0, read it dynamically. This allows the allocator to move the BAR without needing a fixed resource. Note that we cannot do the same for the ACPI BAR (index 0x20), as it cannot be read back. Change-Id: If43e1ccb693ffb17b78bdd76140a0849493a0010 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com> Reviewed-on: https://review.coreboot.org/14633 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-04-05 21:40:24 +02:00
#define __SIMPLE_DEVICE__
soc/intel/apollolake: Add function to read and clear GPE status Implement the generic acpi_get_gpe() function to read and clear the GPE status for a specific GPE. Tested by watching GPE status in a loop while generating interrupts manually from the EC console. BUG=chrome-os-partner:53336 Change-Id: I482ff52051a48441333b573f1cd0fa7f7579a6ab Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/16671 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-19 21:05:49 +02:00
#include <arch/acpi.h>
soc/apollolake: Add helper functions to access Power Management Registers Change-Id: I928efea33030e03cbbaead6812c617d20446f7c9 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/14289 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-02-05 05:13:34 +01:00
#include <arch/io.h>
#include <console/console.h>
soc/apollolake: Return correct wake status in _SWS Wake status is calculated from the four pairs of gpe0 in cbmem CBMEM_ID_POWER_STATE which is filled very early in romstage and depends on the routing information in PMC GPE_CFG register. Coreboot sets the proper value of routing based on devicetree from pmc_init. But when system goes to S3 on waking up PMC is writing default values again in GPE_CFG which results in returning wrong wake status in _SWS. This patch corrects that behaviour by correcting the gpe0 pairs in cbmem after PMC sets the routing table in resume path. BUG=chrome-os-partner:54876 TEST=On resume through powerbtn, lidopen, keyboard press, etc. we are getting proper wake status. Change-Id: I5942d5c20d8c6aef73468dc611190bb7c49c7c7a Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/16040 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Brandon Breitenstein <brandon.breitenstein@intel.com>
2016-08-03 02:25:13 +02:00
#include <cbmem.h>
soc/intel/apollolake: Enable ACPI PM timer emulation on all CPUs Currently we enable ACPI PM timer emulation only on BSP. So the timer doesn't work on other cores and that breaks OSes that use it. Also, microcode uses this information to figure out ACPI IO base, and that is used for other features. This patch enables ACPI timer emulation on all the logical CPUs. BUG=chrome-os-partner:60011 TEST=iotools rdmsr x 0x121, x={0..3}, make sure it is set Change-Id: I0d6cb8761c1c25d3a2fcf59a49c1eda9e4ccc70c Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/17663 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-12-01 02:39:16 +01:00
#include <cpu/x86/msr.h>
soc/apollolake: Add helper functions to access Power Management Registers Change-Id: I928efea33030e03cbbaead6812c617d20446f7c9 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/14289 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-02-05 05:13:34 +01:00
#include <rules.h>
#include <device/pci_def.h>
soc/intel/apollolake: provide poweroff() implementation Implement poweroff() by putting the chipset into ACPI S5 state. BUG=chrome-os-partner:54977 Change-Id: I4ee269f03afd252d4bce909a8cc7c64d6270b16e Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15686 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
2016-07-14 07:26:50 +02:00
#include <halt.h>
soc/intel/apollolake: Use CPU common library code This patch makes SOC files to use common/block/cpu/cpulib.c file's helper functions. Change-Id: I529c67cf20253cf819d1c13849300788104b083c Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/19827 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-05-23 14:47:14 +02:00
#include <intelblocks/msr.h>
soc/apollolake: Add helper functions to access Power Management Registers Change-Id: I928efea33030e03cbbaead6812c617d20446f7c9 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/14289 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-02-05 05:13:34 +01:00
#include <soc/iomap.h>
soc/intel/apollolake: Enable ACPI PM timer emulation on all CPUs Currently we enable ACPI PM timer emulation only on BSP. So the timer doesn't work on other cores and that breaks OSes that use it. Also, microcode uses this information to figure out ACPI IO base, and that is used for other features. This patch enables ACPI timer emulation on all the logical CPUs. BUG=chrome-os-partner:60011 TEST=iotools rdmsr x 0x121, x={0..3}, make sure it is set Change-Id: I0d6cb8761c1c25d3a2fcf59a49c1eda9e4ccc70c Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/17663 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-12-01 02:39:16 +01:00
#include <soc/cpu.h>
soc/apollolake/pmutil: Get PMC base address dynamically Instead of using a hardcoded address for PMC device BAR0, read it dynamically. This allows the allocator to move the BAR without needing a fixed resource. Note that we cannot do the same for the ACPI BAR (index 0x20), as it cannot be read back. Change-Id: If43e1ccb693ffb17b78bdd76140a0849493a0010 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com> Reviewed-on: https://review.coreboot.org/14633 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-04-05 21:40:24 +02:00
#include <soc/pci_devs.h>
soc/apollolake: Add helper functions to access Power Management Registers Change-Id: I928efea33030e03cbbaead6812c617d20446f7c9 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/14289 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-02-05 05:13:34 +01:00
#include <soc/pm.h>
#include <device/device.h>
#include <device/pci.h>
soc/intel/{sky,apollo}lake: Wait until GPE is clear when reading When reading+clearing a GPE for use as an interrupt we need to re-read the status register and keep setting the clear bit until it actually reads back clear. Also add a 1ms timeout in case the status never clears. This is needed if a device sends a longer interrupt pulse and it is still asserted when the "ISR" goes to clear the status. BUG=chrome-os-partner:59299 TEST=test cr50 TPM with 20us pulse to ensure it can successfully communicate with the TPM and does not get confused due to seeing interrupts that it should not. Change-Id: I384f484a1728038d3a355586146deee089b22dd9 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/17212 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-11-03 18:33:43 +01:00
#include <timer.h>
vboot: Separate vboot from chromeos VBOOT_VERIFY_FIRMWARE should be independent of CHROMEOS. This allows use of verified boot library without having to stick to CHROMEOS. BUG=chrome-os-partner:55639 Change-Id: Ia2c328712caedd230ab295b8a613e3c1ed1532d9 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/15867 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-07-25 20:48:03 +02:00
#include <vboot/vboot_common.h>
soc/intel/apollolake: Initialize GPEs in bootblock Initialize the GPEs from mainboard config in bootblock, so they can be used in verstage to query latched interrupt status. I still left it called in ramstage just to be sure that the configuration was not overwritten in FSP stages. Tested by reading and reporting GPE status in a loop in verstage and manually triggering an interrupt on EC console. BUG=chrome-os-partner:53336 Change-Id: Iacd0483e4b3229aca602bb5bb40586eedf35a6ea Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/16670 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-19 21:02:54 +02:00
#include "chip.h"
soc/apollolake: Add helper functions to access Power Management Registers Change-Id: I928efea33030e03cbbaead6812c617d20446f7c9 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/14289 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-02-05 05:13:34 +01:00
soc/apollolake/pmutil: Get PMC base address dynamically Instead of using a hardcoded address for PMC device BAR0, read it dynamically. This allows the allocator to move the BAR without needing a fixed resource. Note that we cannot do the same for the ACPI BAR (index 0x20), as it cannot be read back. Change-Id: If43e1ccb693ffb17b78bdd76140a0849493a0010 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com> Reviewed-on: https://review.coreboot.org/14633 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-04-05 21:40:24 +02:00
static uintptr_t read_pmc_mmio_bar(void)
{
soc/intel/apollolake: Use fixed resource for SRAM and IPC1 Intel telemetry support will require PMC IPC1 and SRAM devices to be operated in ACPI mode. Then using fixed resources on BAR0, BAR1 and BAR2 (PMC only) for those two devices will help the resource assignment in DSDT stage. BUG=chrome-os-partner:57364 BRANCH=None TEST=Boot up into Chrome OS successfully and check with dmesg to see the driver has been loaded successfully without errors. Change-Id: I8f0983a90728b9148a124ae3443ec29cd7b344ce Signed-off-by: Zhao, Lijian <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/16648 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-07 03:15:29 +02:00
return PMC_BAR0;
soc/apollolake/pmutil: Get PMC base address dynamically Instead of using a hardcoded address for PMC device BAR0, read it dynamically. This allows the allocator to move the BAR without needing a fixed resource. Note that we cannot do the same for the ACPI BAR (index 0x20), as it cannot be read back. Change-Id: If43e1ccb693ffb17b78bdd76140a0849493a0010 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com> Reviewed-on: https://review.coreboot.org/14633 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-04-05 21:40:24 +02:00
}
soc/apollolake: Add helper functions to access Power Management Registers Change-Id: I928efea33030e03cbbaead6812c617d20446f7c9 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/14289 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-02-05 05:13:34 +01:00
soc/apollolake: Expose a function to read pmc bar This patch exposes a function to read pmc bar. PMC bar is read in function read_pmc_mmio_bar which is defined static in file pmutil.c. This patch exposes that functionality to call it from other files. BUG=chrome-os-partner:53438 TEST= Read the PMC bar value properly from outside pmutil file. Change-Id: I26ee13e6ab95d3a8991c7f8ea4b3856ceb015d10 Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/15460 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-28 08:00:15 +02:00
uintptr_t get_pmc_mmio_bar(void)
{
return read_pmc_mmio_bar();
}
soc/apollolake: Add helper functions to access Power Management Registers Change-Id: I928efea33030e03cbbaead6812c617d20446f7c9 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/14289 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-02-05 05:13:34 +01:00
static void print_num_status_bits(int num_bits, uint32_t status,
const char * const bit_names[])
{
int i;
if (!status)
return;
for (i = num_bits - 1; i >= 0; i--) {
if (status & (1 << i)) {
if (bit_names[i])
printk(BIOS_DEBUG, "%s ", bit_names[i]);
else
printk(BIOS_DEBUG, "BIT%d ", i);
}
}
}
static uint32_t print_smi_status(uint32_t smi_sts)
{
static const char * const smi_sts_bits[] = {
soc/intel/apollolake: add SMI status bit definitons and use them Provide the bit definitions for the SMI status register. Also, utilize them which means deleting some of the handlers that can't exist because there are no status bits. BUG=chrome-os-partner:54262 Change-Id: I389c7cb3cad01ba0eca52a337ffee352a2010bfa Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15154 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
2016-06-11 01:01:45 +02:00
[BIOS_SMI_STS] = "BIOS",
[LEGACY_USB_SMI_STS] = "LEGACY USB",
[SLP_SMI_STS] = "SLP_SMI",
[APM_SMI_STS] = "APM",
[SWSMI_TMR_SMI_STS] = "SWSMI_TMR",
soc/intel/apollolake: provide fake PM1 SMI status bit It appears that PM1 is not wired up to the SMI status register, but it does definitely cause SMIs to trigger. Therefore, provide a fake PM1 status bit by checking the power button status when SMI status is indicating no status as well as the PM1 control indicating that SCI mode is not enabled. BUG=chrome-os-partner:54262 TEST=Smashed power button on reef to cause SMI in firmware. No longer loops infinitely with constant SMIs firing. Change-Id: I9aa1b5f79b651cbc19a2d3353d9ef65429386889 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15155 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-11 01:04:21 +02:00
[FAKE_PM1_SMI_STS] = "PM1",
soc/intel/apollolake: Fix spacing around operators and commas Fix the following errors detected by checkpatch.pl: ERROR: spaces required around that '==' (ctx:VxO) ERROR: space required before that '-' (ctx:OxV) ERROR: spaces required around that '=' (ctx:VxW) ERROR: spaces required around that '=' (ctx:WxV) ERROR: spaces required around that '=' (ctx:VxV) ERROR: need consistent spacing around '+' (ctx:VxW) ERROR: space prohibited before that '++' (ctx:WxB) ERROR: space prohibited before that ',' (ctx:WxW) ERROR: space required after that ',' (ctx:VxV) TEST=Build for reef Change-Id: I37265a69fcb14fbf7c182ef29d823f70a5748ad8 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/18720 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-09 18:42:48 +01:00
[GPIO_SMI_STS] = "GPIO_SMI",
[GPIO_UNLOCK_SMI_STS] = "GPIO_UNLOCK_SSMI",
soc/intel/apollolake: add SMI status bit definitons and use them Provide the bit definitions for the SMI status register. Also, utilize them which means deleting some of the handlers that can't exist because there are no status bits. BUG=chrome-os-partner:54262 Change-Id: I389c7cb3cad01ba0eca52a337ffee352a2010bfa Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15154 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
2016-06-11 01:01:45 +02:00
[MC_SMI_STS] = "MCSMI",
[TCO_SMI_STS] = "TCO",
[PERIODIC_SMI_STS] = "PERIODIC",
[SERIRQ_SMI_STS] = "SERIRQ",
[SMBUS_SMI_STS] = "SMBUS_SMI",
[XHCI_SMI_STS] = "XHCI",
[HSMBUS_SMI_STS] = "HOST_SMBUS",
[SCS_SMI_STS] = "SCS",
[PCIE_SMI_STS] = "PCI_EXP_SMI",
[SCC2_SMI_STS] = "SCC2",
[SPI_SSMI_STS] = "SPI_SSMI",
[SPI_SMI_STS] = "SPI",
[PMC_OCP_SMI_STS] = "OCP_CSE",
soc/apollolake: Add helper functions to access Power Management Registers Change-Id: I928efea33030e03cbbaead6812c617d20446f7c9 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/14289 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-02-05 05:13:34 +01:00
};
if (!smi_sts)
return 0;
printk(BIOS_DEBUG, "SMI_STS: ");
print_num_status_bits(ARRAY_SIZE(smi_sts_bits), smi_sts, smi_sts_bits);
printk(BIOS_DEBUG, "\n");
return smi_sts;
}
static uint32_t reset_smi_status(void)
{
soc/intel/apollolake: Rename ACPI Base Address and Size Macro Rename these two Macros to help use Common Code - ACPI_PMIO_BASE --> ACPI_BASE_ADDRESS ACPI_PMIO_SIZE --> ACPI_BASE_SIZE Change-Id: I21125b7206c241692cfdf1cdb10b8b3dee62b24a Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/20038 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-06-05 16:31:14 +02:00
uint32_t smi_sts = inl(ACPI_BASE_ADDRESS + SMI_STS);
outl(smi_sts, ACPI_BASE_ADDRESS + SMI_STS);
soc/apollolake: Add helper functions to access Power Management Registers Change-Id: I928efea33030e03cbbaead6812c617d20446f7c9 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/14289 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-02-05 05:13:34 +01:00
return smi_sts;
}
uint32_t clear_smi_status(void)
{
soc/intel/apollolake: provide fake PM1 SMI status bit It appears that PM1 is not wired up to the SMI status register, but it does definitely cause SMIs to trigger. Therefore, provide a fake PM1 status bit by checking the power button status when SMI status is indicating no status as well as the PM1 control indicating that SCI mode is not enabled. BUG=chrome-os-partner:54262 TEST=Smashed power button on reef to cause SMI in firmware. No longer loops infinitely with constant SMIs firing. Change-Id: I9aa1b5f79b651cbc19a2d3353d9ef65429386889 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15155 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-11 01:04:21 +02:00
uint32_t sts = reset_smi_status();
/*
* Check for power button status if nothing else is indicating an SMI
* and SMIs aren't turned into SCIs. Apparently, there is no PM1 status
* bit in the SMI status register. That makes things difficult for
* determining if the power button caused an SMI.
*/
soc/intel/apollolake: Rename ACPI Base Address and Size Macro Rename these two Macros to help use Common Code - ACPI_PMIO_BASE --> ACPI_BASE_ADDRESS ACPI_PMIO_SIZE --> ACPI_BASE_SIZE Change-Id: I21125b7206c241692cfdf1cdb10b8b3dee62b24a Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/20038 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-06-05 16:31:14 +02:00
if (sts == 0 && !(inl(ACPI_BASE_ADDRESS + PM1_CNT) & SCI_EN)) {
uint16_t pm1_sts = inw(ACPI_BASE_ADDRESS + PM1_STS);
soc/intel/apollolake: provide fake PM1 SMI status bit It appears that PM1 is not wired up to the SMI status register, but it does definitely cause SMIs to trigger. Therefore, provide a fake PM1 status bit by checking the power button status when SMI status is indicating no status as well as the PM1 control indicating that SCI mode is not enabled. BUG=chrome-os-partner:54262 TEST=Smashed power button on reef to cause SMI in firmware. No longer loops infinitely with constant SMIs firing. Change-Id: I9aa1b5f79b651cbc19a2d3353d9ef65429386889 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15155 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-11 01:04:21 +02:00
/* Fake PM1 status bit if power button pressed. */
if (pm1_sts & PWRBTN_STS)
sts |= (1 << FAKE_PM1_SMI_STS);
}
return print_smi_status(sts);
soc/apollolake: Add helper functions to access Power Management Registers Change-Id: I928efea33030e03cbbaead6812c617d20446f7c9 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/14289 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-02-05 05:13:34 +01:00
}
uint32_t get_smi_en(void)
{
soc/intel/apollolake: Rename ACPI Base Address and Size Macro Rename these two Macros to help use Common Code - ACPI_PMIO_BASE --> ACPI_BASE_ADDRESS ACPI_PMIO_SIZE --> ACPI_BASE_SIZE Change-Id: I21125b7206c241692cfdf1cdb10b8b3dee62b24a Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/20038 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-06-05 16:31:14 +02:00
return inl(ACPI_BASE_ADDRESS + SMI_EN);
soc/apollolake: Add helper functions to access Power Management Registers Change-Id: I928efea33030e03cbbaead6812c617d20446f7c9 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/14289 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-02-05 05:13:34 +01:00
}
void enable_smi(uint32_t mask)
{
soc/intel/apollolake: Rename ACPI Base Address and Size Macro Rename these two Macros to help use Common Code - ACPI_PMIO_BASE --> ACPI_BASE_ADDRESS ACPI_PMIO_SIZE --> ACPI_BASE_SIZE Change-Id: I21125b7206c241692cfdf1cdb10b8b3dee62b24a Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/20038 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-06-05 16:31:14 +02:00
uint32_t smi_en = inl(ACPI_BASE_ADDRESS + SMI_EN);
soc/apollolake: Add helper functions to access Power Management Registers Change-Id: I928efea33030e03cbbaead6812c617d20446f7c9 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/14289 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-02-05 05:13:34 +01:00
smi_en |= mask;
soc/intel/apollolake: Rename ACPI Base Address and Size Macro Rename these two Macros to help use Common Code - ACPI_PMIO_BASE --> ACPI_BASE_ADDRESS ACPI_PMIO_SIZE --> ACPI_BASE_SIZE Change-Id: I21125b7206c241692cfdf1cdb10b8b3dee62b24a Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/20038 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-06-05 16:31:14 +02:00
outl(smi_en, ACPI_BASE_ADDRESS + SMI_EN);
soc/apollolake: Add helper functions to access Power Management Registers Change-Id: I928efea33030e03cbbaead6812c617d20446f7c9 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/14289 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-02-05 05:13:34 +01:00
}
void disable_smi(uint32_t mask)
{
soc/intel/apollolake: Rename ACPI Base Address and Size Macro Rename these two Macros to help use Common Code - ACPI_PMIO_BASE --> ACPI_BASE_ADDRESS ACPI_PMIO_SIZE --> ACPI_BASE_SIZE Change-Id: I21125b7206c241692cfdf1cdb10b8b3dee62b24a Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/20038 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-06-05 16:31:14 +02:00
uint32_t smi_en = inl(ACPI_BASE_ADDRESS + SMI_EN);
soc/apollolake: Add helper functions to access Power Management Registers Change-Id: I928efea33030e03cbbaead6812c617d20446f7c9 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/14289 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-02-05 05:13:34 +01:00
smi_en &= ~mask;
soc/intel/apollolake: Rename ACPI Base Address and Size Macro Rename these two Macros to help use Common Code - ACPI_PMIO_BASE --> ACPI_BASE_ADDRESS ACPI_PMIO_SIZE --> ACPI_BASE_SIZE Change-Id: I21125b7206c241692cfdf1cdb10b8b3dee62b24a Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/20038 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-06-05 16:31:14 +02:00
outl(smi_en, ACPI_BASE_ADDRESS + SMI_EN);
soc/apollolake: Add helper functions to access Power Management Registers Change-Id: I928efea33030e03cbbaead6812c617d20446f7c9 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/14289 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-02-05 05:13:34 +01:00
}
void enable_pm1_control(uint32_t mask)
{
soc/intel/apollolake: Rename ACPI Base Address and Size Macro Rename these two Macros to help use Common Code - ACPI_PMIO_BASE --> ACPI_BASE_ADDRESS ACPI_PMIO_SIZE --> ACPI_BASE_SIZE Change-Id: I21125b7206c241692cfdf1cdb10b8b3dee62b24a Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/20038 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-06-05 16:31:14 +02:00
uint32_t pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT);
soc/apollolake: Add helper functions to access Power Management Registers Change-Id: I928efea33030e03cbbaead6812c617d20446f7c9 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/14289 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-02-05 05:13:34 +01:00
pm1_cnt |= mask;
soc/intel/apollolake: Rename ACPI Base Address and Size Macro Rename these two Macros to help use Common Code - ACPI_PMIO_BASE --> ACPI_BASE_ADDRESS ACPI_PMIO_SIZE --> ACPI_BASE_SIZE Change-Id: I21125b7206c241692cfdf1cdb10b8b3dee62b24a Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/20038 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-06-05 16:31:14 +02:00
outl(pm1_cnt, ACPI_BASE_ADDRESS + PM1_CNT);
soc/apollolake: Add helper functions to access Power Management Registers Change-Id: I928efea33030e03cbbaead6812c617d20446f7c9 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/14289 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-02-05 05:13:34 +01:00
}
void disable_pm1_control(uint32_t mask)
{
soc/intel/apollolake: Rename ACPI Base Address and Size Macro Rename these two Macros to help use Common Code - ACPI_PMIO_BASE --> ACPI_BASE_ADDRESS ACPI_PMIO_SIZE --> ACPI_BASE_SIZE Change-Id: I21125b7206c241692cfdf1cdb10b8b3dee62b24a Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/20038 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-06-05 16:31:14 +02:00
uint32_t pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT);
soc/apollolake: Add helper functions to access Power Management Registers Change-Id: I928efea33030e03cbbaead6812c617d20446f7c9 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/14289 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-02-05 05:13:34 +01:00
pm1_cnt &= ~mask;
soc/intel/apollolake: Rename ACPI Base Address and Size Macro Rename these two Macros to help use Common Code - ACPI_PMIO_BASE --> ACPI_BASE_ADDRESS ACPI_PMIO_SIZE --> ACPI_BASE_SIZE Change-Id: I21125b7206c241692cfdf1cdb10b8b3dee62b24a Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/20038 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-06-05 16:31:14 +02:00
outl(pm1_cnt, ACPI_BASE_ADDRESS + PM1_CNT);
soc/apollolake: Add helper functions to access Power Management Registers Change-Id: I928efea33030e03cbbaead6812c617d20446f7c9 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/14289 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-02-05 05:13:34 +01:00
}
static uint16_t reset_pm1_status(void)
{
soc/intel/apollolake: Rename ACPI Base Address and Size Macro Rename these two Macros to help use Common Code - ACPI_PMIO_BASE --> ACPI_BASE_ADDRESS ACPI_PMIO_SIZE --> ACPI_BASE_SIZE Change-Id: I21125b7206c241692cfdf1cdb10b8b3dee62b24a Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/20038 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-06-05 16:31:14 +02:00
uint16_t pm1_sts = inw(ACPI_BASE_ADDRESS + PM1_STS);
outw(pm1_sts, ACPI_BASE_ADDRESS + PM1_STS);
soc/apollolake: Add helper functions to access Power Management Registers Change-Id: I928efea33030e03cbbaead6812c617d20446f7c9 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/14289 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-02-05 05:13:34 +01:00
return pm1_sts;
}
static uint16_t print_pm1_status(uint16_t pm1_sts)
{
static const char * const pm1_sts_bits[] = {
[0] = "TMROF",
[5] = "GBL",
[8] = "PWRBTN",
[10] = "RTC",
[11] = "PRBTNOR",
[13] = "USB",
[14] = "PCIEXPWAK",
[15] = "WAK",
};
if (!pm1_sts)
return 0;
printk(BIOS_SPEW, "PM1_STS: ");
print_num_status_bits(ARRAY_SIZE(pm1_sts_bits), pm1_sts, pm1_sts_bits);
printk(BIOS_SPEW, "\n");
return pm1_sts;
}
uint16_t clear_pm1_status(void)
{
return print_pm1_status(reset_pm1_status());
}
void enable_pm1(uint16_t events)
{
soc/intel/apollolake: Rename ACPI Base Address and Size Macro Rename these two Macros to help use Common Code - ACPI_PMIO_BASE --> ACPI_BASE_ADDRESS ACPI_PMIO_SIZE --> ACPI_BASE_SIZE Change-Id: I21125b7206c241692cfdf1cdb10b8b3dee62b24a Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/20038 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-06-05 16:31:14 +02:00
outw(events, ACPI_BASE_ADDRESS + PM1_EN);
soc/apollolake: Add helper functions to access Power Management Registers Change-Id: I928efea33030e03cbbaead6812c617d20446f7c9 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/14289 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-02-05 05:13:34 +01:00
}
static uint32_t print_tco_status(uint32_t tco_sts)
{
static const char * const tco_sts_bits[] = {
[3] = "TIMEOUT",
[17] = "SECOND_TO",
};
if (!tco_sts)
return 0;
printk(BIOS_DEBUG, "TCO_STS: ");
print_num_status_bits(ARRAY_SIZE(tco_sts_bits), tco_sts, tco_sts_bits);
printk(BIOS_DEBUG, "\n");
return tco_sts;
}
static uint32_t reset_tco_status(void)
{
soc/intel/apollolake: Rename ACPI Base Address and Size Macro Rename these two Macros to help use Common Code - ACPI_PMIO_BASE --> ACPI_BASE_ADDRESS ACPI_PMIO_SIZE --> ACPI_BASE_SIZE Change-Id: I21125b7206c241692cfdf1cdb10b8b3dee62b24a Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/20038 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-06-05 16:31:14 +02:00
uint32_t tco_sts = inl(ACPI_BASE_ADDRESS + TCO_STS);
uint32_t tco_en = inl(ACPI_BASE_ADDRESS + TCO1_CNT);
soc/apollolake: Add helper functions to access Power Management Registers Change-Id: I928efea33030e03cbbaead6812c617d20446f7c9 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/14289 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-02-05 05:13:34 +01:00
soc/intel/apollolake: Rename ACPI Base Address and Size Macro Rename these two Macros to help use Common Code - ACPI_PMIO_BASE --> ACPI_BASE_ADDRESS ACPI_PMIO_SIZE --> ACPI_BASE_SIZE Change-Id: I21125b7206c241692cfdf1cdb10b8b3dee62b24a Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/20038 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-06-05 16:31:14 +02:00
outl(tco_sts, ACPI_BASE_ADDRESS + TCO_STS);
soc/apollolake: Add helper functions to access Power Management Registers Change-Id: I928efea33030e03cbbaead6812c617d20446f7c9 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/14289 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-02-05 05:13:34 +01:00
return tco_sts & tco_en;
}
uint32_t clear_tco_status(void)
{
return print_tco_status(reset_tco_status());
}
void enable_gpe(uint32_t mask)
{
soc/intel/apollolake: Rename ACPI Base Address and Size Macro Rename these two Macros to help use Common Code - ACPI_PMIO_BASE --> ACPI_BASE_ADDRESS ACPI_PMIO_SIZE --> ACPI_BASE_SIZE Change-Id: I21125b7206c241692cfdf1cdb10b8b3dee62b24a Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/20038 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-06-05 16:31:14 +02:00
uint32_t gpe0a_en = inl(ACPI_BASE_ADDRESS + GPE0_EN(0));
soc/apollolake: Add helper functions to access Power Management Registers Change-Id: I928efea33030e03cbbaead6812c617d20446f7c9 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/14289 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-02-05 05:13:34 +01:00
gpe0a_en |= mask;
soc/intel/apollolake: Rename ACPI Base Address and Size Macro Rename these two Macros to help use Common Code - ACPI_PMIO_BASE --> ACPI_BASE_ADDRESS ACPI_PMIO_SIZE --> ACPI_BASE_SIZE Change-Id: I21125b7206c241692cfdf1cdb10b8b3dee62b24a Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/20038 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-06-05 16:31:14 +02:00
outl(gpe0a_en, ACPI_BASE_ADDRESS + GPE0_EN(0));
soc/apollolake: Add helper functions to access Power Management Registers Change-Id: I928efea33030e03cbbaead6812c617d20446f7c9 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/14289 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-02-05 05:13:34 +01:00
}
void disable_gpe(uint32_t mask)
{
soc/intel/apollolake: Rename ACPI Base Address and Size Macro Rename these two Macros to help use Common Code - ACPI_PMIO_BASE --> ACPI_BASE_ADDRESS ACPI_PMIO_SIZE --> ACPI_BASE_SIZE Change-Id: I21125b7206c241692cfdf1cdb10b8b3dee62b24a Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/20038 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-06-05 16:31:14 +02:00
uint32_t gpe0a_en = inl(ACPI_BASE_ADDRESS + GPE0_EN(0));
soc/apollolake: Add helper functions to access Power Management Registers Change-Id: I928efea33030e03cbbaead6812c617d20446f7c9 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/14289 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-02-05 05:13:34 +01:00
gpe0a_en &= ~mask;
soc/intel/apollolake: Rename ACPI Base Address and Size Macro Rename these two Macros to help use Common Code - ACPI_PMIO_BASE --> ACPI_BASE_ADDRESS ACPI_PMIO_SIZE --> ACPI_BASE_SIZE Change-Id: I21125b7206c241692cfdf1cdb10b8b3dee62b24a Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/20038 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-06-05 16:31:14 +02:00
outl(gpe0a_en, ACPI_BASE_ADDRESS + GPE0_EN(0));
soc/apollolake: Add helper functions to access Power Management Registers Change-Id: I928efea33030e03cbbaead6812c617d20446f7c9 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/14289 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-02-05 05:13:34 +01:00
}
void disable_all_gpe(void)
{
disable_gpe(~0);
}
intel/apollolake: Add power management utility function This patch adds a power management utility function to clear wake status bits in ACPI GPE0 registers. We need to call this function before going to sleep from common smi handler function. BUG=chrome-os-partner:55583 BRANCH=None TEST=Verified that system goes to sleep on lidclose and powerd_dbus_suspend command issued from built-in keyboard. Change-Id: Icd095d377c82f2e154f2e2db773f737aa49cda64 Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/16298 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-23 06:55:23 +02:00
/* Clear the gpio gpe0 status bits in ACPI registers */
void clear_gpi_gpe_sts(void)
{
int i;
for (i = 1; i < GPE0_REG_MAX; i++) {
soc/intel/apollolake: Rename ACPI Base Address and Size Macro Rename these two Macros to help use Common Code - ACPI_PMIO_BASE --> ACPI_BASE_ADDRESS ACPI_PMIO_SIZE --> ACPI_BASE_SIZE Change-Id: I21125b7206c241692cfdf1cdb10b8b3dee62b24a Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/20038 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-06-05 16:31:14 +02:00
uint32_t gpe_sts = inl(ACPI_BASE_ADDRESS + GPE0_STS(i));
outl(gpe_sts, ACPI_BASE_ADDRESS + GPE0_STS(i));
intel/apollolake: Add power management utility function This patch adds a power management utility function to clear wake status bits in ACPI GPE0 registers. We need to call this function before going to sleep from common smi handler function. BUG=chrome-os-partner:55583 BRANCH=None TEST=Verified that system goes to sleep on lidclose and powerd_dbus_suspend command issued from built-in keyboard. Change-Id: Icd095d377c82f2e154f2e2db773f737aa49cda64 Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/16298 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-23 06:55:23 +02:00
}
}
soc/apollolake: Add helper functions to access Power Management Registers Change-Id: I928efea33030e03cbbaead6812c617d20446f7c9 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/14289 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-02-05 05:13:34 +01:00
static uint32_t reset_gpe_status(void)
{
soc/intel/apollolake: Rename ACPI Base Address and Size Macro Rename these two Macros to help use Common Code - ACPI_PMIO_BASE --> ACPI_BASE_ADDRESS ACPI_PMIO_SIZE --> ACPI_BASE_SIZE Change-Id: I21125b7206c241692cfdf1cdb10b8b3dee62b24a Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/20038 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-06-05 16:31:14 +02:00
uint32_t gpe_sts = inl(ACPI_BASE_ADDRESS + GPE0_STS(0));
outl(gpe_sts, ACPI_BASE_ADDRESS + GPE0_STS(0));
soc/apollolake: Add helper functions to access Power Management Registers Change-Id: I928efea33030e03cbbaead6812c617d20446f7c9 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/14289 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-02-05 05:13:34 +01:00
return gpe_sts;
}
static uint32_t print_gpe_sts(uint32_t gpe_sts)
{
static const char * const gpe_sts_bits[] = {
[0] = "PCIE_SCI",
[2] = "SWGPE",
[3] = "PCIE_WAKE0",
[4] = "PUNIT",
[6] = "PCIE_WAKE1",
[7] = "PCIE_WAKE2",
[8] = "PCIE_WAKE3",
[9] = "PCI_EXP",
[10] = "BATLOW",
[11] = "CSE_PME",
[12] = "XDCI_PME",
[13] = "XHCI_PME",
[14] = "AVS_PME",
[15] = "GPIO_TIER1_SCI",
[16] = "SMB_WAK",
[17] = "SATA_PME",
};
if (!gpe_sts)
return gpe_sts;
printk(BIOS_DEBUG, "GPE0a_STS: ");
print_num_status_bits(ARRAY_SIZE(gpe_sts_bits), gpe_sts, gpe_sts_bits);
printk(BIOS_DEBUG, "\n");
return gpe_sts;
}
uint32_t clear_gpe_status(void)
{
return print_gpe_sts(reset_gpe_status());
}
soc/intel/apollolake: Add function to read and clear GPE status Implement the generic acpi_get_gpe() function to read and clear the GPE status for a specific GPE. Tested by watching GPE status in a loop while generating interrupts manually from the EC console. BUG=chrome-os-partner:53336 Change-Id: I482ff52051a48441333b573f1cd0fa7f7579a6ab Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/16671 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-19 21:05:49 +02:00
/* Read and clear GPE status (defined in arch/acpi.h) */
int acpi_get_gpe(int gpe)
{
int bank;
uint32_t mask, sts;
soc/intel/{sky,apollo}lake: Wait until GPE is clear when reading When reading+clearing a GPE for use as an interrupt we need to re-read the status register and keep setting the clear bit until it actually reads back clear. Also add a 1ms timeout in case the status never clears. This is needed if a device sends a longer interrupt pulse and it is still asserted when the "ISR" goes to clear the status. BUG=chrome-os-partner:59299 TEST=test cr50 TPM with 20us pulse to ensure it can successfully communicate with the TPM and does not get confused due to seeing interrupts that it should not. Change-Id: I384f484a1728038d3a355586146deee089b22dd9 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/17212 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-11-03 18:33:43 +01:00
struct stopwatch sw;
int rc = 0;
soc/intel/apollolake: Add function to read and clear GPE status Implement the generic acpi_get_gpe() function to read and clear the GPE status for a specific GPE. Tested by watching GPE status in a loop while generating interrupts manually from the EC console. BUG=chrome-os-partner:53336 Change-Id: I482ff52051a48441333b573f1cd0fa7f7579a6ab Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/16671 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-19 21:05:49 +02:00
if (gpe < 0 || gpe > GPE0_DW3_31)
return -1;
bank = gpe / 32;
mask = 1 << (gpe % 32);
soc/intel/{sky,apollo}lake: Wait until GPE is clear when reading When reading+clearing a GPE for use as an interrupt we need to re-read the status register and keep setting the clear bit until it actually reads back clear. Also add a 1ms timeout in case the status never clears. This is needed if a device sends a longer interrupt pulse and it is still asserted when the "ISR" goes to clear the status. BUG=chrome-os-partner:59299 TEST=test cr50 TPM with 20us pulse to ensure it can successfully communicate with the TPM and does not get confused due to seeing interrupts that it should not. Change-Id: I384f484a1728038d3a355586146deee089b22dd9 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/17212 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-11-03 18:33:43 +01:00
/* Wait up to 1ms for GPE status to clear */
stopwatch_init_msecs_expire(&sw, 1);
do {
if (stopwatch_expired(&sw))
return rc;
soc/intel/apollolake: Rename ACPI Base Address and Size Macro Rename these two Macros to help use Common Code - ACPI_PMIO_BASE --> ACPI_BASE_ADDRESS ACPI_PMIO_SIZE --> ACPI_BASE_SIZE Change-Id: I21125b7206c241692cfdf1cdb10b8b3dee62b24a Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/20038 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-06-05 16:31:14 +02:00
sts = inl(ACPI_BASE_ADDRESS + GPE0_STS(bank));
soc/intel/{sky,apollo}lake: Wait until GPE is clear when reading When reading+clearing a GPE for use as an interrupt we need to re-read the status register and keep setting the clear bit until it actually reads back clear. Also add a 1ms timeout in case the status never clears. This is needed if a device sends a longer interrupt pulse and it is still asserted when the "ISR" goes to clear the status. BUG=chrome-os-partner:59299 TEST=test cr50 TPM with 20us pulse to ensure it can successfully communicate with the TPM and does not get confused due to seeing interrupts that it should not. Change-Id: I384f484a1728038d3a355586146deee089b22dd9 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/17212 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-11-03 18:33:43 +01:00
if (sts & mask) {
soc/intel/apollolake: Rename ACPI Base Address and Size Macro Rename these two Macros to help use Common Code - ACPI_PMIO_BASE --> ACPI_BASE_ADDRESS ACPI_PMIO_SIZE --> ACPI_BASE_SIZE Change-Id: I21125b7206c241692cfdf1cdb10b8b3dee62b24a Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/20038 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-06-05 16:31:14 +02:00
outl(mask, ACPI_BASE_ADDRESS + GPE0_STS(bank));
soc/intel/{sky,apollo}lake: Wait until GPE is clear when reading When reading+clearing a GPE for use as an interrupt we need to re-read the status register and keep setting the clear bit until it actually reads back clear. Also add a 1ms timeout in case the status never clears. This is needed if a device sends a longer interrupt pulse and it is still asserted when the "ISR" goes to clear the status. BUG=chrome-os-partner:59299 TEST=test cr50 TPM with 20us pulse to ensure it can successfully communicate with the TPM and does not get confused due to seeing interrupts that it should not. Change-Id: I384f484a1728038d3a355586146deee089b22dd9 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/17212 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-11-03 18:33:43 +01:00
rc = 1;
}
} while (sts & mask);
return rc;
soc/intel/apollolake: Add function to read and clear GPE status Implement the generic acpi_get_gpe() function to read and clear the GPE status for a specific GPE. Tested by watching GPE status in a loop while generating interrupts manually from the EC console. BUG=chrome-os-partner:53336 Change-Id: I482ff52051a48441333b573f1cd0fa7f7579a6ab Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/16671 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-19 21:05:49 +02:00
}
soc/apollolake: Add helper functions to access Power Management Registers Change-Id: I928efea33030e03cbbaead6812c617d20446f7c9 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/14289 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-02-05 05:13:34 +01:00
void clear_pmc_status(void)
{
uint32_t prsts;
uint32_t gen_pmcon1;
soc/apollolake/pmutil: Get PMC base address dynamically Instead of using a hardcoded address for PMC device BAR0, read it dynamically. This allows the allocator to move the BAR without needing a fixed resource. Note that we cannot do the same for the ACPI BAR (index 0x20), as it cannot be read back. Change-Id: If43e1ccb693ffb17b78bdd76140a0849493a0010 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com> Reviewed-on: https://review.coreboot.org/14633 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-04-05 21:40:24 +02:00
uintptr_t pmc_bar0 = read_pmc_mmio_bar();
soc/apollolake: Add helper functions to access Power Management Registers Change-Id: I928efea33030e03cbbaead6812c617d20446f7c9 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/14289 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-02-05 05:13:34 +01:00
soc/apollolake/pmutil: Get PMC base address dynamically Instead of using a hardcoded address for PMC device BAR0, read it dynamically. This allows the allocator to move the BAR without needing a fixed resource. Note that we cannot do the same for the ACPI BAR (index 0x20), as it cannot be read back. Change-Id: If43e1ccb693ffb17b78bdd76140a0849493a0010 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com> Reviewed-on: https://review.coreboot.org/14633 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-04-05 21:40:24 +02:00
prsts = read32((void *)(pmc_bar0 + PRSTS));
gen_pmcon1 = read32((void *)(pmc_bar0 + GEN_PMCON1));
soc/apollolake: Add helper functions to access Power Management Registers Change-Id: I928efea33030e03cbbaead6812c617d20446f7c9 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/14289 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-02-05 05:13:34 +01:00
/* Clear the status bits. The RPS field is cleared on a 0 write. */
soc/apollolake/pmutil: Get PMC base address dynamically Instead of using a hardcoded address for PMC device BAR0, read it dynamically. This allows the allocator to move the BAR without needing a fixed resource. Note that we cannot do the same for the ACPI BAR (index 0x20), as it cannot be read back. Change-Id: If43e1ccb693ffb17b78bdd76140a0849493a0010 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com> Reviewed-on: https://review.coreboot.org/14633 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-04-05 21:40:24 +02:00
write32((void *)(pmc_bar0 + GEN_PMCON1), gen_pmcon1 & ~RPS);
write32((void *)(pmc_bar0 + PRSTS), prsts);
soc/apollolake: Add helper functions to access Power Management Registers Change-Id: I928efea33030e03cbbaead6812c617d20446f7c9 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/14289 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-02-05 05:13:34 +01:00
}
/* Return 0, 3, or 5 to indicate the previous sleep state. */
int chipset_prev_sleep_state(struct chipset_power_state *ps)
{
/* Default to S0. */
soc/intel/apollolake: use common Intel ACPI hardware definitions Transition to using the common Intel ACPI hardware definitions generic ACPI definitions. BUG=chrome-os-partner:54977 Change-Id: Icaca9367b526999f0475b21dd968724baa32e3f6 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15667 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-07-14 06:17:38 +02:00
int prev_sleep_state = ACPI_S0;
soc/apollolake: Add helper functions to access Power Management Registers Change-Id: I928efea33030e03cbbaead6812c617d20446f7c9 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/14289 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-02-05 05:13:34 +01:00
if (ps->pm1_sts & WAK_STS) {
soc/intel/apollolake: use common Intel ACPI hardware definitions Transition to using the common Intel ACPI hardware definitions generic ACPI definitions. BUG=chrome-os-partner:54977 Change-Id: Icaca9367b526999f0475b21dd968724baa32e3f6 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15667 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-07-14 06:17:38 +02:00
switch (acpi_sleep_from_pm1(ps->pm1_cnt)) {
case ACPI_S3:
if (IS_ENABLED(CONFIG_HAVE_ACPI_RESUME))
prev_sleep_state = ACPI_S3;
soc/apollolake: Add helper functions to access Power Management Registers Change-Id: I928efea33030e03cbbaead6812c617d20446f7c9 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/14289 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-02-05 05:13:34 +01:00
break;
soc/intel/apollolake: use common Intel ACPI hardware definitions Transition to using the common Intel ACPI hardware definitions generic ACPI definitions. BUG=chrome-os-partner:54977 Change-Id: Icaca9367b526999f0475b21dd968724baa32e3f6 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15667 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-07-14 06:17:38 +02:00
case ACPI_S5:
prev_sleep_state = ACPI_S5;
soc/apollolake: Add helper functions to access Power Management Registers Change-Id: I928efea33030e03cbbaead6812c617d20446f7c9 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/14289 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-02-05 05:13:34 +01:00
break;
}
soc/apollolake: Clear SLP_TYP in PM1_CNT Change-Id: Id49319ec6b52648b03eaeddfdd1580dd82110fb9 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/15336 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-23 18:50:28 +02:00
/* Clear SLP_TYP. */
soc/intel/apollolake: Rename ACPI Base Address and Size Macro Rename these two Macros to help use Common Code - ACPI_PMIO_BASE --> ACPI_BASE_ADDRESS ACPI_PMIO_SIZE --> ACPI_BASE_SIZE Change-Id: I21125b7206c241692cfdf1cdb10b8b3dee62b24a Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/20038 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-06-05 16:31:14 +02:00
outl(ps->pm1_cnt & ~(SLP_TYP), ACPI_BASE_ADDRESS + PM1_CNT);
soc/apollolake: Add helper functions to access Power Management Registers Change-Id: I928efea33030e03cbbaead6812c617d20446f7c9 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/14289 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-02-05 05:13:34 +01:00
}
return prev_sleep_state;
}
soc/apollolake: Return correct wake status in _SWS Wake status is calculated from the four pairs of gpe0 in cbmem CBMEM_ID_POWER_STATE which is filled very early in romstage and depends on the routing information in PMC GPE_CFG register. Coreboot sets the proper value of routing based on devicetree from pmc_init. But when system goes to S3 on waking up PMC is writing default values again in GPE_CFG which results in returning wrong wake status in _SWS. This patch corrects that behaviour by correcting the gpe0 pairs in cbmem after PMC sets the routing table in resume path. BUG=chrome-os-partner:54876 TEST=On resume through powerbtn, lidopen, keyboard press, etc. we are getting proper wake status. Change-Id: I5942d5c20d8c6aef73468dc611190bb7c49c7c7a Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/16040 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Brandon Breitenstein <brandon.breitenstein@intel.com>
2016-08-03 02:25:13 +02:00
/*
* This function re-writes the gpe0 register values in power state
* cbmem variable. After system wakes from sleep state internal PMC logic
* writes default values in GPE_CFG register which gives a wrong offset to
* calculate the wake reason. So we need to set it again to the routing
* table as per the devicetree.
*/
void fixup_power_state(void)
{
int i;
struct chipset_power_state *ps;
ps = cbmem_find(CBMEM_ID_POWER_STATE);
if (ps == NULL)
return;
for (i = 0; i < GPE0_REG_MAX; i++) {
soc/intel/apollolake: Rename ACPI Base Address and Size Macro Rename these two Macros to help use Common Code - ACPI_PMIO_BASE --> ACPI_BASE_ADDRESS ACPI_PMIO_SIZE --> ACPI_BASE_SIZE Change-Id: I21125b7206c241692cfdf1cdb10b8b3dee62b24a Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/20038 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-06-05 16:31:14 +02:00
ps->gpe0_sts[i] = inl(ACPI_BASE_ADDRESS + GPE0_STS(i));
ps->gpe0_en[i] = inl(ACPI_BASE_ADDRESS + GPE0_EN(i));
soc/apollolake: Return correct wake status in _SWS Wake status is calculated from the four pairs of gpe0 in cbmem CBMEM_ID_POWER_STATE which is filled very early in romstage and depends on the routing information in PMC GPE_CFG register. Coreboot sets the proper value of routing based on devicetree from pmc_init. But when system goes to S3 on waking up PMC is writing default values again in GPE_CFG which results in returning wrong wake status in _SWS. This patch corrects that behaviour by correcting the gpe0 pairs in cbmem after PMC sets the routing table in resume path. BUG=chrome-os-partner:54876 TEST=On resume through powerbtn, lidopen, keyboard press, etc. we are getting proper wake status. Change-Id: I5942d5c20d8c6aef73468dc611190bb7c49c7c7a Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/16040 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Brandon Breitenstein <brandon.breitenstein@intel.com>
2016-08-03 02:25:13 +02:00
printk(BIOS_DEBUG, "gpe0_sts[%d]: %08x gpe0_en[%d]: %08x\n",
i, ps->gpe0_sts[i], i, ps->gpe0_en[i]);
}
}
soc/apollolake: Add helper functions to access Power Management Registers Change-Id: I928efea33030e03cbbaead6812c617d20446f7c9 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/14289 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-02-05 05:13:34 +01:00
/* returns prev_sleep_state */
int fill_power_state(struct chipset_power_state *ps)
{
int i;
soc/apollolake/pmutil: Get PMC base address dynamically Instead of using a hardcoded address for PMC device BAR0, read it dynamically. This allows the allocator to move the BAR without needing a fixed resource. Note that we cannot do the same for the ACPI BAR (index 0x20), as it cannot be read back. Change-Id: If43e1ccb693ffb17b78bdd76140a0849493a0010 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com> Reviewed-on: https://review.coreboot.org/14633 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-04-05 21:40:24 +02:00
uintptr_t pmc_bar0 = read_pmc_mmio_bar();
soc/intel/apollolake: Rename ACPI Base Address and Size Macro Rename these two Macros to help use Common Code - ACPI_PMIO_BASE --> ACPI_BASE_ADDRESS ACPI_PMIO_SIZE --> ACPI_BASE_SIZE Change-Id: I21125b7206c241692cfdf1cdb10b8b3dee62b24a Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/20038 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-06-05 16:31:14 +02:00
ps->pm1_sts = inw(ACPI_BASE_ADDRESS + PM1_STS);
ps->pm1_en = inw(ACPI_BASE_ADDRESS + PM1_EN);
ps->pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT);
ps->tco_sts = inl(ACPI_BASE_ADDRESS + TCO_STS);
soc/apollolake/pmutil: Get PMC base address dynamically Instead of using a hardcoded address for PMC device BAR0, read it dynamically. This allows the allocator to move the BAR without needing a fixed resource. Note that we cannot do the same for the ACPI BAR (index 0x20), as it cannot be read back. Change-Id: If43e1ccb693ffb17b78bdd76140a0849493a0010 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com> Reviewed-on: https://review.coreboot.org/14633 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-04-05 21:40:24 +02:00
ps->prsts = read32((void *)(pmc_bar0 + PRSTS));
soc/intel/apollolake: Fix spacing around operators and commas Fix the following errors detected by checkpatch.pl: ERROR: spaces required around that '==' (ctx:VxO) ERROR: space required before that '-' (ctx:OxV) ERROR: spaces required around that '=' (ctx:VxW) ERROR: spaces required around that '=' (ctx:WxV) ERROR: spaces required around that '=' (ctx:VxV) ERROR: need consistent spacing around '+' (ctx:VxW) ERROR: space prohibited before that '++' (ctx:WxB) ERROR: space prohibited before that ',' (ctx:WxW) ERROR: space required after that ',' (ctx:VxV) TEST=Build for reef Change-Id: I37265a69fcb14fbf7c182ef29d823f70a5748ad8 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/18720 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-09 18:42:48 +01:00
ps->gen_pmcon1 = read32((void *)(pmc_bar0 + GEN_PMCON1));
soc/apollolake/pmutil: Get PMC base address dynamically Instead of using a hardcoded address for PMC device BAR0, read it dynamically. This allows the allocator to move the BAR without needing a fixed resource. Note that we cannot do the same for the ACPI BAR (index 0x20), as it cannot be read back. Change-Id: If43e1ccb693ffb17b78bdd76140a0849493a0010 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com> Reviewed-on: https://review.coreboot.org/14633 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-04-05 21:40:24 +02:00
ps->gen_pmcon2 = read32((void *)(pmc_bar0 + GEN_PMCON2));
ps->gen_pmcon3 = read32((void *)(pmc_bar0 + GEN_PMCON3));
soc/apollolake: Add helper functions to access Power Management Registers Change-Id: I928efea33030e03cbbaead6812c617d20446f7c9 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/14289 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-02-05 05:13:34 +01:00
ps->prev_sleep_state = chipset_prev_sleep_state(ps);
printk(BIOS_DEBUG, "pm1_sts: %04x pm1_en: %04x pm1_cnt: %08x\n",
ps->pm1_sts, ps->pm1_en, ps->pm1_cnt);
printk(BIOS_DEBUG, "prsts: %08x tco_sts: %08x\n",
ps->prsts, ps->tco_sts);
printk(BIOS_DEBUG,
"gen_pmcon1: %08x gen_pmcon2: %08x gen_pmcon3: %08x\n",
ps->gen_pmcon1, ps->gen_pmcon2, ps->gen_pmcon3);
printk(BIOS_DEBUG, "smi_en: %08x smi_sts: %08x\n",
soc/intel/apollolake: Rename ACPI Base Address and Size Macro Rename these two Macros to help use Common Code - ACPI_PMIO_BASE --> ACPI_BASE_ADDRESS ACPI_PMIO_SIZE --> ACPI_BASE_SIZE Change-Id: I21125b7206c241692cfdf1cdb10b8b3dee62b24a Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/20038 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-06-05 16:31:14 +02:00
inl(ACPI_BASE_ADDRESS + SMI_EN), inl(ACPI_BASE_ADDRESS + SMI_STS));
soc/intel/apollolake: Fix spacing around operators and commas Fix the following errors detected by checkpatch.pl: ERROR: spaces required around that '==' (ctx:VxO) ERROR: space required before that '-' (ctx:OxV) ERROR: spaces required around that '=' (ctx:VxW) ERROR: spaces required around that '=' (ctx:WxV) ERROR: spaces required around that '=' (ctx:VxV) ERROR: need consistent spacing around '+' (ctx:VxW) ERROR: space prohibited before that '++' (ctx:WxB) ERROR: space prohibited before that ',' (ctx:WxW) ERROR: space required after that ',' (ctx:VxV) TEST=Build for reef Change-Id: I37265a69fcb14fbf7c182ef29d823f70a5748ad8 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/18720 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-09 18:42:48 +01:00
for (i = 0; i < GPE0_REG_MAX; i++) {
soc/intel/apollolake: Rename ACPI Base Address and Size Macro Rename these two Macros to help use Common Code - ACPI_PMIO_BASE --> ACPI_BASE_ADDRESS ACPI_PMIO_SIZE --> ACPI_BASE_SIZE Change-Id: I21125b7206c241692cfdf1cdb10b8b3dee62b24a Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/20038 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-06-05 16:31:14 +02:00
ps->gpe0_sts[i] = inl(ACPI_BASE_ADDRESS + GPE0_STS(i));
ps->gpe0_en[i] = inl(ACPI_BASE_ADDRESS + GPE0_EN(i));
soc/apollolake: Add helper functions to access Power Management Registers Change-Id: I928efea33030e03cbbaead6812c617d20446f7c9 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/14289 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-02-05 05:13:34 +01:00
printk(BIOS_DEBUG, "gpe0_sts[%d]: %08x gpe0_en[%d]: %08x\n",
i, ps->gpe0_sts[i], i, ps->gpe0_en[i]);
}
printk(BIOS_DEBUG, "prev_sleep_state %d\n", ps->prev_sleep_state);
return ps->prev_sleep_state;
}
soc/intel/apollolake: add support for verstage There previously was no support for building verstage on apollolake. Add that suport by linking in the appropriate modules as well as providing vboot_platform_is_resuming(). The link address for verstage is the same as FSP-M because they would never be in CAR along side each other. Additionally, program the ACPI I/O BAR and enable decoding so sleep state can be determined for early firmware verification. Change-Id: I1a0baab342ac55fd82dbed476abe0063787e3491 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14972 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-05-26 18:00:44 +02:00
int vboot_platform_is_resuming(void)
{
soc/intel/apollolake: Rename ACPI Base Address and Size Macro Rename these two Macros to help use Common Code - ACPI_PMIO_BASE --> ACPI_BASE_ADDRESS ACPI_PMIO_SIZE --> ACPI_BASE_SIZE Change-Id: I21125b7206c241692cfdf1cdb10b8b3dee62b24a Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/20038 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-06-05 16:31:14 +02:00
if (!(inw(ACPI_BASE_ADDRESS + PM1_STS) & WAK_STS))
soc/intel/apollolake: add support for verstage There previously was no support for building verstage on apollolake. Add that suport by linking in the appropriate modules as well as providing vboot_platform_is_resuming(). The link address for verstage is the same as FSP-M because they would never be in CAR along side each other. Additionally, program the ACPI I/O BAR and enable decoding so sleep state can be determined for early firmware verification. Change-Id: I1a0baab342ac55fd82dbed476abe0063787e3491 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14972 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-05-26 18:00:44 +02:00
return 0;
soc/intel/apollolake: Rename ACPI Base Address and Size Macro Rename these two Macros to help use Common Code - ACPI_PMIO_BASE --> ACPI_BASE_ADDRESS ACPI_PMIO_SIZE --> ACPI_BASE_SIZE Change-Id: I21125b7206c241692cfdf1cdb10b8b3dee62b24a Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/20038 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-06-05 16:31:14 +02:00
return acpi_sleep_from_pm1(inl(ACPI_BASE_ADDRESS + PM1_CNT)) == ACPI_S3;
soc/intel/apollolake: add support for verstage There previously was no support for building verstage on apollolake. Add that suport by linking in the appropriate modules as well as providing vboot_platform_is_resuming(). The link address for verstage is the same as FSP-M because they would never be in CAR along side each other. Additionally, program the ACPI I/O BAR and enable decoding so sleep state can be determined for early firmware verification. Change-Id: I1a0baab342ac55fd82dbed476abe0063787e3491 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14972 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-05-26 18:00:44 +02:00
}
soc/intel/apollolake: Add utility functions for global reset Apollolake defines Global Reset where Host, TXE and PMC are reset. During boot we may need to trigger a global reset as part of platform initialization (or for error handling). Add functions to trigger global reset, enable/disable it and lock global reset bit. BUG=chrome-os-partner:54149 BRANCH=none TEST=none Change-Id: I84296cd1560a0740f33ef6b488f15f99d397998d Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/15198 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-18 00:30:13 +02:00
/*
* If possible, lock 0xcf9. Once the register is locked, it can't be changed.
* This lock is reset on cold boot, hard reset, soft reset and Sx.
*/
void global_reset_lock(void)
{
uintptr_t etr = read_pmc_mmio_bar() + ETR;
uint32_t reg;
reg = read32((void *)etr);
if (reg & CF9_LOCK)
return;
reg |= CF9_LOCK;
write32((void *)etr, reg);
}
/*
* Enable or disable global reset. If global reset is enabled, hard reset and
* soft reset will trigger global reset, where both host and TXE are reset.
* This is cleared on cold boot, hard reset, soft reset and Sx.
*/
void global_reset_enable(bool enable)
{
uintptr_t etr = read_pmc_mmio_bar() + ETR;
uint32_t reg;
reg = read32((void *)etr);
reg = enable ? reg | CF9_GLB_RST : reg & ~CF9_GLB_RST;
write32((void *)etr, reg);
}
intel/apollolake: Set sleep type to S5 on vboot reboot request Add support for vboot_platform_prepare_reboot which is called whenever vboot requests reboot of the platform. SLP_TYPE needs to be set to S5 in such conditions since the platform would no longer be in a resuming state after reset. Change-Id: I01392bfda90c9274cd52c1004555d250b1d539b7 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/15340 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-23 23:00:05 +02:00
/*
* The PM1 control is set to S5 when vboot requests a reboot because the power
* state code above may not have collected its data yet. Therefore, set it to
* S5 when vboot requests a reboot. That's necessary if vboot fails in the
* resume path and requests a reboot. This prevents a reboot loop where the
* error is continually hit on the failing vboot resume path.
*/
void vboot_platform_prepare_reboot(void)
{
soc/intel/apollolake: Rename ACPI Base Address and Size Macro Rename these two Macros to help use Common Code - ACPI_PMIO_BASE --> ACPI_BASE_ADDRESS ACPI_PMIO_SIZE --> ACPI_BASE_SIZE Change-Id: I21125b7206c241692cfdf1cdb10b8b3dee62b24a Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/20038 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-06-05 16:31:14 +02:00
const uint16_t port = ACPI_BASE_ADDRESS + PM1_CNT;
intel/apollolake: Set sleep type to S5 on vboot reboot request Add support for vboot_platform_prepare_reboot which is called whenever vboot requests reboot of the platform. SLP_TYPE needs to be set to S5 in such conditions since the platform would no longer be in a resuming state after reset. Change-Id: I01392bfda90c9274cd52c1004555d250b1d539b7 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/15340 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-23 23:00:05 +02:00
outl((inl(port) & ~(SLP_TYP)) | (SLP_TYP_S5 << SLP_TYP_SHIFT), port);
}
soc/intel/apollolake: provide poweroff() implementation Implement poweroff() by putting the chipset into ACPI S5 state. BUG=chrome-os-partner:54977 Change-Id: I4ee269f03afd252d4bce909a8cc7c64d6270b16e Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15686 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
2016-07-14 07:26:50 +02:00
void poweroff(void)
{
enable_pm1_control(SLP_EN | (SLP_TYP_S5 << SLP_TYP_SHIFT));
intel/apollolake: Do not halt in poweroff if in SMM Calling halt in poweroff when in SMM prevents SLP_SMI to be triggered preventing the system from entering sleep state. Fix this by calling halt only if ENV_SMM is not true. BUG=chrome-os-partner:56395 BRANCH=None TEST=Verified lidclose behavior on reef. Change-Id: If116c8f4e867543abdc2ff235457c167b5073767 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/16257 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-19 06:31:50 +02:00
/*
* Setting SLP_TYP_S5 in PM1 triggers SLP_SMI, which is handled by SMM
* to transition to S5 state. If halt is called in SMM, then it prevents
* the SMI handler from being triggered and system never enters S5.
*/
if (!ENV_SMM)
halt();
soc/intel/apollolake: provide poweroff() implementation Implement poweroff() by putting the chipset into ACPI S5 state. BUG=chrome-os-partner:54977 Change-Id: I4ee269f03afd252d4bce909a8cc7c64d6270b16e Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15686 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
2016-07-14 07:26:50 +02:00
}
soc/intel/apollolake: Initialize GPEs in bootblock Initialize the GPEs from mainboard config in bootblock, so they can be used in verstage to query latched interrupt status. I still left it called in ramstage just to be sure that the configuration was not overwritten in FSP stages. Tested by reading and reporting GPE status in a loop in verstage and manually triggering an interrupt on EC console. BUG=chrome-os-partner:53336 Change-Id: Iacd0483e4b3229aca602bb5bb40586eedf35a6ea Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/16670 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-19 21:02:54 +02:00
void pmc_gpe_init(void)
{
uint32_t gpio_cfg = 0;
uint32_t gpio_cfg_reg;
uint8_t dw1, dw2, dw3;
lib: provide clearer devicetree semantics The devicetree data structures have been available in more than just ramstage and romstage. In order to provide clearer and consistent semantics two new macros are provided: 1. DEVTREE_EARLY which is true when !ENV_RAMSTAGE 2. DEVTREE_CONST as a replacment for ROMSTAGE_CONST The ROMSTAGE_CONST attribute is used in the source code to mark the devicetree data structures as const in early stages even though it's not just romstage. Therefore, rename the attribute to DEVTREE_CONST as that's the actual usage. The only place where the usage was not devicetree related is console_loglevel, but the same name was used for consistency. Any stage that is not ramstage has the const C attribute applied when DEVTREE_CONST is used. Change-Id: Ibd51c2628dc8f68e0896974f7e4e7c8588d333ed Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/19333 Tested-by: build bot (Jenkins) Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-04-17 05:05:36 +02:00
DEVTREE_CONST struct soc_intel_apollolake_config *config;
soc/intel/apollolake: Initialize GPEs in bootblock Initialize the GPEs from mainboard config in bootblock, so they can be used in verstage to query latched interrupt status. I still left it called in ramstage just to be sure that the configuration was not overwritten in FSP stages. Tested by reading and reporting GPE status in a loop in verstage and manually triggering an interrupt on EC console. BUG=chrome-os-partner:53336 Change-Id: Iacd0483e4b3229aca602bb5bb40586eedf35a6ea Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/16670 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-19 21:02:54 +02:00
/* Look up the device in devicetree */
lib: provide clearer devicetree semantics The devicetree data structures have been available in more than just ramstage and romstage. In order to provide clearer and consistent semantics two new macros are provided: 1. DEVTREE_EARLY which is true when !ENV_RAMSTAGE 2. DEVTREE_CONST as a replacment for ROMSTAGE_CONST The ROMSTAGE_CONST attribute is used in the source code to mark the devicetree data structures as const in early stages even though it's not just romstage. Therefore, rename the attribute to DEVTREE_CONST as that's the actual usage. The only place where the usage was not devicetree related is console_loglevel, but the same name was used for consistency. Any stage that is not ramstage has the const C attribute applied when DEVTREE_CONST is used. Change-Id: Ibd51c2628dc8f68e0896974f7e4e7c8588d333ed Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/19333 Tested-by: build bot (Jenkins) Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-04-17 05:05:36 +02:00
DEVTREE_CONST struct device *dev = dev_find_slot(0, SA_DEVFN_ROOT);
soc/intel/apollolake: Initialize GPEs in bootblock Initialize the GPEs from mainboard config in bootblock, so they can be used in verstage to query latched interrupt status. I still left it called in ramstage just to be sure that the configuration was not overwritten in FSP stages. Tested by reading and reporting GPE status in a loop in verstage and manually triggering an interrupt on EC console. BUG=chrome-os-partner:53336 Change-Id: Iacd0483e4b3229aca602bb5bb40586eedf35a6ea Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/16670 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-19 21:02:54 +02:00
if (!dev || !dev->chip_info) {
printk(BIOS_ERR, "BUG! Could not find SOC devicetree config\n");
return;
}
config = dev->chip_info;
uintptr_t pmc_bar = get_pmc_mmio_bar();
const uint32_t gpio_cfg_mask =
(GPE0_DWX_MASK << GPE0_DW1_SHIFT) |
(GPE0_DWX_MASK << GPE0_DW2_SHIFT) |
(GPE0_DWX_MASK << GPE0_DW3_SHIFT);
/* Assign to local variable */
dw1 = config->gpe0_dw1;
dw2 = config->gpe0_dw2;
dw3 = config->gpe0_dw3;
/* Making sure that bad values don't bleed into the other fields */
dw1 &= GPE0_DWX_MASK;
dw2 &= GPE0_DWX_MASK;
dw3 &= GPE0_DWX_MASK;
/* Route the GPIOs to the GPE0 block. Determine that all values
* are different, and if they aren't use the reset values.
* DW0 is reserved/unused */
if (dw1 == dw2 || dw2 == dw3) {
printk(BIOS_INFO, "PMC: Using default GPE route.\n");
gpio_cfg = read32((void *)pmc_bar + GPIO_GPE_CFG);
dw1 = (gpio_cfg >> GPE0_DW1_SHIFT) & GPE0_DWX_MASK;
dw2 = (gpio_cfg >> GPE0_DW2_SHIFT) & GPE0_DWX_MASK;
dw3 = (gpio_cfg >> GPE0_DW3_SHIFT) & GPE0_DWX_MASK;
} else {
gpio_cfg |= (uint32_t)dw1 << GPE0_DW1_SHIFT;
gpio_cfg |= (uint32_t)dw2 << GPE0_DW2_SHIFT;
gpio_cfg |= (uint32_t)dw3 << GPE0_DW3_SHIFT;
}
gpio_cfg_reg = read32((void *)pmc_bar + GPIO_GPE_CFG) & ~gpio_cfg_mask;
gpio_cfg_reg |= gpio_cfg & gpio_cfg_mask;
write32((void *)pmc_bar + GPIO_GPE_CFG, gpio_cfg_reg);
/* Set the routes in the GPIO communities as well. */
gpio_route_gpe(dw1, dw2, dw3);
}
soc/intel/apollolake: Enable ACPI PM timer emulation on all CPUs Currently we enable ACPI PM timer emulation only on BSP. So the timer doesn't work on other cores and that breaks OSes that use it. Also, microcode uses this information to figure out ACPI IO base, and that is used for other features. This patch enables ACPI timer emulation on all the logical CPUs. BUG=chrome-os-partner:60011 TEST=iotools rdmsr x 0x121, x={0..3}, make sure it is set Change-Id: I0d6cb8761c1c25d3a2fcf59a49c1eda9e4ccc70c Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/17663 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-12-01 02:39:16 +01:00
void enable_pm_timer_emulation(void)
{
/* ACPI PM timer emulation */
msr_t msr;
/*
* The derived frequency is calculated as follows:
* (CTC_FREQ * msr[63:32]) >> 32 = target frequency.
* Back solve the multiplier so the 3.579545MHz ACPI timer
* frequency is used.
*/
msr.hi = (3579545ULL << 32) / CTC_FREQ;
/* Set PM1 timer IO port and enable*/
soc/intel/apollolake: Rename ACPI Base Address and Size Macro Rename these two Macros to help use Common Code - ACPI_PMIO_BASE --> ACPI_BASE_ADDRESS ACPI_PMIO_SIZE --> ACPI_BASE_SIZE Change-Id: I21125b7206c241692cfdf1cdb10b8b3dee62b24a Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/20038 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-06-05 16:31:14 +02:00
msr.lo = EMULATE_PM_TMR_EN | (ACPI_BASE_ADDRESS + R_ACPI_PM1_TMR);
soc/intel/apollolake: Enable ACPI PM timer emulation on all CPUs Currently we enable ACPI PM timer emulation only on BSP. So the timer doesn't work on other cores and that breaks OSes that use it. Also, microcode uses this information to figure out ACPI IO base, and that is used for other features. This patch enables ACPI timer emulation on all the logical CPUs. BUG=chrome-os-partner:60011 TEST=iotools rdmsr x 0x121, x={0..3}, make sure it is set Change-Id: I0d6cb8761c1c25d3a2fcf59a49c1eda9e4ccc70c Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/17663 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-12-01 02:39:16 +01:00
wrmsr(MSR_EMULATE_PM_TMR, msr);
}
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