2009-10-28 18:36:11 +01:00
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##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2009 coresystems GmbH
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; version 2 of the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with this program; if not, write to the Free Software
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## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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##
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2010-08-30 18:36:51 +02:00
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if BOARD_INTEL_D945GCLF
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2009-10-28 18:36:11 +01:00
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2010-08-30 18:36:51 +02:00
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config BOARD_SPECIFIC_OPTIONS # dummy
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def_bool y
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2009-10-28 17:52:48 +01:00
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select ARCH_X86
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2009-12-02 06:43:50 +01:00
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select CPU_INTEL_SOCKET_441
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2012-02-24 15:08:18 +01:00
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select NORTHBRIDGE_INTEL_I945
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select NORTHBRIDGE_INTEL_SUBTYPE_I945GC
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northbridge/intel/i945: CHECK_SLFRCS_ON_RESUME Kconfig option
Originally brought up by Sven Schnelle in March 2011
http://patchwork.coreboot.org/patch/2801/
http://www.coreboot.org/pipermail/coreboot/2011-March/064277.html
On some mainboards it may be neccessary to reset early during resume
from S3 if the SLFRCS register indicates that a memory channel is not
guaranteed to be in self-refresh.
On other mainboards, such as Lenovo X60 and T60, the check always
creates false positives, effectively making it impossible to resume.
The SLFRCS register is documented on page 197 of
Mobile Intel® 945 Express Chipset Family Datasheet
Document Number: 309219-006
which is publically available, and the register indicates if a memory
channel is guaranteed to be in self-refresh mode (if bit = 1), or that
a memory channel *may or may not be* in self-refresh mode (if bit = 0).
The register can thus only be used to positively learn that memory is
in self-refresh. It is not known for sure that memory is *not* in
self-refresh. The register is reset by the PWROK signal, which *should*
go low during S3, and go high again when resuming, so it is unsurprising
that SLFRCS has already been cleared when we read the register.
Sven's measurements of the CKE signal on a ThinkPad shows that memory
remains in self-refresh indefinitely, until coreboot re-initializes the
memory controller, even when SLFRCS bits were = 0.
Boards which require a warm reset when SLFRCS bits are cleared must now
explicitly enable the check in the mainboard Kconfig file.
This commit selects the new option in all existing i945 mainboards.
A follow-up commit will remove the option for ThinkPads.
Change-Id: I02320675efb8fde05c371ef243ba5093a4da6d11
Signed-off-by: Peter Stuge <peter@stuge.se>
Reviewed-on: http://review.coreboot.org/590
Tested-by: build bot (Jenkins)
Reviewed-by: Sven Schnelle <svens@stackframe.org>
2012-01-27 22:17:09 +01:00
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select CHECK_SLFRCS_ON_RESUME
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2009-10-28 17:52:48 +01:00
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select SOUTHBRIDGE_INTEL_I82801GX
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2009-10-28 19:51:47 +01:00
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select SUPERIO_SMSC_LPC47M15X
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2010-07-06 23:05:04 +02:00
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select HAVE_OPTION_TABLE
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2009-10-28 17:52:48 +01:00
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select HAVE_PIRQ_TABLE
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select HAVE_MP_TABLE
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2010-01-18 18:30:36 +01:00
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select HAVE_ACPI_TABLES
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2010-01-25 11:50:21 +01:00
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select HAVE_ACPI_RESUME
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2009-10-28 17:52:48 +01:00
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select MMCONF_SUPPORT
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2010-01-25 08:56:01 +01:00
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select BOARD_ROMSIZE_KB_512
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2010-03-22 12:50:52 +01:00
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select GFXUMA
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2010-10-01 10:02:45 +02:00
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select CHANNEL_XOR_RANDOMIZATION
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2012-07-26 11:34:57 +02:00
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select RTL8168_ROM_DISABLE
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2009-10-28 17:52:48 +01:00
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config MAINBOARD_DIR
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string
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default intel/d945gclf
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config MAINBOARD_PART_NUMBER
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string
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default "D945GCLF"
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config MMCONF_BASE_ADDRESS
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hex
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default 0xf0000000
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config IRQ_SLOT_COUNT
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int
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default 18
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2010-01-25 08:56:01 +01:00
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config MAX_CPUS
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int
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default 4
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2010-08-30 18:36:51 +02:00
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endif # BOARD_INTEL_D945GCLF
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