coreboot-kgpe-d16/src/mainboard/intel/d945gclf/Kconfig

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##
## This file is part of the coreboot project.
##
## Copyright (C) 2009 coresystems GmbH
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program; if not, write to the Free Software
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
if BOARD_INTEL_D945GCLF
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select ARCH_X86
select CPU_INTEL_SOCKET_441
select NORTHBRIDGE_INTEL_I945
select NORTHBRIDGE_INTEL_SUBTYPE_I945GC
northbridge/intel/i945: CHECK_SLFRCS_ON_RESUME Kconfig option Originally brought up by Sven Schnelle in March 2011 http://patchwork.coreboot.org/patch/2801/ http://www.coreboot.org/pipermail/coreboot/2011-March/064277.html On some mainboards it may be neccessary to reset early during resume from S3 if the SLFRCS register indicates that a memory channel is not guaranteed to be in self-refresh. On other mainboards, such as Lenovo X60 and T60, the check always creates false positives, effectively making it impossible to resume. The SLFRCS register is documented on page 197 of Mobile Intel® 945 Express Chipset Family Datasheet Document Number: 309219-006 which is publically available, and the register indicates if a memory channel is guaranteed to be in self-refresh mode (if bit = 1), or that a memory channel *may or may not be* in self-refresh mode (if bit = 0). The register can thus only be used to positively learn that memory is in self-refresh. It is not known for sure that memory is *not* in self-refresh. The register is reset by the PWROK signal, which *should* go low during S3, and go high again when resuming, so it is unsurprising that SLFRCS has already been cleared when we read the register. Sven's measurements of the CKE signal on a ThinkPad shows that memory remains in self-refresh indefinitely, until coreboot re-initializes the memory controller, even when SLFRCS bits were = 0. Boards which require a warm reset when SLFRCS bits are cleared must now explicitly enable the check in the mainboard Kconfig file. This commit selects the new option in all existing i945 mainboards. A follow-up commit will remove the option for ThinkPads. Change-Id: I02320675efb8fde05c371ef243ba5093a4da6d11 Signed-off-by: Peter Stuge <peter@stuge.se> Reviewed-on: http://review.coreboot.org/590 Tested-by: build bot (Jenkins) Reviewed-by: Sven Schnelle <svens@stackframe.org>
2012-01-27 22:17:09 +01:00
select CHECK_SLFRCS_ON_RESUME
select SOUTHBRIDGE_INTEL_I82801GX
select SUPERIO_SMSC_LPC47M15X
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
select HAVE_ACPI_TABLES
select HAVE_ACPI_RESUME
select MMCONF_SUPPORT
select BOARD_ROMSIZE_KB_512
select GFXUMA
select CHANNEL_XOR_RANDOMIZATION
select RTL8168_ROM_DISABLE
config MAINBOARD_DIR
string
default intel/d945gclf
config MAINBOARD_PART_NUMBER
string
default "D945GCLF"
config MMCONF_BASE_ADDRESS
hex
default 0xf0000000
config IRQ_SLOT_COUNT
int
default 18
config MAX_CPUS
int
default 4
endif # BOARD_INTEL_D945GCLF