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coreboot-kgpe-d16/src/soc/intel/apollolake/chip.c

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soc/intel/apollolake: Add chip initialization Change-Id: I54532b71c7649f7eeccbb2213b31418cfdbfb00c Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/13911 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-03-05 06:41:13 +01:00
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2015 Intel Corp.
* (Written by Alexandru Gagniuc <alexandrux.gagniuc@intel.com> for Intel Corp.)
* (Written by Andrey Petrov <andrey.petrov@intel.com> for Intel Corp.)
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
soc/intel: Update license headers Update all of the license headers to make sure they are compliant with coreboot's license header policy. Change-Id: I151d058615290e528d9d1738c17804f6b9cc8dce Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/14321 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-04-10 19:09:16 +02:00
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
soc/intel/apollolake: Add chip initialization Change-Id: I54532b71c7649f7eeccbb2213b31418cfdbfb00c Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/13911 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-03-05 06:41:13 +01:00
*/
soc/apollolake: Add SOC specific c-state table Please refer Apollolake BIOS Writers Guide Change-Id: I5f82cdc4b34a53b5184ef1e918cae15a1df6cc5e Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/15051 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-18 22:47:08 +02:00
#include <arch/acpi.h>
soc/intel/apollolake: Add chip initialization Change-Id: I54532b71c7649f7eeccbb2213b31418cfdbfb00c Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/13911 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-03-05 06:41:13 +01:00
#include <bootstate.h>
soc/intel/apollolake: Add handling of GNVS ACPI entry for CHROMEOS builds Add chromeos required GNVS feature. The GNVS table stays in both CBMEM and ACPI DSDT tables. Change-Id: I4db0eb18d2de62917a94704318a7896c04e4777f Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/14471 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-04-20 03:04:21 +02:00
#include <cbmem.h>
soc/intel/apollolake: Add chip initialization Change-Id: I54532b71c7649f7eeccbb2213b31418cfdbfb00c Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/13911 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-03-05 06:41:13 +01:00
#include <console/console.h>
#include <cpu/cpu.h>
#include <device/device.h>
#include <device/pci.h>
#include <fsp/api.h>
#include <fsp/util.h>
#include <memrange.h>
soc/intel/apollolake: Update platform-specific FSP headers This updates FSP UPD headers that adds new fields. Importantly there are new FSPS UPD fields that allow to specify some BARs. They are needed by FSP SiliconInit API to work properly. Change-Id: Ie268c57c66b4d8fd6e00835916004058ff05762e Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/14217 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-03-18 22:43:00 +01:00
#include <soc/iomap.h>
soc/intel/apollolake: Add chip initialization Change-Id: I54532b71c7649f7eeccbb2213b31418cfdbfb00c Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/13911 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-03-05 06:41:13 +01:00
#include <soc/cpu.h>
soc/intel/apollolake: Take advantage of common opregion code Change-Id: I2d16336513bcd5a0544a6b68b609e40dd7c141fb Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/14807 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-13 04:11:48 +02:00
#include <soc/intel/common/vbt.h>
soc/intel/apollolake: work around FSP for gpio interrupt polarity FSP is currently setting a hard-coded policy for the interrupt polarity settings. When the mainboard has already set the GPIO settings up prior to SiliconInit being called that results in the previous settings being dropped. Work around FSP's default policy until FSP is fixed. BUG=chrome-os-partner:54955 Change-Id: Ibbd8c4894d8fbce479aeb73aa775b67df15dae85 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15649 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-13 08:49:10 +02:00
#include <soc/itss.h>
soc/intel/apollolake: Add handling of GNVS ACPI entry for CHROMEOS builds Add chromeos required GNVS feature. The GNVS table stays in both CBMEM and ACPI DSDT tables. Change-Id: I4db0eb18d2de62917a94704318a7896c04e4777f Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/14471 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-04-20 03:04:21 +02:00
#include <soc/nvs.h>
soc/intel/apollolake: Add chip initialization Change-Id: I54532b71c7649f7eeccbb2213b31418cfdbfb00c Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/13911 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-03-05 06:41:13 +01:00
#include <soc/pci_devs.h>
intel/apollolake: Enable SPI properly in bootblock and ramstage Bootblock: - Temporary BAR needs to be assigned for SPI device until PCI enumeration is done by ramstage which allocates a new BAR. - Call spi_init to allow bootblock/verstage to write/erase on flash. Ramstage: - spi_init needs to run in ramstage to allow write protect to be disabled for eventlog and NVRAM updates. This needs to be done pretty early so that any init calls(e.g. mainboard_ec_init) writing to flash work properly. Verified with this change that there are no more flash write/erase errors for ELOG/NVRAM. BUG=chrome-os-partner:54283 Change-Id: Iff840e055548485e6521889fcf264a10fb5d9491 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/15209 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com> Tested-by: build bot (Jenkins)
2016-06-16 02:13:20 +02:00
#include <spi-generic.h>
soc/intel/apollolake: Implement global reset handling Global reset enable bit is not cleared on reset. Therefore, clear the bit early. Lock down 0xcf9 so that payload/OS can't issue global reset. BUG=chrome-os-partner:54149 BRANCH=none TEST=none Change-Id: I3ddf6dd82429b725c818bcd96e163d2ca0acd308 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/15199 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-06-15 07:20:28 +02:00
#include <soc/pm.h>
soc/intel/apollolake: handle p2sb quirks The P2SB device is device 0xd and function 0. If hidden that causes the latter pci devices on function >= 1 to not be probed in the kernel. This is also a problem for coreboot if the P2SB device is hidden by FSP. That means the coreboot driver won't be ran. Therefore, provide hide and unhide functions for the P2SB device. The other quirk is to allow the GPIO devices to work correctly. Those devices are ACPI devices. However, their resources are sub-regions within the P2SB BAR. Sadly, linux doesn't handle ACPI devices being children of PCI devices. This leads to resource conflict errors when the P2SB device is visible. For the time being keep the P2SB device hidden, but also ensure the resources it is using are accounted for and reserved. The fallout of that is the PMC and SPI device are no longer probed by the kernel. BUG=chrome-os-partner:53017 TEST=Ensured P2SB device is visible and pci resources are allocated correctly for the devices. Change-Id: I24e59bbde74310e1ce8425b344a3ad0b88702153 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15530 Tested-by: build bot (Jenkins) Reviewed-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-01 23:36:03 +02:00
#include <soc/p2sb.h>
soc/intel/apollolake: Add chip initialization Change-Id: I54532b71c7649f7eeccbb2213b31418cfdbfb00c Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/13911 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-03-05 06:41:13 +01:00
#include "chip.h"
soc/intel/apollolake: Take advantage of common opregion code Change-Id: I2d16336513bcd5a0544a6b68b609e40dd7c141fb Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/14807 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-13 04:11:48 +02:00
static void *vbt;
static struct region_device vbt_rdev;
soc/intel/apollolake: Add function to translate device into ACPI name Add support for the soc_acpi_name() handler in the device operations structure to translate a device path into ACPI name. In order to make this more complete add some missing devices in include/soc/pci_devs.h. Change-Id: I517bc86d8d9fe70bfa0fc4eb3828681887239587 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/15479 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-27 19:51:17 +02:00
static const char *soc_acpi_name(struct device *dev)
{
if (dev->path.type == DEVICE_PATH_DOMAIN)
return "PCI0";
if (dev->path.type != DEVICE_PATH_PCI)
return NULL;
switch (dev->path.pci.devfn) {
/* DSDT: acpi/northbridge.asl */
case NB_DEVFN:
return "MCHC";
/* DSDT: acpi/lpc.asl */
case LPC_DEVFN:
return "LPCB";
/* DSDT: acpi/xhci.asl */
case XHCI_DEVFN:
return "XHCI";
/* DSDT: acpi/pch_hda.asl */
case HDA_DEVFN:
return "HDAS";
/* DSDT: acpi/lpss.asl */
case LPSS_DEVFN_UART0:
return "URT1";
case LPSS_DEVFN_UART1:
return "URT2";
case LPSS_DEVFN_UART2:
return "URT3";
case LPSS_DEVFN_UART3:
return "URT4";
case LPSS_DEVFN_SPI0:
return "SPI1";
case LPSS_DEVFN_SPI1:
return "SPI2";
case LPSS_DEVFN_SPI2:
return "SPI3";
case LPSS_DEVFN_PWM:
return "PWM";
case LPSS_DEVFN_I2C0:
return "I2C0";
case LPSS_DEVFN_I2C1:
return "I2C1";
case LPSS_DEVFN_I2C2:
return "I2C2";
case LPSS_DEVFN_I2C3:
return "I2C3";
case LPSS_DEVFN_I2C4:
return "I2C4";
case LPSS_DEVFN_I2C5:
return "I2C5";
case LPSS_DEVFN_I2C6:
return "I2C6";
case LPSS_DEVFN_I2C7:
return "I2C7";
/* Storage */
case SDCARD_DEVFN:
return "SDCD";
case EMMC_DEVFN:
return "EMMC";
case SDIO_DEVFN:
return "SDIO";
}
return NULL;
}
soc/intel/apollolake: Add chip initialization Change-Id: I54532b71c7649f7eeccbb2213b31418cfdbfb00c Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/13911 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-03-05 06:41:13 +01:00
static void pci_domain_set_resources(device_t dev)
{
assign_resources(dev->link_list);
}
static struct device_operations pci_domain_ops = {
.read_resources = pci_domain_read_resources,
.set_resources = pci_domain_set_resources,
.enable_resources = NULL,
.init = NULL,
.scan_bus = pci_domain_scan_bus,
.ops_pci_bus = pci_bus_default_ops,
soc/intel/apollolake: Add function to translate device into ACPI name Add support for the soc_acpi_name() handler in the device operations structure to translate a device path into ACPI name. In order to make this more complete add some missing devices in include/soc/pci_devs.h. Change-Id: I517bc86d8d9fe70bfa0fc4eb3828681887239587 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/15479 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-27 19:51:17 +02:00
.acpi_name = &soc_acpi_name,
soc/intel/apollolake: Add chip initialization Change-Id: I54532b71c7649f7eeccbb2213b31418cfdbfb00c Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/13911 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-03-05 06:41:13 +01:00
};
static struct device_operations cpu_bus_ops = {
.read_resources = DEVICE_NOOP,
.set_resources = DEVICE_NOOP,
.enable_resources = DEVICE_NOOP,
.init = apollolake_init_cpus,
.scan_bus = NULL,
soc/apollolake: Add SOC specific c-state table Please refer Apollolake BIOS Writers Guide Change-Id: I5f82cdc4b34a53b5184ef1e918cae15a1df6cc5e Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/15051 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-18 22:47:08 +02:00
.acpi_fill_ssdt_generator = generate_cpu_entries,
soc/intel/apollolake: Add chip initialization Change-Id: I54532b71c7649f7eeccbb2213b31418cfdbfb00c Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/13911 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-03-05 06:41:13 +01:00
};
static void enable_dev(device_t dev)
{
/* Set the operations if it is a special bus type */
if (dev->path.type == DEVICE_PATH_DOMAIN) {
dev->ops = &pci_domain_ops;
} else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) {
dev->ops = &cpu_bus_ops;
}
}
static void soc_init(void *data)
{
struct range_entry range;
soc/intel/apollolake: Add handling of GNVS ACPI entry for CHROMEOS builds Add chromeos required GNVS feature. The GNVS table stays in both CBMEM and ACPI DSDT tables. Change-Id: I4db0eb18d2de62917a94704318a7896c04e4777f Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/14471 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-04-20 03:04:21 +02:00
struct global_nvs_t *gnvs;
soc/intel/apollolake: Add chip initialization Change-Id: I54532b71c7649f7eeccbb2213b31418cfdbfb00c Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/13911 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-03-05 06:41:13 +01:00
soc/intel/apollolake: Take advantage of common opregion code Change-Id: I2d16336513bcd5a0544a6b68b609e40dd7c141fb Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/14807 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-13 04:11:48 +02:00
/* Save VBT info and mapping */
if (locate_vbt(&vbt_rdev) != CB_ERR)
vbt = rdev_mmap_full(&vbt_rdev);
soc/intel/apollolake: work around FSP for gpio interrupt polarity FSP is currently setting a hard-coded policy for the interrupt polarity settings. When the mainboard has already set the GPIO settings up prior to SiliconInit being called that results in the previous settings being dropped. Work around FSP's default policy until FSP is fixed. BUG=chrome-os-partner:54955 Change-Id: Ibbd8c4894d8fbce479aeb73aa775b67df15dae85 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15649 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-13 08:49:10 +02:00
/* Snapshot the current GPIO IRQ polarities. FSP is setting a
* default policy that doesn't honor boards' requirements. */
itss_snapshot_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END);
soc/intel/apollolake: Add chip initialization Change-Id: I54532b71c7649f7eeccbb2213b31418cfdbfb00c Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/13911 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-03-05 06:41:13 +01:00
/* TODO: tigten this resource range */
/* TODO: fix for S3 resume, as this would corrupt OS memory */
range_entry_init(&range, 0x200000, 4ULL*GiB, 0);
fsp_silicon_init(&range);
soc/intel/apollolake: Add handling of GNVS ACPI entry for CHROMEOS builds Add chromeos required GNVS feature. The GNVS table stays in both CBMEM and ACPI DSDT tables. Change-Id: I4db0eb18d2de62917a94704318a7896c04e4777f Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/14471 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-04-20 03:04:21 +02:00
soc/intel/apollolake: work around FSP for gpio interrupt polarity FSP is currently setting a hard-coded policy for the interrupt polarity settings. When the mainboard has already set the GPIO settings up prior to SiliconInit being called that results in the previous settings being dropped. Work around FSP's default policy until FSP is fixed. BUG=chrome-os-partner:54955 Change-Id: Ibbd8c4894d8fbce479aeb73aa775b67df15dae85 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15649 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-13 08:49:10 +02:00
/* Restore GPIO IRQ polarities back to previous settings. */
itss_restore_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END);
soc/intel/apollolake: handle p2sb quirks The P2SB device is device 0xd and function 0. If hidden that causes the latter pci devices on function >= 1 to not be probed in the kernel. This is also a problem for coreboot if the P2SB device is hidden by FSP. That means the coreboot driver won't be ran. Therefore, provide hide and unhide functions for the P2SB device. The other quirk is to allow the GPIO devices to work correctly. Those devices are ACPI devices. However, their resources are sub-regions within the P2SB BAR. Sadly, linux doesn't handle ACPI devices being children of PCI devices. This leads to resource conflict errors when the P2SB device is visible. For the time being keep the P2SB device hidden, but also ensure the resources it is using are accounted for and reserved. The fallout of that is the PMC and SPI device are no longer probed by the kernel. BUG=chrome-os-partner:53017 TEST=Ensured P2SB device is visible and pci resources are allocated correctly for the devices. Change-Id: I24e59bbde74310e1ce8425b344a3ad0b88702153 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15530 Tested-by: build bot (Jenkins) Reviewed-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-01 23:36:03 +02:00
/*
* Keep the P2SB device visible so it and the other devices are
* visible in coreboot for driver support and PCI resource allocation.
* There is a UPD setting for this, but it's more consistent to use
* hide and unhide symmetrically.
*/
p2sb_unhide();
soc/intel/apollolake: Add handling of GNVS ACPI entry for CHROMEOS builds Add chromeos required GNVS feature. The GNVS table stays in both CBMEM and ACPI DSDT tables. Change-Id: I4db0eb18d2de62917a94704318a7896c04e4777f Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/14471 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-04-20 03:04:21 +02:00
/* Allocate ACPI NVS in CBMEM */
gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(*gnvs));
soc/intel/apollolake: Add chip initialization Change-Id: I54532b71c7649f7eeccbb2213b31418cfdbfb00c Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/13911 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-03-05 06:41:13 +01:00
}
soc/intel/apollolake: Take advantage of common opregion code Change-Id: I2d16336513bcd5a0544a6b68b609e40dd7c141fb Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/14807 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-13 04:11:48 +02:00
static void soc_final(void *data)
{
if (vbt)
rdev_munmap(&vbt_rdev, vbt);
soc/intel/apollolake: Implement global reset handling Global reset enable bit is not cleared on reset. Therefore, clear the bit early. Lock down 0xcf9 so that payload/OS can't issue global reset. BUG=chrome-os-partner:54149 BRANCH=none TEST=none Change-Id: I3ddf6dd82429b725c818bcd96e163d2ca0acd308 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/15199 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-06-15 07:20:28 +02:00
/* Disable global reset, just in case */
global_reset_enable(0);
/* Make sure payload/OS can't trigger global reset */
global_reset_lock();
soc/intel/apollolake: Take advantage of common opregion code Change-Id: I2d16336513bcd5a0544a6b68b609e40dd7c141fb Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/14807 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-13 04:11:48 +02:00
}
soc/intel/apollolake: add code to disable unused device Parse the devicetree and pass the unused device to fsp for disabling the device function. BRANCH=none BUG=chrome-os-partner:54325 TEST=device off in devicetree should disable the device. Change-Id: I784b72a43fda13aa17634bf680205ab2d36e8d09 Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com> Reviewed-on: https://review.coreboot.org/15337 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-06-23 03:32:17 +02:00
static void disable_dev(struct device *dev, struct FSP_S_CONFIG *silconfig) {
switch (dev->path.pci.devfn) {
case ISH_DEVFN:
silconfig->IshEnable = 0;
break;
case SATA_DEVFN:
silconfig->EnableSata = 0;
break;
case PCIEA0_DEVFN:
silconfig->PcieRootPortEn[0] = 0;
break;
case PCIEA1_DEVFN:
silconfig->PcieRootPortEn[1] = 0;
break;
case PCIEA2_DEVFN:
silconfig->PcieRootPortEn[2] = 0;
break;
case PCIEA3_DEVFN:
silconfig->PcieRootPortEn[3] = 0;
break;
case PCIEB0_DEVFN:
silconfig->PcieRootPortEn[4] = 0;
break;
case PCIEB1_DEVFN:
silconfig->PcieRootPortEn[5] = 0;
break;
case XHCI_DEVFN:
silconfig->Usb30Mode = 0;
break;
case XDCI_DEVFN:
silconfig->UsbOtg = 0;
break;
soc/intel/apollolake: Change PCI macros to match Skylake Change PCI macros in such a way they can be transparently used across romstage and ramstage. Change-Id: Idc708c1990f2fc1d941bb82efcb0a697524f2eca Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/15483 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-06-28 21:14:33 +02:00
case LPSS_DEVFN_I2C0:
soc/intel/apollolake: add code to disable unused device Parse the devicetree and pass the unused device to fsp for disabling the device function. BRANCH=none BUG=chrome-os-partner:54325 TEST=device off in devicetree should disable the device. Change-Id: I784b72a43fda13aa17634bf680205ab2d36e8d09 Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com> Reviewed-on: https://review.coreboot.org/15337 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-06-23 03:32:17 +02:00
silconfig->I2c0Enable = 0;
break;
soc/intel/apollolake: Change PCI macros to match Skylake Change PCI macros in such a way they can be transparently used across romstage and ramstage. Change-Id: Idc708c1990f2fc1d941bb82efcb0a697524f2eca Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/15483 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-06-28 21:14:33 +02:00
case LPSS_DEVFN_I2C1:
soc/intel/apollolake: add code to disable unused device Parse the devicetree and pass the unused device to fsp for disabling the device function. BRANCH=none BUG=chrome-os-partner:54325 TEST=device off in devicetree should disable the device. Change-Id: I784b72a43fda13aa17634bf680205ab2d36e8d09 Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com> Reviewed-on: https://review.coreboot.org/15337 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-06-23 03:32:17 +02:00
silconfig->I2c1Enable = 0;
break;
soc/intel/apollolake: Change PCI macros to match Skylake Change PCI macros in such a way they can be transparently used across romstage and ramstage. Change-Id: Idc708c1990f2fc1d941bb82efcb0a697524f2eca Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/15483 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-06-28 21:14:33 +02:00
case LPSS_DEVFN_I2C2:
soc/intel/apollolake: add code to disable unused device Parse the devicetree and pass the unused device to fsp for disabling the device function. BRANCH=none BUG=chrome-os-partner:54325 TEST=device off in devicetree should disable the device. Change-Id: I784b72a43fda13aa17634bf680205ab2d36e8d09 Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com> Reviewed-on: https://review.coreboot.org/15337 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-06-23 03:32:17 +02:00
silconfig->I2c2Enable = 0;
break;
soc/intel/apollolake: Change PCI macros to match Skylake Change PCI macros in such a way they can be transparently used across romstage and ramstage. Change-Id: Idc708c1990f2fc1d941bb82efcb0a697524f2eca Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/15483 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-06-28 21:14:33 +02:00
case LPSS_DEVFN_I2C3:
soc/intel/apollolake: add code to disable unused device Parse the devicetree and pass the unused device to fsp for disabling the device function. BRANCH=none BUG=chrome-os-partner:54325 TEST=device off in devicetree should disable the device. Change-Id: I784b72a43fda13aa17634bf680205ab2d36e8d09 Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com> Reviewed-on: https://review.coreboot.org/15337 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-06-23 03:32:17 +02:00
silconfig->I2c3Enable = 0;
break;
soc/intel/apollolake: Change PCI macros to match Skylake Change PCI macros in such a way they can be transparently used across romstage and ramstage. Change-Id: Idc708c1990f2fc1d941bb82efcb0a697524f2eca Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/15483 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-06-28 21:14:33 +02:00
case LPSS_DEVFN_I2C4:
soc/intel/apollolake: add code to disable unused device Parse the devicetree and pass the unused device to fsp for disabling the device function. BRANCH=none BUG=chrome-os-partner:54325 TEST=device off in devicetree should disable the device. Change-Id: I784b72a43fda13aa17634bf680205ab2d36e8d09 Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com> Reviewed-on: https://review.coreboot.org/15337 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-06-23 03:32:17 +02:00
silconfig->I2c4Enable = 0;
break;
soc/intel/apollolake: Change PCI macros to match Skylake Change PCI macros in such a way they can be transparently used across romstage and ramstage. Change-Id: Idc708c1990f2fc1d941bb82efcb0a697524f2eca Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/15483 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-06-28 21:14:33 +02:00
case LPSS_DEVFN_I2C5:
soc/intel/apollolake: add code to disable unused device Parse the devicetree and pass the unused device to fsp for disabling the device function. BRANCH=none BUG=chrome-os-partner:54325 TEST=device off in devicetree should disable the device. Change-Id: I784b72a43fda13aa17634bf680205ab2d36e8d09 Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com> Reviewed-on: https://review.coreboot.org/15337 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-06-23 03:32:17 +02:00
silconfig->I2c5Enable = 0;
break;
soc/intel/apollolake: Change PCI macros to match Skylake Change PCI macros in such a way they can be transparently used across romstage and ramstage. Change-Id: Idc708c1990f2fc1d941bb82efcb0a697524f2eca Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/15483 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-06-28 21:14:33 +02:00
case LPSS_DEVFN_I2C6:
soc/intel/apollolake: add code to disable unused device Parse the devicetree and pass the unused device to fsp for disabling the device function. BRANCH=none BUG=chrome-os-partner:54325 TEST=device off in devicetree should disable the device. Change-Id: I784b72a43fda13aa17634bf680205ab2d36e8d09 Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com> Reviewed-on: https://review.coreboot.org/15337 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-06-23 03:32:17 +02:00
silconfig->I2c6Enable = 0;
break;
soc/intel/apollolake: Change PCI macros to match Skylake Change PCI macros in such a way they can be transparently used across romstage and ramstage. Change-Id: Idc708c1990f2fc1d941bb82efcb0a697524f2eca Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/15483 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-06-28 21:14:33 +02:00
case LPSS_DEVFN_I2C7:
soc/intel/apollolake: add code to disable unused device Parse the devicetree and pass the unused device to fsp for disabling the device function. BRANCH=none BUG=chrome-os-partner:54325 TEST=device off in devicetree should disable the device. Change-Id: I784b72a43fda13aa17634bf680205ab2d36e8d09 Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com> Reviewed-on: https://review.coreboot.org/15337 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-06-23 03:32:17 +02:00
silconfig->I2c7Enable = 0;
break;
soc/intel/apollolake: Change PCI macros to match Skylake Change PCI macros in such a way they can be transparently used across romstage and ramstage. Change-Id: Idc708c1990f2fc1d941bb82efcb0a697524f2eca Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/15483 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-06-28 21:14:33 +02:00
case LPSS_DEVFN_UART0:
soc/intel/apollolake: add code to disable unused device Parse the devicetree and pass the unused device to fsp for disabling the device function. BRANCH=none BUG=chrome-os-partner:54325 TEST=device off in devicetree should disable the device. Change-Id: I784b72a43fda13aa17634bf680205ab2d36e8d09 Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com> Reviewed-on: https://review.coreboot.org/15337 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-06-23 03:32:17 +02:00
silconfig->Hsuart0Enable = 0;
break;
soc/intel/apollolake: Change PCI macros to match Skylake Change PCI macros in such a way they can be transparently used across romstage and ramstage. Change-Id: Idc708c1990f2fc1d941bb82efcb0a697524f2eca Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/15483 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-06-28 21:14:33 +02:00
case LPSS_DEVFN_UART1:
soc/intel/apollolake: add code to disable unused device Parse the devicetree and pass the unused device to fsp for disabling the device function. BRANCH=none BUG=chrome-os-partner:54325 TEST=device off in devicetree should disable the device. Change-Id: I784b72a43fda13aa17634bf680205ab2d36e8d09 Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com> Reviewed-on: https://review.coreboot.org/15337 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-06-23 03:32:17 +02:00
silconfig->Hsuart1Enable = 0;
break;
soc/intel/apollolake: Change PCI macros to match Skylake Change PCI macros in such a way they can be transparently used across romstage and ramstage. Change-Id: Idc708c1990f2fc1d941bb82efcb0a697524f2eca Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/15483 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-06-28 21:14:33 +02:00
case LPSS_DEVFN_UART2:
soc/intel/apollolake: add code to disable unused device Parse the devicetree and pass the unused device to fsp for disabling the device function. BRANCH=none BUG=chrome-os-partner:54325 TEST=device off in devicetree should disable the device. Change-Id: I784b72a43fda13aa17634bf680205ab2d36e8d09 Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com> Reviewed-on: https://review.coreboot.org/15337 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-06-23 03:32:17 +02:00
silconfig->Hsuart2Enable = 0;
break;
soc/intel/apollolake: Change PCI macros to match Skylake Change PCI macros in such a way they can be transparently used across romstage and ramstage. Change-Id: Idc708c1990f2fc1d941bb82efcb0a697524f2eca Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/15483 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-06-28 21:14:33 +02:00
case LPSS_DEVFN_UART3:
soc/intel/apollolake: add code to disable unused device Parse the devicetree and pass the unused device to fsp for disabling the device function. BRANCH=none BUG=chrome-os-partner:54325 TEST=device off in devicetree should disable the device. Change-Id: I784b72a43fda13aa17634bf680205ab2d36e8d09 Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com> Reviewed-on: https://review.coreboot.org/15337 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-06-23 03:32:17 +02:00
silconfig->Hsuart3Enable = 0;
break;
soc/intel/apollolake: Change PCI macros to match Skylake Change PCI macros in such a way they can be transparently used across romstage and ramstage. Change-Id: Idc708c1990f2fc1d941bb82efcb0a697524f2eca Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/15483 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-06-28 21:14:33 +02:00
case LPSS_DEVFN_SPI0:
soc/intel/apollolake: add code to disable unused device Parse the devicetree and pass the unused device to fsp for disabling the device function. BRANCH=none BUG=chrome-os-partner:54325 TEST=device off in devicetree should disable the device. Change-Id: I784b72a43fda13aa17634bf680205ab2d36e8d09 Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com> Reviewed-on: https://review.coreboot.org/15337 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-06-23 03:32:17 +02:00
silconfig->Spi0Enable = 0;
break;
soc/intel/apollolake: Change PCI macros to match Skylake Change PCI macros in such a way they can be transparently used across romstage and ramstage. Change-Id: Idc708c1990f2fc1d941bb82efcb0a697524f2eca Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/15483 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-06-28 21:14:33 +02:00
case LPSS_DEVFN_SPI1:
soc/intel/apollolake: add code to disable unused device Parse the devicetree and pass the unused device to fsp for disabling the device function. BRANCH=none BUG=chrome-os-partner:54325 TEST=device off in devicetree should disable the device. Change-Id: I784b72a43fda13aa17634bf680205ab2d36e8d09 Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com> Reviewed-on: https://review.coreboot.org/15337 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-06-23 03:32:17 +02:00
silconfig->Spi1Enable = 0;
break;
soc/intel/apollolake: Change PCI macros to match Skylake Change PCI macros in such a way they can be transparently used across romstage and ramstage. Change-Id: Idc708c1990f2fc1d941bb82efcb0a697524f2eca Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/15483 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-06-28 21:14:33 +02:00
case LPSS_DEVFN_SPI2:
soc/intel/apollolake: add code to disable unused device Parse the devicetree and pass the unused device to fsp for disabling the device function. BRANCH=none BUG=chrome-os-partner:54325 TEST=device off in devicetree should disable the device. Change-Id: I784b72a43fda13aa17634bf680205ab2d36e8d09 Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com> Reviewed-on: https://review.coreboot.org/15337 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-06-23 03:32:17 +02:00
silconfig->Spi2Enable = 0;
break;
case SDCARD_DEVFN:
silconfig->SdcardEnabled = 0;
break;
case EMMC_DEVFN:
silconfig->eMMCEnabled = 0;
break;
case SDIO_DEVFN:
silconfig->SdioEnabled = 0;
break;
case SMBUS_DEVFN:
silconfig->SmbusEnable = 0;
break;
default:
printk(BIOS_WARNING, "PCI:%02x.%01x: Could not disable the device\n",
PCI_SLOT(dev->path.pci.devfn),
PCI_FUNC(dev->path.pci.devfn));
break;
}
}
static void parse_devicetree(struct FSP_S_CONFIG *silconfig)
{
soc/intel/apollolake: Change PCI macros to match Skylake Change PCI macros in such a way they can be transparently used across romstage and ramstage. Change-Id: Idc708c1990f2fc1d941bb82efcb0a697524f2eca Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/15483 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-06-28 21:14:33 +02:00
struct device *dev = NB_DEV_ROOT;
soc/intel/apollolake: add code to disable unused device Parse the devicetree and pass the unused device to fsp for disabling the device function. BRANCH=none BUG=chrome-os-partner:54325 TEST=device off in devicetree should disable the device. Change-Id: I784b72a43fda13aa17634bf680205ab2d36e8d09 Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com> Reviewed-on: https://review.coreboot.org/15337 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-06-23 03:32:17 +02:00
if (!dev) {
printk(BIOS_ERR, "Could not find root device\n");
return;
}
/* Only disable bus 0 devices. */
for (dev = dev->bus->children; dev; dev = dev->sibling) {
if (!dev->enabled)
disable_dev(dev, silconfig);
}
}
soc/intel/apollolake: Add chip initialization Change-Id: I54532b71c7649f7eeccbb2213b31418cfdbfb00c Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/13911 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-03-05 06:41:13 +01:00
void platform_fsp_silicon_init_params_cb(struct FSPS_UPD *silupd)
{
struct FSP_S_CONFIG *silconfig = &silupd->FspsConfig;
static struct soc_intel_apollolake_config *cfg;
/* Load VBT before devicetree-specific config. */
soc/intel/apollolake: Take advantage of common opregion code Change-Id: I2d16336513bcd5a0544a6b68b609e40dd7c141fb Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/14807 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-13 04:11:48 +02:00
silconfig->GraphicsConfigPtr = (uintptr_t)vbt;
soc/intel/apollolake: Add chip initialization Change-Id: I54532b71c7649f7eeccbb2213b31418cfdbfb00c Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/13911 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-03-05 06:41:13 +01:00
soc/intel/apollolake: Change PCI macros to match Skylake Change PCI macros in such a way they can be transparently used across romstage and ramstage. Change-Id: Idc708c1990f2fc1d941bb82efcb0a697524f2eca Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/15483 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-06-28 21:14:33 +02:00
struct device *dev = NB_DEV_ROOT;
intel/apollolake: Fix logic error Testing dev->chip == NULL when dev == NULL doesn't make sense (and gcc thinks that's undefined behavior which should be rewarded with a trap). Change-Id: I801ce3d6b791fdf96b23333432dee394aa2e2ddf Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/14360 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-04-14 11:53:48 +02:00
if (!dev || !dev->chip_info) {
soc/intel/apollolake: Add chip initialization Change-Id: I54532b71c7649f7eeccbb2213b31418cfdbfb00c Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/13911 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-03-05 06:41:13 +01:00
printk(BIOS_ERR, "BUG! Could not find SOC devicetree config\n");
return;
}
cfg = dev->chip_info;
soc/intel/apollolake: add code to disable unused device Parse the devicetree and pass the unused device to fsp for disabling the device function. BRANCH=none BUG=chrome-os-partner:54325 TEST=device off in devicetree should disable the device. Change-Id: I784b72a43fda13aa17634bf680205ab2d36e8d09 Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com> Reviewed-on: https://review.coreboot.org/15337 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-06-23 03:32:17 +02:00
/* Parse device tree and disable unused device*/
parse_devicetree(silconfig);
soc/intel/apollolake: Add chip initialization Change-Id: I54532b71c7649f7eeccbb2213b31418cfdbfb00c Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/13911 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-03-05 06:41:13 +01:00
silconfig->PcieRpClkReqNumber[0] = cfg->pcie_rp0_clkreq_pin;
silconfig->PcieRpClkReqNumber[1] = cfg->pcie_rp1_clkreq_pin;
silconfig->PcieRpClkReqNumber[2] = cfg->pcie_rp2_clkreq_pin;
silconfig->PcieRpClkReqNumber[3] = cfg->pcie_rp3_clkreq_pin;
silconfig->PcieRpClkReqNumber[4] = cfg->pcie_rp4_clkreq_pin;
silconfig->PcieRpClkReqNumber[5] = cfg->pcie_rp5_clkreq_pin;
soc/intel/apollolake: Update platform-specific FSP headers This updates FSP UPD headers that adds new fields. Importantly there are new FSPS UPD fields that allow to specify some BARs. They are needed by FSP SiliconInit API to work properly. Change-Id: Ie268c57c66b4d8fd6e00835916004058ff05762e Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/14217 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-03-18 22:43:00 +01:00
soc/intel/apollolake: Add EMMC DLL API Starting from 136_30,FSP supports to update all the SDIO DLL programming value through silicon init upd. Implement the interface to pass board specific programming value to fsp silicon init. Change-Id: Ifd901148f3f7f89f966217491c661ec346337c38 Signed-off-by: Zhao, Lijian <lijian.zhao@intel.com> Reviewed-on: https://chromium.devtools.intel.com/7372 Reviewed-by: Petrov, Andrey <andrey.petrov@intel.com> Tested-by: Petrov, Andrey <andrey.petrov@intel.com> Reviewed-on: https://chromium.devtools.intel.com/7585 Reviewed-on: https://review.coreboot.org/15084 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-18 04:01:34 +02:00
if (cfg->emmc_tx_cmd_cntl != 0)
silconfig->EmmcTxCmdCntl = cfg->emmc_tx_cmd_cntl;
if (cfg->emmc_tx_data_cntl1 != 0)
silconfig->EmmcTxDataCntl1 = cfg->emmc_tx_data_cntl1;
if (cfg->emmc_tx_data_cntl2 != 0)
silconfig->EmmcTxDataCntl2 = cfg->emmc_tx_data_cntl2;
if (cfg->emmc_rx_cmd_data_cntl1 != 0)
silconfig->EmmcRxCmdDataCntl1 = cfg->emmc_rx_cmd_data_cntl1;
if (cfg->emmc_rx_strobe_cntl != 0)
silconfig->EmmcRxStrobeCntl = cfg->emmc_rx_strobe_cntl;
if (cfg->emmc_rx_cmd_data_cntl2 != 0)
silconfig->EmmcRxCmdDataCntl2 = cfg->emmc_rx_cmd_data_cntl2;
soc/apollolake: Add ish_enable in soc_intel_apollolake_config Also initialize IshEnable in Silicon Init UPD with the value from devicetree.cb Signed-off-by: Hannah Williams <hannah.williams@intel.com> Change-Id: I8f57a7353471cc3efa21c7011cdd0b369d25275d Reviewed-on: https://review.coreboot.org/14894 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-03-28 23:45:59 +02:00
silconfig->IshEnable = cfg->integrated_sensor_hub_enable;
intel/apollolake: Disable setting of EISS bit in FSP chrome-os-partner:54589 Change-Id: I5bdd417ed2f7ec013aeb8a0d4a9de57b1ad564a1 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/15276 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-21 01:08:42 +02:00
soc/apollolake: Allow enable/disable of LPSS S0ix from devicetree Change-Id: Ib7aa1d1b32adcb541a155b8ba2ee011cb5bcf784 Signed-off-by: Saurabh Satija <saurabh.satija@intel.com> Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/15055 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-05-04 00:15:31 +02:00
silconfig->LPSS_S0ixEnable = cfg->lpss_s0ix_enable;
intel/apollolake: Disable setting of EISS bit in FSP chrome-os-partner:54589 Change-Id: I5bdd417ed2f7ec013aeb8a0d4a9de57b1ad564a1 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/15276 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-21 01:08:42 +02:00
/* Disable setting of EISS bit in FSP. */
silconfig->SpiEiss = 0;
soc/intel/apollolake: Add chip initialization Change-Id: I54532b71c7649f7eeccbb2213b31418cfdbfb00c Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/13911 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-03-05 06:41:13 +01:00
}
struct chip_operations soc_intel_apollolake_ops = {
CHIP_NAME("Intel Apollolake SOC")
.enable_dev = &enable_dev,
soc/intel/apollolake: Take advantage of common opregion code Change-Id: I2d16336513bcd5a0544a6b68b609e40dd7c141fb Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/14807 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-13 04:11:48 +02:00
.init = &soc_init,
.final = &soc_final
soc/intel/apollolake: Add chip initialization Change-Id: I54532b71c7649f7eeccbb2213b31418cfdbfb00c Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/13911 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-03-05 06:41:13 +01:00
};
static void fsp_notify_dummy(void *arg)
{
enum fsp_notify_phase ph = (enum fsp_notify_phase) arg;
soc/intel/apollolake: Add handling of global reset in FspNotify stage Call basic FSP reset handling in FspNotify stage. Handling of reset requests for other stages need to be implemented as well. BUG=chrome-os-partner:54149 BRANCH=none TEST=with FSP that returns reset codes, do cold boot, check that reboot sequence occurs properly. Change-Id: I55542aa37e60edb17ca24ac358b61df72679b83e Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/15280 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-23 04:32:51 +02:00
enum fsp_status ret;
soc/intel/apollolake: Add chip initialization Change-Id: I54532b71c7649f7eeccbb2213b31418cfdbfb00c Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/13911 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-03-05 06:41:13 +01:00
soc/intel/apollolake: Add handling of global reset in FspNotify stage Call basic FSP reset handling in FspNotify stage. Handling of reset requests for other stages need to be implemented as well. BUG=chrome-os-partner:54149 BRANCH=none TEST=with FSP that returns reset codes, do cold boot, check that reboot sequence occurs properly. Change-Id: I55542aa37e60edb17ca24ac358b61df72679b83e Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/15280 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-23 04:32:51 +02:00
if ((ret = fsp_notify(ph)) != FSP_SUCCESS) {
printk(BIOS_CRIT, "FspNotify failed, ret = %x!\n", ret);
if (fsp_reset_requested(ret))
fsp_handle_reset(ret);
}
soc/apollolake: Put CSE to low power state fsp_notify(END_OF_FIRMWARE) should be sent to FSP to enable putting CSE in low power state Change-Id: I76b8e85ccf077032616ba8e4a333d9264dc65ed2 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/15054 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-04-29 23:48:20 +02:00
/* Call END_OF_FIRMWARE Notify after READY_TO_BOOT Notify */
soc/intel/apollolake: handle p2sb quirks The P2SB device is device 0xd and function 0. If hidden that causes the latter pci devices on function >= 1 to not be probed in the kernel. This is also a problem for coreboot if the P2SB device is hidden by FSP. That means the coreboot driver won't be ran. Therefore, provide hide and unhide functions for the P2SB device. The other quirk is to allow the GPIO devices to work correctly. Those devices are ACPI devices. However, their resources are sub-regions within the P2SB BAR. Sadly, linux doesn't handle ACPI devices being children of PCI devices. This leads to resource conflict errors when the P2SB device is visible. For the time being keep the P2SB device hidden, but also ensure the resources it is using are accounted for and reserved. The fallout of that is the PMC and SPI device are no longer probed by the kernel. BUG=chrome-os-partner:53017 TEST=Ensured P2SB device is visible and pci resources are allocated correctly for the devices. Change-Id: I24e59bbde74310e1ce8425b344a3ad0b88702153 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15530 Tested-by: build bot (Jenkins) Reviewed-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-01 23:36:03 +02:00
if (ph == READY_TO_BOOT) {
soc/apollolake: Put CSE to low power state fsp_notify(END_OF_FIRMWARE) should be sent to FSP to enable putting CSE in low power state Change-Id: I76b8e85ccf077032616ba8e4a333d9264dc65ed2 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/15054 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-04-29 23:48:20 +02:00
fsp_notify_dummy((void *)END_OF_FIRMWARE);
soc/intel/apollolake: handle p2sb quirks The P2SB device is device 0xd and function 0. If hidden that causes the latter pci devices on function >= 1 to not be probed in the kernel. This is also a problem for coreboot if the P2SB device is hidden by FSP. That means the coreboot driver won't be ran. Therefore, provide hide and unhide functions for the P2SB device. The other quirk is to allow the GPIO devices to work correctly. Those devices are ACPI devices. However, their resources are sub-regions within the P2SB BAR. Sadly, linux doesn't handle ACPI devices being children of PCI devices. This leads to resource conflict errors when the P2SB device is visible. For the time being keep the P2SB device hidden, but also ensure the resources it is using are accounted for and reserved. The fallout of that is the PMC and SPI device are no longer probed by the kernel. BUG=chrome-os-partner:53017 TEST=Ensured P2SB device is visible and pci resources are allocated correctly for the devices. Change-Id: I24e59bbde74310e1ce8425b344a3ad0b88702153 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15530 Tested-by: build bot (Jenkins) Reviewed-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-01 23:36:03 +02:00
/* Hide the P2SB device to align with previous behavior. */
p2sb_hide();
}
soc/intel/apollolake: Add chip initialization Change-Id: I54532b71c7649f7eeccbb2213b31418cfdbfb00c Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/13911 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-03-05 06:41:13 +01:00
}
BOOT_STATE_INIT_ENTRY(BS_DEV_RESOURCES, BS_ON_EXIT, fsp_notify_dummy,
(void *) AFTER_PCI_ENUM);
BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, fsp_notify_dummy,
(void *) READY_TO_BOOT);
BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, fsp_notify_dummy,
(void *) READY_TO_BOOT);
intel/apollolake: Enable SPI properly in bootblock and ramstage Bootblock: - Temporary BAR needs to be assigned for SPI device until PCI enumeration is done by ramstage which allocates a new BAR. - Call spi_init to allow bootblock/verstage to write/erase on flash. Ramstage: - spi_init needs to run in ramstage to allow write protect to be disabled for eventlog and NVRAM updates. This needs to be done pretty early so that any init calls(e.g. mainboard_ec_init) writing to flash work properly. Verified with this change that there are no more flash write/erase errors for ELOG/NVRAM. BUG=chrome-os-partner:54283 Change-Id: Iff840e055548485e6521889fcf264a10fb5d9491 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/15209 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com> Tested-by: build bot (Jenkins)
2016-06-16 02:13:20 +02:00
/*
* spi_init() needs to run unconditionally on every boot (including resume) to
* allow write protect to be disabled for eventlog and nvram updates. This needs
* to be done as early as possible in ramstage. Thus, add a callback for entry
* into BS_PRE_DEVICE.
*/
static void spi_init_cb(void *unused)
{
spi_init();
}
BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, spi_init_cb, NULL);
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