coreboot-kgpe-d16/src/soc/intel/cannonlake/Kconfig

config SOC_INTEL_CANNONLAKE
	bool
	help
	  Intel Cannonlake support

if SOC_INTEL_CANNONLAKE

config CPU_SPECIFIC_OPTIONS
	def_bool y
	select ACPI_INTEL_HARDWARE_SLEEP_VALUES
	select ARCH_BOOTBLOCK_X86_32
	select ARCH_RAMSTAGE_X86_32
	select ARCH_ROMSTAGE_X86_32
	select ARCH_VERSTAGE_X86_32
	select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH
	select BOOT_DEVICE_SUPPORTS_WRITES
	select C_ENVIRONMENT_BOOTBLOCK
	select COMMON_FADT
	select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
	select GENERIC_GPIO_LIB
	select HAVE_HARD_RESET
	select HAVE_INTEL_FIRMWARE
	select HAVE_MONOTONIC_TIMER
	select INTEL_CAR_NEM_ENHANCED
	select PARALLEL_MP
	select PARALLEL_MP_AP_WORK
	select PLATFORM_USES_FSP2_0
	select POSTCAR_CONSOLE
	select POSTCAR_STAGE
	select REG_SCRIPT
	select RELOCATABLE_RAMSTAGE
	select SMP
	select SOC_INTEL_COMMON
	select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
	select SOC_INTEL_COMMON_BLOCK
	select SOC_INTEL_COMMON_BLOCK_ACPI
	select SOC_INTEL_COMMON_BLOCK_CAR
	select SOC_INTEL_COMMON_BLOCK_CPU
	select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT
	select SOC_INTEL_COMMON_BLOCK_CSE
	select SOC_INTEL_COMMON_BLOCK_FAST_SPI
	select SOC_INTEL_COMMON_BLOCK_GPIO
	select SOC_INTEL_COMMON_BLOCK_GSPI
	select SOC_INTEL_COMMON_BLOCK_LPSS
	select SOC_INTEL_COMMON_BLOCK_PCR
	select SOC_INTEL_COMMON_BLOCK_PMC
	select SOC_INTEL_COMMON_BLOCK_RTC
	select SOC_INTEL_COMMON_BLOCK_SA
	select SOC_INTEL_COMMON_BLOCK_SMBUS
	select SOC_INTEL_COMMON_BLOCK_SMM
	select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP
	select SOC_INTEL_COMMON_BLOCK_TIMER
	select SOC_INTEL_COMMON_BLOCK_UART
	select SOC_INTEL_COMMON_SPI_FLASH_PROTECT
	select SOC_INTEL_COMMON_RESET
	select SUPPORT_CPU_UCODE_IN_CBFS
	select TSC_CONSTANT_RATE
	select TSC_MONOTONIC_TIMER
	select UDELAY_TSC

config UART_DEBUG
	bool "Enable UART debug port."
	default y
	select CONSOLE_SERIAL
	select BOOTBLOCK_CONSOLE
	select DRIVERS_UART
	select DRIVERS_UART_8250MEM_32
	select NO_UART_ON_SUPERIO

config UART_FOR_CONSOLE
	int "Index for LPSS UART port to use for console"
	default 2 if DRIVERS_UART_8250MEM
	default 0
	help
	    Index for LPSS UART port to use for console:
	    0 = LPSS UART0, 1 = LPSS UART1, 2 = LPSS UART2

config DCACHE_RAM_BASE
	default 0xfef00000

config DCACHE_RAM_SIZE
	default 0x40000
	help
	  The size of the cache-as-ram region required during bootblock
	  and/or romstage.

config DCACHE_BSP_STACK_SIZE
	hex
	default 0x4000
	help
	  The amount of anticipated stack usage in CAR by bootblock and
	  other stages.

config IED_REGION_SIZE
	hex
	default 0x400000

config MAX_ROOT_PORTS
	int
	default 24

config SMM_TSEG_SIZE
	hex
	default 0x800000

config PCR_BASE_ADDRESS
	hex
	default 0xfd000000
	help
	  This option allows you to select MMIO Base Address of sideband bus.

config CPU_BCLK_MHZ
	int
	default 100

config SOC_INTEL_COMMON_BLOCK_GSPI_MAX
	int
	default 3

# Clock divider parameters for 115200 baud rate
config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL
	hex
	default 0x30

config SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL
	hex
	default 0xc35

config CHROMEOS
	select CHROMEOS_RAMOOPS_DYNAMIC

config VBOOT
	select VBOOT_SEPARATE_VERSTAGE
	select VBOOT_OPROM_MATTERS
	select VBOOT_SAVE_RECOVERY_REASON_ON_REBOOT
	select VBOOT_STARTS_IN_BOOTBLOCK
	select VBOOT_VBNV_CMOS
	select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH

endif