Commit Graph

17637 Commits

Author SHA1 Message Date
Martin Roth 0cf7acc688 nvramcui: Cast u8 * values to char * to eliminate warnings
error: pointer targets of 'strcmp' differ in signedness
expected 'const char *' but argument is of type
'u8 * {aka unsigned char *}'

Change-Id: Id5cbb6fc2efd7c57abc59b08416047e10461436f
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/14521
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-05-03 20:00:07 +02:00
Patrick Georgi 06a0b567ce intel/baytrail: use fmap information for code caching
Instead of using CBFS_SIZE from Kconfig, use values generated from fmap.
While at it, make sure that the cached region size is a power of two.

fmap_config is also added to cpu_incs-y, but that doesn't hurt (except
for some miniscule increase in compile time) because it's #if-guarded.
The upside is that dependencies are tracked properly.

Change-Id: I03a919e1381ca3d0e972780b2c7d76c590aaa994
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/14573
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-05-03 19:01:10 +02:00
Patrick Georgi 58a150a1a3 lib/cbfs: Use fmap derived information about the COREBOOT region
It used to use CONFIG_CBFS_SIZE. The plan is that CBFS_SIZE only informs
default*.fmd generation, while everything else derives its information
from there.

Also document the existing assumption that boot media should access the
COREBOOT region (and not any other potentially existing fmap region
containing a CBFS).

Change-Id: I08254e4510f71edf99c2c8b56ac8f92008727c4a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/14572
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-03 19:00:36 +02:00
Patrick Georgi 919be612b8 fmaptool: Export some fmap knowledge to the build environment
By exporting base and offset of CBFS-formatted fmap regions, the code
can use these when it's not prudent to do a runtime lookup.

Change-Id: I20523b5cea68880af4cb1fcea4b37bb8ac2a23db
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/14571
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-03 11:42:45 +02:00
Patrick Georgi 849635d4ef build system: rename fmap.h to fmap_config.h
There's an in-tree fmap.h, and the file generated by fmaptool is likely
used in tandem with it. To avoid problems, rename the generated file
(which so far isn't used).

Change-Id: I95dfde513a7f78677cf18ecd7ce8745e40af316b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/14570
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-03 11:42:20 +02:00
Patrick Georgi fa5aba0484 arch/x86: Drop CBFS_BASE_ADDRESS
It's unused.

Change-Id: I50af2b50d2c5a7a24afe9099c5c01d17ce54a6c9
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/14569
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-03 11:41:55 +02:00
Patrick Georgi 6f07ff10d1 southbridge/amd: Drop HUDSON_FWM_INSIDE_CBFS
It's unused.

Change-Id: I853702e40dcab9f193b2a3de7deeec80ab1d25f0
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/14568
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-03 11:41:07 +02:00
Patrick Georgi 5cc0ee270c build system: remove CBFSTOOL_PRE1_OPTS
It isn't used anymore.

Change-Id: Ie554d1dd87ae3f55547466e484c0864e55c9d102
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/14567
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-05-03 11:40:49 +02:00
Stefan Tauner 127c131754 .gitignore: add build and libpayload dirs for nvramcui payload
Change-Id: I8a29ca1b07df68b50ab54276c9d9b32a81308e02
Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at>
Reviewed-on: https://review.coreboot.org/14562
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-05-03 04:16:45 +02:00
Stefan Tauner 98ab22711d xcompile: test if gcc is really available
Just because an 'as' with a certain prefix is available does not guarantee
that a 'gcc' with the same prefix is available as well.

Without a check detect_compiler_runtime() would try to execute an
unavailable binary and print something like this:
.../xcompile: line 218: arm-linux-gnueabi-gcc: command not found

Change-Id: Icbadfeb2860152f7cf7696a9122521d0d881f3aa
Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at>
Reviewed-on: https://review.coreboot.org/14563
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-05-03 04:16:24 +02:00
Jonathan Neuschäfer 2d67d12570 board_status/towiki: Link to CGit instead of Gitweb
Gitweb isn't online anymore, so fix a few broken links.

Change-Id: I7fdfcb60f83a718c9a5b6c7f7ef4df9206451d95
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/14559
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-05-03 04:13:35 +02:00
Lee Leahy eee0e22976 soc/intel/quark: Remove UPD parameters
Remove the UPD parameters to match QuarkFsp code.

TEST=Build and run on Galileo Gen2

Change-Id: Ie4639d1f087cc2bc4387aa691eb66b640fe8faf9
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/14451
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-02 22:04:54 +02:00
Aaron Durbin 0e55632661 cpu/x86/mp_init: remove unused callback arguments
The BSP and AP callback declarations both had an optional argument
that could be passed. In practice that functionality was never used
so drop it.

Change-Id: I47fa814a593b6c2ee164c88d255178d3fb71e8ce
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/14556
Tested-by: build bot (Jenkins)
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-05-02 20:07:25 +02:00
Aaron Durbin ddf4fa0cc3 drivers/intel/fsp1_1: fix linking romstage when SEPARATE_VERSTAGE used
The skylake-based Chromebooks use a separate verstage which runs
just after bootblock and prior to romstage. However, that
config is not enabled for coreboot.org so when
C_ENVIRONMENT_BOOTBLOCK changes were done it wasn't observed
that the Chromebook config failed because 2 _start symbols
were present. Remedy this failure by using the common
car_stage_entry symbol for taking over control flow.

Change-Id: I3f29b90ba8e3786b2106a34e49e6d1f9831dcc7c
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/14549
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
2016-05-02 20:06:58 +02:00
Aaron Durbin aef586548a arch/x86/assembly_entry: allow early post CAR stages to use common code
The skylake-based Chromebooks use a separate verstage which runs
just after bootblock and prior to romstage. The normal path for
romstage would be to reload the gdt, however in the previously
described scenario has verstage performing that work. Therefore,
provide that path under those conditions. The only difference
from the C_ENVIRONMENT_BOOTBLOCK scenario is that the stack
should not be reloaded since there's no way to know the top
of the stack.

Change-Id: Ic39ab52a856233d3042ac02a15ae4816ddfe07c7
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/14548
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
2016-05-02 20:06:23 +02:00
Aaron Durbin 800b0173c9 arch/x86/asembly_entry: reorder conditional stage entry macros
The path that just clears CAR_GLOBAL variables and jumps
to the stage entry point needs another condition for
separate verstage just after bootblock. However, the
current conditional is a negative conditional so
swap the logic around to make it easier to extend.

Change-Id: Iab6682498054715a6eaa0476390da6355238b9bc
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/14547
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
2016-05-02 20:04:56 +02:00
Aaron Durbin a6e9051bc6 lib/coreboot_table: use the architecture dependent table size
Utilize the architecture dependent coreboot table size value
from <arch/cbconfig.h>

Change-Id: I80d51a5caf7c455b0b47c380e1d79cf522502a4c
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/14455
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
2016-05-02 20:03:34 +02:00
Aaron Durbin a2118a21c9 arch: introduce architecture dependent common variables
Stefan and others have discussed their interest in only
including options in Kconfig that are directly associated
with building a coreboot image. There are variables that
are architecture dependent that are utilized in the
coreboot infrastructure. To meet that goal, introduce
<arch/cbconfig.h> header file which defines variables
for the coreboot infrastructure that are architecture
dependent but utilized in common infrastructure.

Change-Id: Ic4cb9e81bab042797539dce004db0f7ee8526ea6
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/14454
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
2016-05-02 19:51:47 +02:00
Timothy Pearson 394041b149 nb/amd/mct_ddr3: Only initialize ECC bits once
The ECC check bits of all ECC DIMMS were inadvertently initialized
twice in the same routine, significantly delaying startup.  Part
of this was related to an obsolete MCA workaround that has been
fixed through multiple commits, therefore the workaround is no
longer needed.

Only initialize the ECC check bits once.

Change-Id: I90ac1147d9b006794d29b866a9cb5b7ead8f01e7
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/14503
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-05-02 16:17:52 +02:00
Furquan Shaikh 4c76ab678a x86/memlayout.h: Do not include data/bss sections in C_ENVIRONMENT_BOOTBLOCK
C_ENVIRONMENT_BOOTBLOCK on x86 is like romstage and uses cache-as-ram
separately. It does not use any data/bss sections.

Change-Id: I8957f467f01e754fa2d95783466a01daa6c4e51a
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/14533
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
2016-05-02 04:22:53 +02:00
Jonathan Neuschäfer 2a8adac7f5 romcc.1: Point bug reporters to the coreboot ML / bug tracker
Change-Id: Ic0866a5183c64070ef35b21ba00586bc65dfcde8
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/14538
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-05-01 16:29:09 +02:00
Jonathan Neuschäfer f03217b6bb payloads/nvramcui: Make the makefile non-executable
Change-Id: Id584cbf02c9d3ecb89fcf2a3190f0a73816954a8
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/14526
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-05-01 16:28:56 +02:00
Jonathan Neuschäfer 5b724d48bc mb/emulation/*/board_info.txt: Update QEMU URL
Change-Id: If4d57c7898c0de20035533dccd4554f45a71d5d1
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/14525
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-05-01 16:25:01 +02:00
Timothy Pearson ac6bd5b037 nb/amd/mct_ddr3: Warn if MaxRdLatency training fails on Family 15h
Change-Id: Idb948acd1a508379f600fbd2fd40fb26b7571d7c
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/14545
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-01 00:50:47 +02:00
Timothy Pearson 2bb1d30d69 nb/amd/mct_ddr3: Stop receiver enable cycle training after window found
During receiver enable cycle training on Family 15h the entire range
of possible delays is searched, even though the single passing window
is often found nearly immediately.  Skip the remainder of the delay
range after the passing window has been located.

Change-Id: If98217fa8e7de77366762d3c7bb01049a1dc080f
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/14544
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-01 00:50:21 +02:00
Timothy Pearson 29dd5da1dc nb/amd/mct_ddr3: Do not constantly reset read data timing registers to 0
During DQS receiver enable cycle training on Family 15h platforms the
read data timing registers were inadvertently set to zero on every
lane training attempt.

Ensure that the read data timing registers are correctly set after
each lane is trained in receiver enable cycle training.  This allows
more than one RDIMM to function on a given DCT channel.

Change-Id: I87d732f0383e9785a73b57e6f48855f3e872f1f9
Tested-On: ASUS KGPE-D16
Tested-With: 1x Opteron 6262HE
Tested-With: 4x Crucial 36KSF1G72PZ-1G6M1 (slots A2 / A1 / B2 / B1)
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/14543
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-01 00:50:05 +02:00
Timothy Pearson 263c679075 nb/amd/mct_ddr3: Skip nibble training when current DIMM is not x4
Change-Id: I1f5b024606093dc81de3f3d69b7a43e20141b709
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/14542
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-01 00:49:40 +02:00
Timothy Pearson 7f731f8d4f nb/amd/mct_ddr3: Fix x4 DIMM receiver enable training on Fam15h
The existing Family 15h receiver enable training code stored
temporary delay values in the wrong variables, leading to
the requisite averaging of delays across nibbles not being
applied.  This in turn made x4 DIMMs less stable than they
should have been.

Store temporary nibble delay values in a dedicated array.

Change-Id: Ic5da898af7d689db4110211f89b886ccdbb5f78f
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/14541
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-01 00:49:24 +02:00
Lee Leahy efcee9fadd lib/reg_script: Allow multiple independent handlers
Remove the platform_bus_table routine and replace it with a link time
table.  This allows the handlers to be spread across multiple modules
without any one module knowing about all of the handlers.

Establish number ranges for both the SOC and mainboard.

TEST=Build and run on Galileo Gen2

Change-Id: I0823d443d3352f31ba7fa20845bbf550b585c86f
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/14554
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2016-04-30 20:44:58 +02:00
Lee Leahy 6bcbe5749b lib/regscript: Add exclusive-or (xor) support
Add xor support which enables toggling of a bit:
* REG_SCRIPT_COMMAND_RXW enum value
* REG_*_RXW* macros to support using REG_SCRIPT_COMMAND_RXW
* REG_*_XOR* macros to support using REG_SCRIPT_COMMAND_RXW
* reg_script_rxw routine to perform and/xor operation
* case in reg_script_run_step to call reg_script_rxw

TEST=Build and run on Galileo Gen2

Change-Id: I50a492c7c2643df5dc2d2fa7113e3722c1e480c7
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/14495
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-04-30 15:40:20 +02:00
Hannah Williams 733b39aed4 soc/apollolake: Prevent PMC BAR reassignment during resource allocation
Change-Id: Ie8e21e62ecd25f3c620a57c24948411c14c1e111
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/14315
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-04-30 02:34:29 +02:00
Aaron Durbin 80a3df2607 soc/intel/apollolake: clarify Fast SPI CS2 pad configuration
The pad for CS2 of the Fast SPI interface needs to be configured for
automatic MMIO translation when a SPI TPM is utilized. Instead of
unconditionally configuring that pad under LPC_TPM provide a explicit
Kconfig for a mainboard to select.

Change-Id: Ia94b90e12d71a4b849359188a853f7e036cc583b
Signed-off-by: Aaron Durbin <adurbin@chormium.org>
Reviewed-on: https://review.coreboot.org/14531
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
Tested-by: build bot (Jenkins)
2016-04-29 19:49:09 +02:00
Patrick Rudolph 588ccaa9a7 nb/intel/sandybridge/raminit: fix regression "always use mrccache"
Fix regression introduced by:
Ib48fe8380446846df17d37b22968f7d4fd6b9b13

Don't run channel_test on S3 resume as it overrides memory
that might be in use.
Fixes MCE events reported by the GNU/Linux kernel that
low memory has been modified.

Reset on failed s3 resume.

Change-Id: Ibadea286619c7906225f86a93aaa0b4caf26cabe
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/14439
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-04-29 13:11:35 +02:00
Werner Zeh fa6f861b57 siemens/mc_bdx1: Add new mainboard.
Add new mainboard for MC BDX1 board which is based on Intel Camelback
Mountain. This mainboard is an industry type board and has several
Ethernet interfaces among with two USB3.0 connectors. It uses 24V DC
power supply and has its own form factor which does not match any
standard.
This commit adds the new mainboard and prepares the Kconfig
environment so that this board can be selected and generated.
Although the generated image can boot into Linux and DOS,
not all functions are implemented yet.
Forthcoming commits will add more functionality.

Change-Id: I29011cfd3b0d13bcf163223f657e02f69978e39a
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/14516
Tested-by: build bot (Jenkins)
Reviewed-by: York Yang <york.yang@intel.com>
2016-04-29 06:29:54 +02:00
Timothy Pearson 09e3bfbd8b nb/amd/mct_ddr3: Restart system on training failure instead of using die()
DIMM training can sporadically fail due to external influences or various
errata.  In these cases, restarting to retry training is a more appropriate
response than halting the system and requiring manual intervention.

Change-Id: Id49f7419f56e0640a84448cc06ecbaf62bed145e
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/14529
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-04-28 20:04:54 +02:00
Jonathan Neuschäfer 8f407f695e Add board URLs for the RISC-V boards
Change-Id: Ifdf40986c2407d8c5b0097654b42e056f4498d39
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/14518
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-28 19:19:27 +02:00
Jonathan Neuschäfer d6d50099e0 Fix "Spike RISCV" board name
Change-Id: If0f835e69862a78433e7c1a34efa4706cc27b214
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/14517
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-28 19:19:15 +02:00
Werner Zeh 7611e7e2f1 fsp_baytrail: Fix missing "$" when using Kconfig switch
To include gfx.c in ramstage, there is a Kconfig option
(FSP_BAYTRAIL_GFX_INIT) which can be activated on demand.
Unfortunately, the "$"-character is missing so that this switch is
never active.

Change-Id: I0c3c562b3caca53ac6510c2c5dc30e7f606f5ad0
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/14532
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-04-28 19:11:52 +02:00
Werner Zeh 608d991cf8 drivers/intel/i210: Use uint8_t and friends instead of u8
Switch all types to uint8_t and the like instead of u8.

Change-Id: Ia12c4ee9e21e2d3166c2f895c819357fa2ed9a94
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/14515
Tested-by: build bot (Jenkins)
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-04-28 08:25:23 +02:00
Werner Zeh bf13d3f567 mc_tcu3: Switch to hwilib instead of own hwinfo implementation
Use hwilib in vendorcode/siemens/hwilib to get fields from hwinfo
instead of having mainboard specific hwinfo code.
This patch does not change the functional behavior in any way.

Change-Id: Idb226a82a08b1b753f654c5cde106236e72f33c3
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/14506
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-04-28 08:16:05 +02:00
Werner Zeh 223498fa16 vendorcode/siemens: Add hwilib for Siemens specific info struct
Add a library which unifies access to Siemens specific hardware information
data. This library is meant to be used with Siemens platforms and can be
selected in Kconfig. The needed source of information has to be present
in cbfs.
This lib can be used in romstage and ramstage.

Change-Id: I2c6e003b0c123b4cf6a84906c2b133b8c38c8b1a
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/14505
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2016-04-28 08:15:47 +02:00
Lance Zhao 1bd0c0c497 soc/intel/apollolake: Add handling of GNVS ACPI entry for CHROMEOS builds
Add chromeos required GNVS feature. The GNVS table stays in both CBMEM
and ACPI DSDT tables.

Change-Id: I4db0eb18d2de62917a94704318a7896c04e4777f
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/14471
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-04-28 05:47:30 +02:00
Zhao, Lijian 164e8f1d9b soc/intel/apollolake: Add GPIO devices
Add GPIO controller in ACPI device description.

GPIO controller driver is probed in kernel and all
the pins in the banks are showing respective values.

Change-Id: I0512cfec872113b15fd204ec3b95efeac87f694a
Signed-off-by: Zhao, Lijian <lijian.zhao@intel.com>
Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com>
Reviewed-on: https://review.coreboot.org/14478
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-04-28 05:46:00 +02:00
Andrey Petrov 0c85b7f4d7 soc/intel/apollolake: Add cache for BIOS ROM
Enable caching of BIOS region with variable MTRR. This is most
useful if enabled early such as in bootblock.

Change-Id: I39f33ca43f06fce26d1d48e706c97f097e3c10f1
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/14480
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2016-04-28 05:45:37 +02:00
Andrey Petrov e976bd4469 soc/intel/apollolake: Enable LPC bus interface
This adds early LPC setup in bootblock (for Chrome EC) as well as
late (ramstage) IO decode/sirq enable.

Change-Id: Ic270e66dbf07240229d4783f80e2ec02007c36c2
Signed-off-by: Divya Sasidharan <divya.s.sasidharan@intel.com>
Signed-off-by: Freddy Paul <freddy.paul@intel.com>
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/14469
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-04-28 05:38:34 +02:00
Andrey Petrov f748f83ecb soc/intel/apollolake: Enable RAM cache for cbmem region in ramstage
Use postcar infrastructure to enable caching of area where ramstage
runs.

Change-Id: I3f2f6e82f3b9060c7350ddff754cd3dbcf457671
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/14095
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-04-28 05:16:02 +02:00
Zhao, Lijian 2b9a5f5688 soc/intel/apollolake: Fix northbridge _crs scope
Move _CRS scope from MCHC device only to whole pci root bus. Otherwise
ACPI will not able to assign resource to devices other than MCHC.

Change-Id: Iaa294c63e03a4fc6644f1be5d69ab3de077e6cc3
Signed-off-by: Zhao, Lijian <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/14477
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-04-28 05:14:47 +02:00
Divya Sasidharan cbf1a0fec8 mainboard/amenia: Enable Chrome EC Interface/Keyboard
Enabled LPC channel between host and EC.
Superio.asl will enable proper probing of onboard keyboard.

Change-Id: I57014fc90b345661853280ae3402f86e56af5fb9
Signed-off-by: Divya Sasidharan <divya.s.sasidharan@intel.com>
Signed-off-by: Freddy Paul <freddy.paul@intel.com>
Reviewed-on: https://review.coreboot.org/14468
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-04-28 05:13:54 +02:00
Andrey Petrov 4520c5e757 soc/intel/apollolake: Configure a GPIO for TPM in bootblock
One of devices connected to FAST SPI bus is TPM. SoC uses dedicated
line for chip select for TPM function. If TPM is used, that line needs
to be configured to a specific native funciton.

Change-Id: Ib5bf4c759adf9656f7b34540d4fc924945d27a97
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/14467
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-04-28 05:11:23 +02:00
Andrey Petrov 1ba068550d soc/intel/apollolake: Avoid marking 0xe0000-0xfffff region usable
coreboot writes RDSP at 0xf0000. Since depthcharge wipes usable
memory regions before starting, kernel can't find RDSP.

Change-Id: I584bd5d24248cf38f46342615cf3b0252a821b2a
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/14466
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-04-28 05:11:11 +02:00