Commit Graph

36918 Commits

Author SHA1 Message Date
Ben Chuang ff17b31dfb drivers/genesyslogic/gl9755: Add driver for Genesys Logic GL9755
The device is a PCIe Gen2 to SD 4.0 card reader controller to be
used in the Chromebook. The datasheet name is GL9755S and the revision
is 05.

The patch sets LTR value.

Signed-off-by: Ben Chuang <benchuanggli@gmail.com>
Change-Id: I16048dde348be248c748d50ca4a8a62c8a781430
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45062
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-09-18 15:49:15 +00:00
Malik_Hsu 8ad2b8be25 mb/google/volteer/eldrid: Add option to enable WiFi SAR configs
This change adds a user selectable option to enable all WiFi SAR
configs that apply to volteer

BUG=b:168169690
TEST=1. cros-workon-volteer start
          coreboot-private-files-baseboard-volteer
     2. USE="project_eldrid" emerge-volteer chromeos-config
          coreboot-private-files-baseboard-volteer
     3. check wifi_sar-eldrid.hex in
          coreboot-private/3rdparty/blobs/baseboard-volteer

Change-Id: I6b74cd2b34ebb99cc59d456e28fd7ab2399d71d0
Signed-off-by: Malik_Hsu <malik_hsu@wistron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45233
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-18 15:46:26 +00:00
Yilin Yang 46eaa5a1ba util/rockchip: Port make_idb.py to python3
BUG=chromium:1023662
TEST=buildbot pass
TEST=1. Use python2 script
     2. Run `emerge-kevin coreboot` twice, so we get bootblock.bin.1
     and bootblock.bin.2
     3. Run `xxd` on these two bootblock so we get bootblock.bin.1.hex
     and bootblock.bin.2.hex
     4. `diff bootblock.bin.1.hex bootblock.bin.2.hex` and record the
     difference. (at least, the time info changes)
     5. Migrate to python3
     6. Similar steps, we get bootblock.bin.py3.hex
     7. `diff bootblock.bin.1.hex bootblock.bin.py3.hex`, the difference
     is similar. (time info, git hash changes)

Signed-off-by: Yilin Yang <kerker@google.com>
Change-Id: I04253084ec9b65310c52598b629390051cd2172b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45447
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-18 13:30:05 +00:00
Angel Pons 12beaea5e2 superio/nuvoton: Inline `nuvoton_hwm_select_bank`
There's no need to place a single-line function in its own compilation
unit, and then guard it behind a Kconfig symbol. This also allows using
this function in stages other than ramstage.

Change-Id: I103a4ea4cef24844d382854c9358bbb37d229e04
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42130
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-18 12:37:36 +00:00
Angel Pons 64a6b6cb1f src/include: Add PnP/HWM unset_and_set functions
RMW (read/modify/write) ops on PnP devices has never been so simple.

The semantics also allow the compiler to emit valid warnings if the
input parameters would overflow, which are silenced when the cast is
placed outside of the function.

Change-Id: Ica01211af2a9a00aed98880844a836f6b7957b14
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42134
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-18 12:06:38 +00:00
Yilin Yang 1502494cba util/exynos: Port *_cksum.py to python3
BUG=chromium:1023662
TEST=1. Create a tiny file `in.txt` as input
     2. Run `fixed_cksum.py in.txt out.txt 20` with py2 and py3 version,
     the output is the same
     3. Run `variable_cksum.py in.txt out.txt` with py2 and py3 version,
     the output is the same

Signed-off-by: Yilin Yang <kerker@google.com>
Change-Id: I9428269dfb826a3a95fffef9ea3f7c1a7107ef84
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45460
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-09-18 08:00:39 +00:00
Yilin Yang f944e619dd util/mtkheader: Port gen-bl-img.py to python3
BUG=chromium:1023662
TEST=1. Use python2 script
     2. Run `emerge-asurada coreboot` twice, so we get bootblock.bin.1
     and bootblock.bin.2
     3. Run `xxd` on these two bootblock so we get bootblock.bin.1.hex
     and bootblock.bin.2.hex
     4. `diff bootblock.bin.1.hex bootblock.bin.2.hex` and record the
     difference. (at least, the time info changes)
     5. Migrate to python3
     6. Similar steps, we get bootblock.bin.py3.hex
     7. `diff bootblock.bin.1.hex bootblock.bin.py3.hex`, the difference
     is similar.

Signed-off-by: Yilin Yang <kerker@google.com>
Change-Id: I788e7c9b09257142728a0f76df8c2ccc72bf6b3b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45440
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-09-18 08:00:22 +00:00
Yu-Ping Wu 541f2f74a3 libpayload: cbgfx: Fix 'equals' counter for Lanczos resampling
The current initialization of the 'equals' counter is incorrect, so that
when 'equals >= SSZ * SSZ', the pixels in the sample array might not be
all the same, leading to a wrong pixel value being set in the
framebuffer.

The 'equals' counter stores the number of latest pixels that were
exactly equal. Within the for loop of 'ox', the sample array is updated
in a column-based order, and the 'equals' counter is updated
accordingly. However, the 'equals' counter is initialized in a row-based
order, which causes it to be set too large than it should be. Consider
the example where sample[sx][sy] are initially:

 [X X X A A A]  // sy = 0
 [X X X B B B]
 [X X X B B B]
 [X X X B B B]
 [X X X B B B]
 [X X X B B B]  // sy = SSZ

Then, the correct implementation will initialize 'equals' to be 15, with
last_equal being B. Suppose all of the remaining pixels are B. Then, at
the end of the 'while (fpfloor(ixfp) > ix)' loop when ix = 4, or
equivalently after 4 more columns of sample are updated, 'equals' will
be 15 + 6 * 4 = 39, which is greater than SSZ * SSZ = 36, but we can see
there are still 2 A's in the sample:

 [B B B B A A]
 [B B B B B B]
 [B B B B B B]
 [B B B B B B]
 [B B B B B B]
 [B B B B B B]

Therefore, we must also initialize the 'equals' counter in a
column-based order.

BUG=b:167739127
TEST=emerge-puff libpayload
TEST=Character 'k' is rendered correctly on puff
BRANCH=zork

Change-Id: Ibc91ad1af85adcf093eff40797cd54f32f57111d
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45235
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-09-18 01:35:35 +00:00
Michael Niewöhner 5d1a328e88 soc/intel/cannonlake: add missing special function pads
The following parameters do nothing else than configuring the
corresponding pads to native mode:

- DdiPortEdp
- DdiPort*Hpd
- DdiPort*Ddc
- GpioDdp*
- SpiGpioAssign
- I2c*GpioAssign
- SerialIoUartDebugEnable
- Gp*GpioAssign
- Uart*GpioAssign
- GpioEnableHdaLink
- AudioLinkDmic*
- AudioLinkSsp*
- GpioEnableHdaSspMasterClock
- AudioLinkSndw*
- SmbAlertEnable

Add the missing special function gpio pad groups for CNL, to be able to
configure them via gpio.h instead having to set various FSP parameters.

The groups and names are documented in the PCH EDS, in Linux
(linux/drivers/pinctrl/intel/pinctrl-cannonlake.c) and other places.

Also, see soc/intel/tigerlake for reference.

Change-Id: Ia3bc1df1a14dbca7c7213577cb2d5b98bb0acf64
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45211
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2020-09-17 21:53:38 +00:00
Jeremy Soller b349f258a9 mb/system76/lemp9: update power limits
Tested on lemp9, power limits are adjusted from the previously low
values to the values the thermal system can handle. This was
determined by increasing the values and running the system at 100%
CPU utilization until thermal throttling occured and the chassis
temperature became uncomfortable.

Signed-off-by: Jeremy Soller <jeremy@system76.com>
Change-Id: I5e176e9d98376f8e2dc415e4397efc456869e72d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43624
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-17 21:37:11 +00:00
Michael Niewöhner d7775b763f mb/system76/lemp9: disable PCH DMIC, which is not wired
The microphone is wired to the audio codec, not to the PCH. Disable the
DMIC interface.

Change-Id: I4128a694c1a66d3c2c2d1cb831fcca3487160f8f
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45133
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-17 21:35:32 +00:00
Michael Niewöhner 1c2b1b977a soc/intel/cannonlake: rename "RSVD" GPIOs to their correct names
The names of the GPIO_RSVD_* are documented in the PCH EDS, in Linux
(linux/drivers/pinctrl/intel/pinctrl-cannonlake.c) and other places.

Also, see soc/intel/tigerlake for reference.

Change-Id: I59df09c8fd464e75f918455aa1972765abc51459
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45210
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2020-09-17 21:13:29 +00:00
Jeremy Soller 748bfac734 mb/system76/lemp9: skip FSP init of UART2
This UART is already initialized by coreboot for the console, it does
not need to be initialized by the FSP.

Tested on lemp9.

Signed-off-by: Jeremy Soller <jeremy@system76.com>
Change-Id: I7c299fd7cf6fe53d1f500a899a14e63e51ad6266
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43676
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-09-17 20:47:49 +00:00
Angel Pons 75594e9ff7 nb/intel/haswell: Put DMIBAR/EPBAR registers into separate files
Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical.

Change-Id: Ib68d8b88b0d79cb33d42f9e21cfb0e57abae75e8
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45355
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-17 20:22:31 +00:00
Angel Pons e4156c33bd nb/intel/haswell: Move register headers into a subfolder
Move all files with register definitions into a `registers` subfolder.
Subsequent commits will move the remaining registers into this folder.

Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical.

Change-Id: I143b3c829be44a39e14902255cd4bb13bf02f0c1
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45354
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-17 20:22:17 +00:00
Angel Pons b8b117c7e7 nb/intel/x4x: Clean up TPM-related code
Perform the read to the TPM base address using <arch/mmio.h> functions.
Remove dead variable assignment and rename TPM base address macro.

Tested with BUILD_TIMELESS=1. Asus P5QL PRO remains identical.

Change-Id: I11d737903c57fce768b760fe717564dae8879ad0
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45389
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-09-17 20:00:17 +00:00
Angel Pons 6549661b9c nb/intel/pineview: Guard DMIBAR/EPBAR macro parameters
Add brackets around the parameters to avoid operation order problems.

Tested with BUILD_TIMELESS=1, Foxconn D41S remains identical.

Change-Id: I347466f56d3d5fb3793b3a25e4a825c844e50d42
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45386
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-09-17 19:59:59 +00:00
Angel Pons d25e2f6c80 nb/intel/pineview/iomap.h: Rename to memmap.h
It primarily contains definitions for MMIO windows.

Change-Id: I8cd639c8c7d400a5bfd73735113dd27dd6f948e6
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45385
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-09-17 19:59:48 +00:00
Angel Pons 298d34d8ff nb/intel/ironlake: Do not re-read ME UMA size
It has been read twice already, so don't read it a third time.

Change-Id: I56ec3a10246f6ebe8074e7b8c164bda6b90eee87
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45363
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-09-17 19:59:29 +00:00
Angel Pons 8690746efb nb/intel/ironlake: Drop some unused function parameters
Some of the HECI functions do not need raminfo at all.

Change-Id: If0720fa87e5e18820db77a1b61bcdb42ecc538fb
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45362
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-09-17 19:59:13 +00:00
Angel Pons d02f3303d9 nb/intel/ironlake: Drop `heci_bar` field from raminit
This field is only written to, never read. Drop it from raminfo.
Also, bump MRC_CACHE_VERSION as the saved data layout has changed.

Change-Id: I83d6e69addff996e2f18472d3e1d4f7b9ba974fd
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45361
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-09-17 19:59:04 +00:00
Angel Pons 122e4ebd7d nb/intel/haswell: Clean up register definitions
Several registers have been copy-pasted from i945 and do not exist on
Haswell. Moreover, other register definitions were missing. Although
most of them are unused, native platform init may eventually use them.

Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical.

Change-Id: I6b3a47b2af406da6b030d417f14a2f4d394aa9c8
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45353
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-17 19:58:33 +00:00
Angel Pons e5ec50c236 nb/intel/haswell: Guard DMIBAR/EPBAR macro parameters
Add brackets around the parameters to avoid operation order problems.

Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical.

Change-Id: I5e1a02ba2ebf468f0d80b7f1838766280b6b7b22
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45352
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-17 19:58:00 +00:00
Angel Pons a3cb322018 nb/intel/haswell: Introduce memmap.h
Move all memory map definitions into a separate header.

Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical.

Change-Id: Ib275f9ad8ca9ff343604c9e8cbb130c74ddad54f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45351
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-17 19:57:50 +00:00
Angel Pons 743159396a nb/intel/sandybridge: Drop `void *` cast in `MCHBAR32`
This changes the binary for the native raminit code path.

Tested on Asus P8Z77-V LX2, still boots with native raminit.

Change-Id: Ie8f1205a64e5264cb909d67c1dd402c18a6241ad
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45350
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-17 19:57:37 +00:00
Matt Papageorge ec0fb40893 Update amd_blobs submodule to upstream master
Updating from commit id 3bd9078:
2020-08-12 17:03:38 -0600 - (picasso: Update PSP to 0.8.6.7B)

to commit id e393a88:
2020-09-16 14:32:50 +0000 - (Update SMU firmware for Picasso, Pollock and Dali)

This brings in 1 new commits.

Change-Id: I1e317cf6ef4803577e9b353fb3313d001db228d7
Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45455
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-17 19:46:18 +00:00
Angel Pons c8027454ba nb/intel/sandybridge: Drop casts from DEFAULT_{MCHBAR,DMIBAR}
This allows us to drop some casts to uintptr_t around the tree.
The MCHBAR32 macro still needs a cast to preserve reproducibility.
Only the native raminit path needs the cast, the MRC path does not.

Tested with BUILD_TIMELESS=1, these boards remain identical:
 - Lenovo ThinkPad X230
 - Dell OptiPlex 9010
 - Roda RW11 (with MRC raminit)

Change-Id: I8ca1c35e2c1f1b4f0d83bd7bb080b8667dbe3cb3
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45349
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-17 19:35:19 +00:00
Angel Pons 92717ff3e4 nb/intel/sandybridge: Drop invalid `DEFAULT_RCBABASE` macro
RCBA is located in the PCH. Replace all instances with the
already-defined `DEFAULT_RCBA` macro, which is equivalent.

Change-Id: I4b92737820b126d32da09b69e09675464aa22e31
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45348
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-17 19:35:03 +00:00
Angel Pons 10240510a7 nb/intel/ironlake: Drop invalid `DEFAULT_RCBABASE` macro
This macro is unused, and RCBA is located in the PCH. Drop it.

Change-Id: Id7c095496360bbe96dc2a36dcc557a1481c02c31
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45347
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-17 19:34:54 +00:00
Michael Niewöhner 1d7b7f6e7a mb/system76/lemp9: move HDA options into devicetree
Change-Id: Id4fc12896f89739d0ee2a47a42173693921da14e
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45132
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-17 19:24:30 +00:00
Shreesh Chhabbi 7fbcdb3f9a mb/volteer: Select USE_CAR_NEM_ENHANCED_V2 for Tigerlake QS based
platforms

BUG=b:145958015
TEST= Build Volteer coreboot and boot on Volteer Proto 2 and Delbin.

Cq-Depend:chrome-internal-review:3249528
Change-Id: I0ff896424ab23dba43075c44eb9b2c2c480ccbfb
Signed-off-by: Shreesh Chhabbi <shreesh.chhabbi@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45456
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2020-09-17 19:04:28 +00:00
nick_xr_chen 5200063114 mb/google/volteer/variants/eldrid: Configure DP_HPD as PAD_NC
GPP_A19(DP_HPD1) and GPP_A20(DP_HPD2) were configured native function
(NF1) without internal pull-down which wrongly presents HPD interrupts.
This change configures GPP_A19 and GPP_A20 to be no connection and
disables DdiPort1Hpd and DdiPort2Hpd.

BUG=b:165893624, b:168090618

Signed-off-by: nick_xr_chen <nick_xr_chen@wistron.corp-partner.google.com>
Change-Id: I31b25be1c9248debf855435c7b688b358e2cd57e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45246
Reviewed-by: Scott Chao <scott_chao@wistron.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-17 18:20:53 +00:00
Elyes HAOUAS 72fc9a3e26 src: Remove redundant <device/pnp_type.h>
When <device/pnp.h> is needed, it is supposed to provide <device/pnp_type.h>.

Change-Id: I0e479e2abdb6cfb8633840db2222ce5397fe7d55
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45403
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-17 13:22:44 +00:00
Elyes HAOUAS 4b683b85a8 src: Remove redundant <device/pnp_def.h>
When <device/pnp.h> is needed, it is supposed to provide <device/pnp_def.h>.
So remove redundant <device/pnp_def.h> includes.
I'll remove also <device/pnp_type.h> in a separate patch.

Change-Id: Ib9903ae456c32db4ba346020659c17c27a939e89
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45316
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-09-17 13:21:48 +00:00
Rob Barnes 28cb14bf13 soc/amd/picasso: Clean up legacy UART config
Clean up configuration of the legacy UART and add Kconfig options for
the mapping between UART and legacy I/O decode.

BUG=b:143283592
BUG=b:153675918
TEST=Linux detects an additional legacy serial port for each active MMIO
one if PICASSO_UART_LEGACY is selected.
BRANCH=zork

Signed-off-by: Rob Barnes <robbarnes@google.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id08ff6428d4019303ebb6e44e13aba480cf1fde2
Reviewed-on: https://chromium-review.googlesource.com/2037891
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40322
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-09-17 12:35:56 +00:00
Michael Niewöhner 60795784b7 soc/intel/cannonlake: fix GPIO community numbering in ACPI
This corrects the GPIO community numbers in CNL-LP ACPI code.

Change-Id: I9f13a28d3e8f427859570a4d209304ae8444efd9
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45209
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-17 10:36:31 +00:00
Subrata Banik 7938ebc7d7 soc/intel/common/block/chip: Refactor chip_get_common_soc_structure()
Found-by: Klocwork, Pointer soc_config is used uninitialized.

Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: I7e2aa4ef23a68a2ec2ba9d55cf890a7f81e3e278
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45416
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-17 09:57:06 +00:00
Subrata Banik 754de4da37 soc/intel/common/block: Add NULL check for 'ctx' pointer
Found-by: Klocwork, Avoid NULL pointer (ctx) dereference.

Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: I16015b538112e0b125b4a5e145c26263c456953c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45411
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-17 09:56:56 +00:00
CK Hu 804b3bd10f soc/mediatek/mt8192: Init PLL in bootblock
Signed-off-by: CK Hu <ck.hu@mediatek.com>
Change-Id: If16d244e07d9f369efd991132587a92e38200b45
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45395
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-09-17 06:56:55 +00:00
Weiyi Lu fd3c727ed9 soc/mediatek/mt8192: Add mtcmos init support
Using common mtcmos code to power on audio and display modules in SOC.

TEST=Boots correctly on MT8192EVB. Passes the status check at the end of
     mtcmos_power_on()

Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
Change-Id: Ie7bff831eecfc2b4d315a577f6ff86befc483eab
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45394
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-17 06:56:31 +00:00
Chris Wang 7ef7596569 mb/google/zork: Add dptc interface support for morphius
Add dptc interface in devicetree for morphius.
Set the STAPM parameters for tablet mode:

    dptc_enable = 1
    dptc_fast_ppt_limit = 24000
    dptc_slow_ppt_limit = 20000
    dptc_sustained_power_limit = 6000

BUG=b:157943445
BRANCH=zork
TEST=Build. check the setting changed.

Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: I4dac4b7e5157ad7ad407f42a6fc6b06eefbf3291
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45153
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-09-17 06:19:07 +00:00
Chris Wang e019bd910f ec/google/chromeec: Add dptc interface support
add the dptc interface support when system in tablet mode.
In some FP5/FT5 platform, which will have different power or thermal
parameters depends on different form factor.

BUG=b:157943445
BRANCH=Zork
TEST=Build. check the setting changed.

Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: I2be7942132cea474237f531021ad4fd9856b5050
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44265
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-17 06:18:59 +00:00
Chris Wang 4735b1c01b soc/amd/picasso: add dptc support
add dptc support for different power parameter on tablet/clamshell mode

The BIOS may choose to adjust power and/or thermal parameters at its own
discretion. The DPTC interface(DPTCi) ALIB Function adds flexibility by
allowing  the BIOS to request power state changes independently of specific
 events.

BUG=b:157943445
BRANCH=none
TEST=Build.Generated ASL code from SSDT by acipgen_dptci().check the setting changed.

Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: Icae94103f254f8fdb84e6ee0f5404fb09fa97b2d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43408
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-09-17 06:05:27 +00:00
Angel Pons 2ce386a3c2 soc/intel/common/block: Do not die if PRMRR size unsupported
If a given PRMRR size is not supported, do NOT brick people's devices.
We don't do that when PRMRRs aren't even supported anyway.

Change-Id: Ib917be873aedbc5e789bb0894fca335b5ee9e2c2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45373
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2020-09-16 20:56:35 +00:00
Shelley Chen 2d90ddd2d2 region_file_update_data_arr: Modify region_file with array of buffers
Add region_file_update_data_arr, which has the same functionality as
region_file_update_data, but accepts mutliple data buffers.  This is
useful for when we have the mrc_metadata and data in non-contiguous
addresses, which is the case when we bypass the storing of mrc_cache
data into the cbmem.

BUG=b:150502246
BRANCH=None
TEST=reboot from ec console.  Make sure memory training happens.
     reboot from ec console.  Make sure that we don't do training again.

Change-Id: Ia530f7d428b9b07ce3a73e348016038d9daf4c15
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45407
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-16 16:02:54 +00:00
Felix Held a79e01bf71 soc/amd/picasso/data_fabric: make register number parameter unsigned
The register number is always non-negative, so it should be an unsigned
type.

Change-Id: I6b6df5a41fe58efc53eaa87c01b88426ea8daa6e
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45430
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-09-16 14:47:15 +00:00
Felix Held bf90b14d6a soc/amd/picasso/data_fabric: include types.h
data_fabric.c uses types from stdint.h, but doesn't include stdint.h
directly, so replace the inclusion of stdbool.h with types.h which
includes both stdbool.h and stdint.h.

Change-Id: I4c1ea444e50218cf19fc8fff499929336265bd03
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45429
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
2020-09-16 14:47:04 +00:00
Marc Jones 5cb7599ca1 xeon_sp/skx: Reorder pci_devs.h
Reorder to be similar to cpx/include/soc/pci_devs.h.
We may be able to merge the files in the future.

Checked TiogaPass with BUILD_TIMELESS=1

Change-Id: I939707cc9e58e23f053156f40df4c21a6072570b
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45220
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-16 10:18:59 +00:00
Marc Jones 8015482f67 xeon_sp/cpx/pci_devs.h: Remove duplicate defines
Change-Id: I8fc4e07269175eb2f40655b828e340697a9a892a
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45219
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-16 10:18:44 +00:00
Weiyi Lu 0fed84b8c4 soc/mediatek: move power status bits under each chip
The power status bits of display and audio of MT8192 are different
from the bits of MT8173 & MT8183, so move those under each chip.

Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
Change-Id: Iaa211b8db733d8aa52d93af9e507042bf0984d55
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45393
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-09-16 07:48:20 +00:00