Commit Graph

36918 Commits

Author SHA1 Message Date
Caveh Jalali 3b616e4bde mb/google/volteer: Fix GPP_E12 definition
GPP_E12 should not be defined in the baseboard as its use is
determined by the variant. For legacy reasons, we still have GPP_E12
defined in early_gpio but should not. Malefor and volteer* have the
same GPP_E12 definition, but that is a misconfiguration. I think that
was a copy-paste that slipped through the reviews.

BUG=b:157597158
TEST=volteer2 boots to the OS

Change-Id: Ic3ef864827aa94b0b96e335565119f3d5d008837
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45197
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2020-09-14 07:04:45 +00:00
David Wu a545d30831 mb/google/volteer/var/voxel: Update DPTF parameters and TCC offset
1. Set tcc offset to 5 degree celsius
2. Apply the DPTF parameters received from the thermal team.

BUG=b:167523658
TEST=build and verify by thermal team

Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I01a6fc5bd959798c8dd423df3907c69c883733e8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45111
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-09-14 07:04:34 +00:00
Tim Wawrzynczak a5cb5649fb mb/google/volteer: Refactor baseboard devicetree
Clean up the DPTF section of the baseboard devicetree; this makes
overrides simpler, as not necessarily all of the fields need to be
overridden.

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Iad46fd02f7602c9419d7c3674b0d2b6f5add9a93
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45179
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-14 07:04:28 +00:00
Sumeet R Pawnikar 426e07aaf2 mb/google/dedede/variants/drawcia: Increase PL2 value from 15W to 20W
Jasper Lake SoC supports PL2 (Power Limit2) as 20W. Increase PL2 value from 15W to 20W.

BRANCH=None
BUG=b:166656373
TEST=Built and tested on drawlat system

Change-Id: I82d6792907bb1c88cc9dd57d1eaeda8421c12fb2
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45162
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-14 07:04:07 +00:00
Anil Kumar 033038fd48 soc/intel/tigerlake: Increase PRERAM_CBMEM_CONSOLE_SIZE to 8KB
This patch increases PRERAM_CBMEM_CONSOLE_SIZE from 5KB to 8KB to fix
cbmem buffer overflow issue.

Bug=None
Branch=None
Test=Boot TGLRVP and check cbmem -c | grep 'CBFS: Locating' lists all stages

Signed-off-by: Anil Kumar <anil.kumar.k@intel.com>
Change-Id: I2393cc83008211be8e6a2ca7a1e41a7e9d92caf0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45183
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-14 07:03:47 +00:00
John Zhao 623da4bc5d mb/google/volteer: Add error handling
Coverity detects missing error handling after calling function
tlcl_lib_init. This change checks the function tlcl_lib_init return
value and handles error properly.

Found-by: Coverity CID 1432491
TEST=None

Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: Ife38b1450451cb25e5479760d640375db153e499
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45176
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-14 07:03:33 +00:00
David Wu d944f1797f mb/google/volteer: Enable EC software sync
Enable EC software sync for terrador and todor

BUG=None
TEST=emerge-volteer coreboot chromeos-bootimage

Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I8c463eadd19d99dc04923f7400560cf7ba4b8101
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45186
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2020-09-14 07:03:20 +00:00
Shreesh Chhabbi 121bc7a674 soc/intel/tigerlake: Select USE_CAR_NEM_ENHANCED_V2 for tigerlake
Selects Cache QoS mask MSR programming flow for Tigerlake SoC.

BUG=b:145958015
TEST= Build and boot to Chrome OS on TGL-UP3 RVP.
Recipe used:
1. Patch https://review.coreboot.org/c/coreboot/+/43494 that
implements calculation of CQOS mask dynamically based on stack
size usage & incorporates Tigerlake SoC specific programming flow.
2. QS Engineering Microcode based on 0x56 Official Microcode with
LLC CQOS change.
3. QS SoC Part

Signed-off-by: Shreesh Chhabbi <shreesh.chhabbi@intel.corp-partner.google.com>
Change-Id: I602d93eb4f8243ec49993b00691140d9a6cf5733
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45094
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-09-14 07:02:44 +00:00
Aamir Bohra c1d227d312 soc/intel/common/cpu: Update COS mask calculation for NEM enhanced mode
Update the COS mask calculation to accomodate the RW data as per SoC
configuration. Currently only one way is allocated for RW data and
configured for non-eviction. For earlier platform this served fine,
and could accomodate a RW data up to 256Kb. Starting TGL and JSL, the
DCACHE_RAM_SIZE is configured for 512Kb, which cannot be mapped to a
single way. Hence update the number of ways to be configured for non-
eviction as per total LLC size.

The total LLC size/ number of ways gives the way size. DCACHE_RAM_SIZE/
way size gives the number of ways that need to be configured for non-
eviction, instead of harcoding it to 1.

TGL uses MSR IA32_CR_SF_QOS_MASK_1(0x1891) and IA32_CR_SF_QOS_MASK_2(0x1892)
as COS mask selection register and hence needs to be progarmmed accordingly.

Also JSL and TGL platforms the COS mask selection is mapped to bit 32:33
of MSR IA32_PQR_ASSOC(0xC8F) and need to be updated in edx(maps 63:32)
before MSR write instead of eax(maps 31:0). This implementation corrects
that as well.

BUG=b:149273819
TEST= Boot waddledoo(JSL), hatch(CML), Volteer(TGL)with NEM enhanced
      CAR configuration.

Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Change-Id: I54e047161853bfc70516c1d607aa479e68836d04
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43494
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shreesh Chhabbi <shreesh.chhabbi@intel.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-09-14 07:02:26 +00:00
Martin Roth 1ba86f685b utils/docker/coreboot-sdk: Update python to python2, add python3
The latest debian image needs the python2 package specified instead of
just 'python'.  Also add python3 to the builder as we'll probably be
getting python3 scripts before too long.

Change-Id: Iceea3981b1e219141bf06ad0b559cdbf1c98b360
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45265
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-09-13 23:14:16 +00:00
Yu-Ping Wu aec3b1f7d7 libpayload: malloc: Fix realloc for overlapping buffers
The current realloc() works by freeing the origin buffer, allocating a
new one, and copying the data over. It's true that free() won't touch
the actual memory. However, the alloc() following it will potentially
modify the memory that belongs to the old buffer in order to create a
new free block (right after the newly allocated block). This causes 8
bytes (HDRSIZE) to be overwritten before being copied to the new buffer.

To fix the problem, we must create the header of the new free block
after the data is copied. In this patch, the content of alloc() is split
into two functions:

1. find_free_block(): Find a free block with large enough size, without
   touching the memory
2. use_block(): Update the header of the newly allocated block, and
   create the header of the new free block right after it

Then, inside realloc(), call memmove() call right after
find_free_block() while before use_block().

BUG=b:165439970
TEST=emerge-puff libpayload
TEST=Puff boots
TEST=Verified realloc() correctly copied data when buffers overlapped

Change-Id: I9418320a26820909144890300ddfb09ec2570f43
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45284
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-09-13 13:40:11 +00:00
Felix Held 828a36e325 soc/amd/picasso/chip: fix typo in acp_pme_enable
That devicetree setting is about the Audio Co-Processor and not ACPI.

BRANCH=zork

Change-Id: I7f376371ee094392d4434340c77f0fc8d0d8e4e1
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45300
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-09-13 00:04:10 +00:00
Felix Held 6c61b4b3ac soc/amd/picasso/aoac: make AOAC device number unsigned
The AOAC device number is never negative, so make it unsigned.

BRANCH=zork

Change-Id: I3e0d15a646f02da5767504471961d5d9f8f28bea
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45308
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-13 00:03:34 +00:00
Felix Held 2617073ee0 soc/amd/picasso/uart: make AOAC device ID in uart_enable unsigned
This change is separate from CB:45308 to only have the directly UART-
related changes in this patch train.

BRANCH=zork

Change-Id: Ie587fdbd1e6229c1374fce3568c6a361577dc6c4
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45310
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-09-13 00:01:38 +00:00
Felix Held 2e800038ab soc/amd/picasso/uart: add missing types.h include
BRANCH=zork

Change-Id: I51923d72a2ad8dceeef11e15fb6765262dd514d9
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45309
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-09-13 00:01:12 +00:00
Angel Pons 1b89f5eeab soc/intel/common/block/*/Kconfig: Guard options with if-blocks
The usual structure of these files is a global enable symbol, usually
followed by an if-block which contains all other dependent symbols.

Use this instead of having a `depends on` line to each symbol. Guard all
symbols, even if they originally were not guarded, since they don't do
anything useful unless the global enable option is selected.

Change-Id: If5347187b07a46192f0063011ab197b5047f555f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45043
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-12 23:00:12 +00:00
Idwer Vollering 042edd389b Update vboot submodule to upstream master
Updating from commit id fefcaa65:
    vboot: adjust VB2_SECDATA_KERNEL_FLAGS in non-recovery path

to commit id 4bb06cc1:
    COIL: Change denylist to blocklist

This brings in 20 new commmits.

Signed-off-by: Idwer Vollering <vidwer@gmail.com>
Change-Id: I0efef2f0ab6ecb89c8132cca2bd4ab7f71e85ced
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45299
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-12 20:53:25 +00:00
Felix Held 4b58d14fa7 soc/intel/denverton_ns/uart_debug: include header for uart_platform_base
Include console/uart.h for the declaration of uart_platform_base instead
of declaring the function in the source file.

Change-Id: Ib72d8884f27e93cec058dbcda404dd6908de1981
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45295
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-09-12 15:00:07 +00:00
Felix Held e3a1247b15 include/console/uart: make index parameter unsigned
The UART index is never negative, so make it unsigned and drop the
checks for the index to be non-negative.

Change-Id: I64bd60bd2a3b82552cb3ac6524792b9ac6c09a94
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45294
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-09-12 14:59:33 +00:00
Felix Held 8395165eee soc/amd/picasso/uart: make index parameters unsigned
The UART index is never negative, so make it unsigned and drop the check
for the index to be non-negative.

BRANCH=zork

Change-Id: I38b5dad87f8af4fbe8ee1d919230efe48f68686c
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45292
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-09-12 14:59:12 +00:00
Christian Walter c92524d488 mb/ocp/deltalake: Enable TPM2
Change-Id: I6eaaf80dd2bd69096574ab967ec0c6738b05903b
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45268
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-12 14:30:27 +00:00
Michael Büchler 70fea013c7 cpu/intel/model_1067x: enable PECI
This is required for Super I/Os to be able to read the CPU temperature
through PECI.

On 45nm Core 2 CPUs (Wolfdale, Yorkfield) it is not enabled by default.
This is probably related to erratum AW67 "Enabling PECI via the PECI_CTL
MSR incorrectly writes CPUID_FEATURE_MASK1 MSR". The suggested
workaround is "Do not initialize PECI before processor update is
loaded". Since coreboot performs microcode updates before running this
code it should not cause any trouble. It was tested on a Core 2 Duo
E8400, stepping E0.

PECI is already enabled by default on older (65nm) CPUs. Tested: Pentium
Dual-Core E2160.

See commit edac28ce65 for the same change
on cpu/intel/model_6fx.

Signed-off-by: Michael Büchler <michael.buechler@posteo.net>
Change-Id: I5a3ec033bd816665af4ecc82f7b167857cd7c1b6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45184
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-09-12 10:50:33 +00:00
Elyes HAOUAS eea0657044 mb/msi/ms7721: Use PNP_IDX_EN instead of magic number
Change-Id: Ica66ad6da61376f64f9d24de015f84d250327d66
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44840
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-09-11 22:36:37 +00:00
Elyes HAOUAS c33f6e047f mb/ibase/mb899: Use 'PNP_IDX_*' macros instead of magic number
Change-Id: I1e543f8ff701fa20eaaee601ef54f0b056e61909
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44832
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-09-11 22:33:28 +00:00
Elyes HAOUAS 92c4bc19e9 mb/kontron/ktqm77: Use 'PNP_IDX_*' instead of magic numbers
Change-Id: Ic4f51a59524bacb374d90c5620f810e96d7b8eb2
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44839
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-09-11 22:32:52 +00:00
Bob Moragues c06c0ce559 strongbad / coachz : Add Initial Support
BUG=b:162409909
BUG=b:164196066
BRANCH=NONE
TEST=Verify build of strongbad target

Signed-off-by: Bob Moragues <moragues@chromium.org>
Change-Id: If83bd2c8f25fdd3c9625f40121e55c3c922a66fe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45276
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-11 22:32:34 +00:00
Elyes HAOUAS 600e70dd52 mb/kontron/986lcd-m: Use ''PNP_IDX_*' instead of magic numbers
Change-Id: Ic7c1b4defa8c65ed739b1cf3861087cd53cd997c
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44838
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-09-11 22:32:28 +00:00
Elyes HAOUAS e1b1bc94c8 mb/biostar/am1ml: Use 'PNP_IDX_*' instead of magic numbers
Change-Id: I5eaf33558e14f63045928215d88d2ad2554fdbf2
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44836
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-09-11 22:24:27 +00:00
Elyes HAOUAS 9b54dfa1d0 src/superio: Use 'PNP_IDX_*' macros instead of magic numbers
Change-Id: I2f8d6d9e8b6e84bb6c2b4e73b0fbeca476130d05
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44833
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-09-11 22:19:38 +00:00
Karthikeyan Ramasubramanian aa03f30e6e mb/google/dedede/var/drawcia: Remove debug statement with NULL pointer
The debug statement to print WiFi SAR file can potentially have a NULL
pointer. Also the debug statement does not add much value. Hence remove the
debug statement.

BUG=b:165613510
TEST=Build and boot the drawcia board to OS.

Change-Id: I710240f5e965f523fb8ac55a67880e1cbf9abd48
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45298
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-09-11 19:51:54 +00:00
Nico Huber 8e1ea525d1 sconfig: Allow to link devices to other device's drivers
Rarely, the driver of one device needs to know about another device
that can be anywhere in the device hierarchy. Current applications
boil down to EEPROMs that store information that is consumed by some
code (e.g. MAC address).

The idea is to give device nodes in the `devicetree.cb` an alias that
can later be used to link it to a device driver's `config` structure.
The driver has to declare a field of type `struct device *`, e.g.

    struct some_chip_driver_config {
            DEVTREE_CONST struct device *needed_eeprom;
    };

In the devicetree, the referenced device gets an alias, e.g.

    device i2c 0x50 alias my_eeprom on end

The author of the devicetree is free to choose any alias name that
is unique in the devicetree. Later, when configuring the driver the
alias can be used to link the device with the field of a driver's
config:

    chip some/chip/driver
            use my_eeprom as needed_eeprom
    end

Override devices can add an alias if it does not exist, but cannot
change the alias for a device that already exists.

Alias names are checked for conflicts both in the base tree and in the
override tree.

References are resolved after the tree is parsed so aliases and
references do not need to be in a specific order in the tree.

Change-Id: I058a319f9b968924fbef9485a96c9e3f900a3ee8
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35456
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-11 17:34:01 +00:00
Elyes HAOUAS ad7c8ffba9 src/ec: Drop unneeded empty lines
Change-Id: I1955390fcceeb42ecb644ac74541b7e9dd25320f
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44610
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-09-11 17:07:03 +00:00
Wisley Chen 8b70772ab4 mb/google/dedede/var/drawcia: Add Wifi SAR for drawcia
drawman/drawlat/drawcia share the same coreboot, and only drawcia is convertible.
Use tablet mode of fw config to decide to load custom wifi sar or not.

BUG=b:165613510
TEST=enable CHROMEOS_WIFI_SAR in config of coreboot,
emerge-dedede coreboot-private-files-baseboard-dedede coreboot chromeos-bootimage.

Change-Id: Ibcd498021e63d0a172c71c3d94b60b3a25973467
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44661
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-09-11 15:50:39 +00:00
Wisley Chen 4b5998917e mb/google/dedede: Enable FW_CONFIG
Enable FW_CONFIG and add tablet mode field in devicetree

BUG=b:165613510
TEST=emerge-dedede coreboot

Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Change-Id: I55e4c0d0b4aa2337c01773006d0b485fdcd91654
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45185
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-09-11 15:50:25 +00:00
Wisley Chen b68679bcdc mb/google/dedede: Add option to enable WiFi SAR configs
BUG=b:165613510
TEST=emerge-dedede coreboot

Change-Id: Ic575889fd9b726a710abff78e1ecc8427b668d5d
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44631
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-09-11 15:49:18 +00:00
Rob Barnes 875d0c22b8 mb/google/zork: Add woomax memory ID 0
Woomax needs memory ID 0 to map to MT40A512M16TB-062E:J.

BUG=b:165611555
TEST=None

Signed-off-by: Rob Barnes <robbarnes@google.com>
Change-Id: Ibbcef6be382bd6649c93cfe92427f124dd137112
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45264
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-11 15:41:21 +00:00
Nikolai Vyssotski 1e633e88dd soc/amd/picasso: Fix TSC frequency calculation
Fix TSC frequency calculation per Picasso PPR. This code was copied
from Stoney and was incorrect for Picasso.

BUG=b:163423984
TEST=verify Dalboz TSC to be 1GHz
BRANCH=zork

Change-Id: Ibe3f49c7d295e7336ee042da2b94823171b6eb55
Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45055
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-09-11 15:32:14 +00:00
Felix Held 1fa45b1460 vc/amd/fsp/picasso: Fix FSP-S UPD header file formatting
Use one tab instead of 8 spaces at the beginning of the lines added in
commit 39a8040ddc.

Change-Id: I8d7553e1b41dbbbdabd7392028a51e3a0f79c97a
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45257
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-09-11 14:28:38 +00:00
Felix Held b026c7c65a soc/amd/common/espi_util: clarify espi_open_io_window
Calling espi_open_generic_io_window in espi_open_io_window depends on
the condition in the preceding if statement, so move the command into an
else block to make it more obvious that this is the case.

TEST=Timeless build results in identical image.

Change-Id: I3039817afd79c30a2df2f2f54e7848f52dc2c487
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44353
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-09-11 14:27:57 +00:00
Subrata Banik 3999aa6cdb soc/intel/tigerlake: Clean up systemagent.h
List of changes:
1. Convert inconsistent white space into tab.
2. Group together all MCHBAR offset macros.

Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: I82fc362589389081b1b1856524a972b780af9a13
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45256
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-11 03:14:05 +00:00
Subrata Banik 86e53267c4 device: Fix incompatible-pointer-types build error
The build error `incompatible-pointer-types` occurs while using
`pci_dev_request_bus_master` as part of device ops

Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: I3b1ce85b8db1ddf9ac860415edbe64694b91b3d1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45122
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-11 03:13:17 +00:00
Alex Levin a903ea8d62 mb/google/volteer/variants/volteer2: route GPP_F14 via APIC
GPP_F14 should be configured to be routed via APIC and not SCI.

BUG=b:162528549
TEST=verified on a volteer2

Signed-off-by: Alex Levin <levinale@google.com>
Change-Id: I7f2c7af230dd75b3cb3806e2b186725d49da9e68
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45279
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-11 01:04:36 +00:00
Julius Werner 8678d47deb trogdor: Strappings_update_final3.1_second_thisistherealone.patch
Apparently what I thought was lazor-rev2 is actually lazor-rev3 and
nobody is really sure what lazor-rev4 is going to be at this point or
how we proceed from there. What seems to be somewhat agreed upon is that
for now all Lazor revisions use the "old" GPIO mapping and it's not very
clear if that's ever going to change for Lazor, so let's take the
revision restriction out from Lazor for now.

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I4939ccfd8464da6e72b5e01a58489b8c80f5b4df
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45225
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Philip Chen <philipchen@google.com>
2020-09-10 21:40:07 +00:00
Rob Barnes b2545cc3c6 soc/amd/picasso: Move APCB generation out of picasso
Move APCB generation out of the picasso makefile and into the mainboard
makefile. APCB generation tends to be mainboard specific and does not
belong in the soc makefile.

BUG=b:168099242
TEST=Build mandolin and check for APCB in coreboot binary
     Build and boot ezkinil

Change-Id: Ib85ad94e515f2ffad58aafe06c1f1d4043e9303c
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45222
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-10 20:26:03 +00:00
Michael Niewöhner 3992da034f lib/Makefile.inc: fix hex-to-bin conversion of SPD files
This fixes the hex-to-bin conversion command, used to generated binary
SPD files from hexdumps.

An issue that only appeared on one of my systems, where conversion of
'01 02 03' to binary resulted in \x01\x32\x03 instead of \x01\x02\x03:

for c in 01 02 03; do printf $(printf '\%o' 0x$c); done | xxd -g 1
00000000: 01 32 03                                         .2.

The reason for this was that the syntax in lib/Makefile.inc is wrong,
because the backslash must be escaped due to chaining two printf
commands.

Change-Id: I36b0efac81977e95d3cc4f189c3ae418379fe315
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45207
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-10 17:30:00 +00:00
Patrick Georgi 28276fc834 util/abuild: Remove symbols that don't exist anymore in Kconfig
Bayou and OpenBIOS aren't supported by the coreboot build system
anymore, so remove these mentions.

Change-Id: Ibdf6fdc776068041cb468fdbf5b56b06f85c2d4b
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45180
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-10 15:50:27 +00:00
Jason Glenesk f459a4084e soc/amd/picasso: Add MADT entry for GNB IOAPIC
Add the missing entry using new Kconfig symbol for IOAPIC ID. coreboot
will always enable the GNB IOAPIC.

Cq-Depend: chrome-internal:3247431, chrome-internal:3253044
BUG=b:167421913, b:166519072
TEST=Boot fully to morphius board with and without amd_iommu kernel
     parameter. Dump MADT and IVRS tables. Cross check ioapic entries
     in MADT against IVRS.
BRANCH=Zork

Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Change-Id: Ic4a2e9b71dba948e8a4907e5f97131426d8a4a3e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45056
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-10 12:38:19 +00:00
Marshall Dawson 39c64b0bdd soc/amd/picasso: Assign IOAPIC IDs, GNB APIC base with FSP
Add Kconfig symbols for the FCH and GNB IOAPIC IDs, then pass
the info to FSP to keep it in sync with coreboot.  Do the same
for the northbridge's IOAPIC base address.

Use the new values where needed, and reserve the resources
consumed by the GNB IOAPIC.

BUG=b:167421913, b:166519072
TEST=Boot Morphius and verify settings
BRANCH=Zork

Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: I57d3d6b2ebd8b5d511dbcb4324ea065cc3111a2d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45115
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-10 12:37:45 +00:00
Marshall Dawson 39a8040ddc vc/amd/fsp/picasso: Sync FSP-S UPD header file
Sync the UPD definitions with the latest auto-generated files.
Definitions and usage will be updated in a subsequent FSP
Integration Guide.

Cq-Depend: chrome-internal:3247431
BUG=b:167421913, b:166519072, b:159664044
TEST=Boot morphius
BRANCH=Zork

Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: Ic85e1f457c8932d933d8645738de68319dbf375a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45113
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-09-10 12:37:29 +00:00
Yu-Ping Wu aa78c9ea4a mb/google/asurada: Add config for hayato
BUG=b:163789704
TEST=emerge-asurada coreboot
BRANCH=none

Change-Id: I1a5928fb81356aaf040534e1675933a504aa9f95
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45163
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-10 06:39:45 +00:00