Commit Graph

49228 Commits

Author SHA1 Message Date
Sean Rhodes 7ef5376123 soc/intel/apollolake: Configure FSP UPDs to allow coreboot to lockdown
Configure FSP S UPDs to allow coreboot to handle the lockdown.

The main change here is setting `Write Protection Support` to 0,
as the default is Enabled, which shouldn't allow writes (even though
it seems to).

The UPDs are identical on APL and GLK, but all ones configured
in this patch have been there since their initial releases.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I35185b498315511f3236758caebfe2f9c28fd04a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65039
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-19 14:55:23 +00:00
Angel Pons d669562663 mb/prodrive/hermes: Add part numbers to SMBIOS
Adjust the EEPROM layout to account for two new fields: board part
number and product part number. In addition, put them in a Type 11
SMBIOS table (OEM Strings).

TODO: This currently stores the "raw" part numbers, should we add a
prefix to the SMBIOS strings?

Change-Id: I85fb9dc75f231004ccce2a55ebd9d7a4867fcb93
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67276
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-19 14:53:01 +00:00
Tim Van Patten 1075fef445 amd/mendocino/root_complex: Throttle SOC during low/no battery
Use dynamic power and thermal configuration (DPTC) via ACPI ALIB calls
to throttle the SOC when there is no battery or critically low battery,
to enable the SOC to boot without overwhelming the AC charger and
browning out.

DPTC is not enabled for low/no battery mode with this CL. It will be
enabled for Skyrim in a following CL.

BRANCH=none
BUG=b:217911928
TEST=Boot skyrim

Signed-off-by: Tim Van Patten <timvp@google.com>
Change-Id: Ifeddb99e97af93b40a5aad960d760e4c101cf086
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67189
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-19 10:00:51 +00:00
Tim Van Patten d8210d6ee1 amd/mendocino/acpi/soc: Add DPTC Support
Add support for DPTC by calling SB.DPTC() as part of PNOT().

BRANCH=none
BUG=b:217911928
TEST=Boot skyrim

Signed-off-by: Tim Van Patten <timvp@google.com>
Change-Id: Ifc332bfc4d273031c93b77673224b4f3c2871fb1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67694
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-19 09:57:12 +00:00
Tim Van Patten 7a6451bd3e skyrim/overridetree: Add "Throttle" DPTC values
Add the Low/No Battery Mode DPTC values for Skyrim.

These values were generated by AMD.

BRANCH=none
BUG=b:217911928
TEST=Build skyrim

Signed-off-by: Tim Van Patten <timvp@google.com>
Change-Id: I5f277761cb7379b4344492f95010d8d5ddd689fb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67693
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-19 09:56:34 +00:00
Tim Van Patten 1cf0acdc1c soc/amd/mendocino: Add low/no battery VRM limit registers
Add DPTC Low/No battery VRM limit registers to throttle the SOC.

BRANCH=none
BUG=b:217911928
TEST=Build skyrim

Signed-off-by: Tim Van Patten <timvp@google.com>
Change-Id: I9c4ed227b54efbab9f03d6acf64b1160ad73f460
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67692
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-19 09:56:06 +00:00
Tim Van Patten 11ca995500 amd/mendocino/root_complex: Set DPTC VRM limit values
Set the DPTC VRM limit values for normal mode.

BRANCH=none
BUG=b:217911928
TEST=Boot skyrim

Signed-off-by: Tim Van Patten <timvp@google.com>
Change-Id: I2041a713323f039dcfdacdfa43e74cf450c3c0d1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67691
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-19 09:55:20 +00:00
Tim Van Patten cf9e0a08f5 mb/google/skyrim: Add "Normal" DPTC values
Add the Normal Mode DPTC values for Skyrim.

These values were generated by AMD.

BRANCH=none
BUG=b:217911928
TEST=Build skyrim

Signed-off-by: Tim Van Patten <timvp@google.com>
Change-Id: I1e1f55b941f3e70aad33d55a90fb012eac3ba12d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67690
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-19 09:54:40 +00:00
Tim Van Patten b06873f77c soc/amd/mendocino: Add VRM limit DPTC registers
Add VRM DPTC limit registers. These are required when throttling the SOC
for low/no battery mode to prevent the SOC from overwhelming the
charger.

b/245942343 is tracking passing these additional fields to the FSP and
having the FSP configure them.

BRANCH=none
BUG=b:217911928
TEST=Build skyrim

Signed-off-by: Tim Van Patten <timvp@google.com>
Change-Id: Ie62129d967192f9a9cf654b1854d7dbe4324802a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67378
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-19 09:54:00 +00:00
Tim Van Patten a90aebbf2a soc/amd/acpi: Add low/no battery mode to DPTC
Update acpigen_write_alib_dptc() to support "low/no battery mode",
which throttles the SOC when there is no battery connected or the
battery charge is critically low.

This is in preparation for enabling this functionality for Mendocino.

BUG=b:217911928
TEST=Build zork
TEST=Boot nipperkin
TEST=Boot skyrim

Signed-off-by: Tim Van Patten <timvp@google.com>
Change-Id: Icea10a3876a29744ad8485be1557e184bcbfa397
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66804
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-19 09:53:17 +00:00
Jan Dabros 2d9e96a5ab soc/amd/mendocino/acpi: Add support for shared TPM_I2C controller
There are platforms equipped with AMD SoC where I2C3 controller
connected to TPM device is shared between X86 and PSP. In order to
handle this, PSP acts as an I2C-arbitrator, where x86 (kernel) sends
acquire and release requests to be accepted by PSP.

Introduce new CONFIG for Mendocino SoCs similar to what we have for
Cezanne.

BUG=b:241878652
BRANCH=none

Signed-off-by: Jan Dabros <jsd@semihalf.com>
Change-Id: I015a24715271d2b26c0bd3c9425e20fb2987a954
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67674
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-09-19 09:52:25 +00:00
Subrata Banik e8097f7a28 mb/google/rex: Add ELAN6918 touchscreen
ELAN6918 Power Sequencing seems not perfectly matching
with the previous platforms and setting GPP_C06 to high prior
to the power sequencing is actually makes it work.

Ideally Power Sequencing should be as below for ELAN6918 (in ACPI)
`POWER enabled -> RESET deasserted -> Report EN enabled`

But below sequence is only working currently:
`Report EN enabled (ramstage) -> POWER enabled (ACPI) -> RESET
 deasserted (ACPI)`

BUG=b:247029304
TEST=Verified ELAN touch panel is working as expected after booting
Google/rex device to ChromeOS.

Change-Id: Ideaeb0faa882b8e603534bbface51ea76923d436
Signed-off-by: Eran Mitrani <mitrani@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66990
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-09-19 09:50:58 +00:00
Nick Vaccaro dbe4fe2c88 mb/google/brya/var/brya4es: deprecate brya4es
The brya4es variant is no longer needed, removing code for brya4es.

BUG=b:246611270
TEST=None

Change-Id: I9b222f89fe766c63158518713be19d7959451721
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67667
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-09-19 09:49:06 +00:00
Werner Zeh 57ed348b20 mb/siemens/mc_apl1: Do not wait for legacy devices on mc_apl7
Since there are no legacy devices on the variant mc_apl7 do not wait
for them on mc_apl7.

Change-Id: Ia4e6c0fb495a347be51bd6604a1d9b73098fb7b6
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67684
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-19 09:48:27 +00:00
Elyes Haouas c8870b1334 crossgcc: Upgrade llvm from version 14.0.6 to 15.0.0
Test build for QEMU x86 i440fx/piix4.

Change-Id: I3144a83fcbd92eec51d70e9be33ff2fcb2821731
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67416
Reviewed-by: Patrick Georgi <patrick@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-18 17:14:10 +00:00
Elyes Haouas 035e9f9f0c crossgcc: Upgrade cmake from 3.23.2 to 3.24.2
Change-Id: I81a8371190513ca34d3c5efb0e3770ac3d873b03
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67367
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-09-18 17:14:04 +00:00
Yidi Lin 0811a6492d cbmem: use aligned_memcpy for reading lb_cbmem_entry information
The lbtable contains the memory entries that have fields unnaturally
aligned in memory. Therefore, we need to perform an aligned_memcpy() to
fix the issues with platforms that don't allow unaligned accesses.

BUG=b:246887035
TEST=cbmem -l; cbmem -r ${CBMEM ID}

Change-Id: Id94e3d65118083a081fc060a6938836f6176ab54
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67672
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-09-18 03:24:16 +00:00
Patrick Georgi f0d5f67e46 riscv: Enable the newfangled way of selecting instruction sets
gcc12+ will require riscv architecture selection to come not only with
featurei suffixd charactersa, it also comes with feature_ful suffix_ed
words_mith. Much creative, very appreciate.

To accommodate for this madness, enable the already existing (but off by
default) support for that in our gcc11 build, support using by detecting
the compiler's behavior in xcompile and pass that knowledge along to our
build system.

Then cross our fingers and hope for the best!

Change-Id: I5dfeed766626e78d4f8378d9d857b7a4d61510fd
Signed-off-by: Patrick Georgi <patrick@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67457
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-09-17 05:56:34 +00:00
Miriam Polzer 2c38933a0e security/vboot: Add rollback NVRAM space for TPM 2
Create an NVRAM space in TPM 2.0 that survives owner clear and can be
read and written without authorization. This space allows to seal data
with the TPM that can only be unsealed before the space was cleared.
It will be used during ChromeOS enterprise rollback to securely
carry data across a TPM clear.

Public documentation on the rollback feature:
https://source.chromium.org/chromium/chromiumos/platform2/+/main:oobe_config/README.md

BUG=b/233746744

Signed-off-by: Miriam Polzer <mpolzer@google.com>
Change-Id: I59ca0783b41a6f9ecd5b72f07de6fb403baf2820
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66623
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-09-17 01:42:11 +00:00
Husni Faiz f634aed758 console: attach smbus console driver
This patch attaches the smbus console functions to the high
level console interface.

Change-Id: I3a9bf64e59d529253bfdcdfa565bb2bb92975728
Signed-off-by: Husni Faiz <ahamedhusni73@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67341
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-16 17:03:49 +00:00
Husni Faiz f571ce5c67 bd82x6x/early_pch: enable smbus in bootblock stage
SMBus is typically enabled in the ROMSTAGE. To get the
BOOTBLOCK console message, the SMBus should be enabled
in the BOOTBLOCK stage.

Change-Id: I97d0afb013ede428383acaa0aa97ab04fe80e2a4
Signed-off-by: Husni Faiz <ahamedhusni73@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67340
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-16 17:02:39 +00:00
Husni Faiz 67300f88cd drivers/smbus: add smbus console driver
This patch adds a new smbus console driver and Kconfig
options to enable the driver.

Change-Id: Ife77fb2c3e1cc77678a4972701317d50624ceb95
Signed-off-by: Husni Faiz <ahamedhusni73@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67339
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-16 17:01:17 +00:00
Jeremy Soller c5d0761dea soc/intel/cnl: Add Cometlake-H/S Q0 (10+2) CPU ID
The Q0 stepping has a different ID than P1.

Reference: CML EDS Volume 1 (Intel doc #606599)
Change-Id: Id1da42aa93ab3440ae743d943a00713b7df3f453
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66159
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-09-16 16:17:36 +00:00
Jeremy Soller 9601b1e273 soc/intel/alderlake: Set FSP-S GnaEnable based on devicetree
Change-Id: Ifd25416c55c4dba1709f74cdedc0c58e881d6266
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66090
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-09-16 16:17:19 +00:00
Elyes Haouas 3541c31add util/kconfig/regex.c: Remove leftover
coreboot doesn't support the MIPS architecture anymore.

Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I404d034949a7786d7971117081537baf27ff2e22
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67353
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-09-16 14:52:44 +00:00
Elyes Haouas a3c287d7a3 crossgcc [binutils]: Remove 'enable-plugins' option
unneeded 'enable-plugins' option sneaked in..., so remove it.

Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: Id1d7f2c7e6b70c28e1060c6ee915363ffe412ef6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67645
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-09-16 13:06:22 +00:00
Elyes Haouas b8e5baf2f2 crossgcc [binutils]: Remove invalid enable-interwork option
'enable-interwork' is not a binutils configure option.

Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I29cd6137c700ff6871868a723daf33909aa218ff
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65609
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-09-16 13:05:44 +00:00
Arthur Heymans 5d8fe86db2 drivers/usb/hub/acpi.c: Don't use heap for ACPI name
Using malloc would increase the heap use each time this function is
called. Instead allocate a per struct device buffer inside the
chip_info struct.

Found by coverity scan, CID 1488815.

Change-Id: Ie24870b34338624b3bf3a6f420debdd24a68ffbd
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64338
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-09-16 13:05:19 +00:00
Eric Lai 4d9748f87c mb/google/nissa/var/nivviks: Enable nau8825 ADCOUT
Enable nau8825 ADCOUT to make I2S signal meet spec.

BUG=b:234789689
TEST=I2S waveform can meet spec timing.

Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: I7ea472ac4e4add4e790b9b3fbb6becd40665eb1a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67660
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-09-16 12:08:19 +00:00
Eric Lai 82a9f865fd drivers/i2c/nau8825: Add ADCOUT IO drive strength control
Add a property to control the driving of ADCOUT.

BUG=b:234789689
TEST= build passed.

Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: Ibbedd5838a795ee645a5458b960062c5530ff3b5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67659
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-09-16 12:08:09 +00:00
Sridhar Siricilla 90a439384b soc/intel/common: Update comment on HFSTS1.spi_protection_mode
The patch updates comment on HFSTS1.spi_protection_mode.
The spi_protection_mode indicates SPI protection status as well as EOM
status (in a single staged EOM flow). Starting from TGL platform, staged
EOM flow is introduced. In this flow, spi_protection_mode alone doesn't
indicate the EOM status.

For information on EOM status, please refer secton# 3.6.1 in doc#
612229.

TEST=Build code for Gimble

Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I19df5cfaa6d49963bbfb3f8bc692d847e58c4420
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67533
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-09-16 12:07:06 +00:00
Elyes Haouas 6580674b34 contributing/coding_style.md: Add missing ">"
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I2f2cd20139f4cdb7ba665e9e49a03faea1ac085b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67658
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-09-16 11:49:27 +00:00
Subrata Banik a3acac15ee Revert "drivers/wifi: Move MTL Magnetar CNVi DIDs from SoC to generic driver"
This reverts commit 510a55d4ee.

Reason for revert: Observed `missing read resource` issue for
cnvi device

BUG=b:244687646
TEST=No error seen in AP log while booting Google/rex

Without this patch:
[SPEW ]  PCI: 00:14.3 read_resources bus 0 link: 0
[ERROR]  GENERIC: 0.0 missing read_resources
[SPEW ]  PCI: 00:14.3 read_resources bus 0 link: 0 done

With this patch:
[SPEW ]  PCI: 00:14.3 read_resources bus 0 link: 0
[SPEW ]  PCI: 00:14.3 read_resources bus 0 link: 0 done

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I1e881313729f1088cffa7c161722ee79bb9acc49
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67566
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2022-09-16 05:37:05 +00:00
Subrata Banik 00b682e6a4 soc/intel/meteorlake: Enable `SOC_INTEL_COMMON_BLOCK_CNVI` config
TEST=Able to build and boot Google/rex.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I64aab8391f89414754785cea47671f3350324297
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67652
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2022-09-16 05:36:34 +00:00
Subrata Banik fa317d574e mb/google/rex: Enable `DRIVERS_WIFI_GENERIC` config
TEST=Able to build and boot the Google/rex.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Iae5317b24856ef2cbd2f36cc28f645826536c21a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67641
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2022-09-16 05:36:26 +00:00
Tim Van Patten 53ba14de1e amd/mendocino: Control DPTC with only Kconfig
SOC_AMD_COMMON_BLOCK_ACPI_DPTC can be enabled conditionally for any
skyrim boards, similar to mainboard/google/zork/Kconfig. This makes the
value dptc_tablet_mode_enable redundant.

This CL removes dptc_tablet_mode_enable so DPTC is controlled entirely
with the Kconfig value SOC_AMD_COMMON_BLOCK_ACPI_DPTC. This means DPTC
is only included for boards that actually enable it.

BRANCH=none
BUG=b:217911928
TEST=emerge-skyrim coreboot

Signed-off-by: Tim Van Patten <timvp@google.com>
Change-Id: I73fca5a16826313219247f452d37fb526ad4f4df
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67639
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-09-15 17:58:50 +00:00
Tim Van Patten 9eac097205 amd/cezanne: Control DPTC with only Kconfig
SOC_AMD_COMMON_BLOCK_ACPI_DPTC can be enabled conditionally for any
guybrush boards, similar to .mainboard/google/zork/Kconfig This makes
the value dptc_tablet_mode_enable redundant.

This CL removes dptc_tablet_mode_enable so DPTC is controlled entirely
with the Kconfig value SOC_AMD_COMMON_BLOCK_ACPI_DPTC. This means DPTC
is only included for boards that actually enable it.

BRANCH=none
BUG=b:217911928
TEST=emerge-guybrush coreboot

Signed-off-by: Tim Van Patten <timvp@google.com>
Change-Id: I07f1266fa80a6c9ee4ec3b3ba970a70c6c72fb54
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67638
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-09-15 17:58:31 +00:00
Tim Van Patten 54ce4aa98c zork: Control DPTC with only Kconfig
Moving the config value SOC_AMD_COMMON_BLOCK_ACPI_DPTC to
soc/amd/picasso/Kconfig and conditionally enabling it for only Morphius
boards makes the value dptc_tablet_mode_enable redundant.

This CL removes dptc_tablet_mode_enable so DPTC is controlled entirely
with the Kconfig value SOC_AMD_COMMON_BLOCK_ACPI_DPTC. This means DPTC
is only included for boards that actually enable it.

BRANCH=none
BUG=b:217911928
TEST=Build zork

Signed-off-by: Tim Van Patten <timvp@google.com>
Change-Id: Ic54a9bb491234088be8184bec8b09e2e31ffa298
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67635
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-09-15 17:58:07 +00:00
Arthur Heymans 56776a1ab3 soc/amd: Do SMM relocation via MSR
AMD CPUs have a convenient MSR that allows to set the SMBASE in the save
state without ever entering SMM (e.g. at the default 0x30000 address).
This has been a feature in all AMD CPUs since at least AMD K8. This
allows to do relocation in parallel in ramstage and without setting up a
relocation handler, which likely results in a speedup. The more cores
the higher the speedup as relocation was happening sequentially. On a 4
core AMD picasso system this results in 33ms boot speedup.

TESTED on google/vilboz (Picasso) with CONFIG_SMI_DEBUG: verify that SMM
is correctly relocated with the BSP correctly entering the smihandler.

Change-Id: I9729fb94ed5c18cfd57b8098c838c08a04490e4b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64872
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-09-15 14:47:52 +00:00
Nico Huber 576861994e soc/intel/skylake: Assign device ops in chipset devicetree
Some PCI IDs were missing, and at least one (SPT's fast SPI
device in a generic SPI driver) was wrong. Hence, this patch
actually changes behavior depending on the devices actually
present in a machine.

In this patch the Skylake devicetree is written in a single-line
style. Alternative, the device operations could be put on a separate
line, e.g.
    device pci 00.0 alias system_agent on
            ops systemagent_ops
    end

Tested on Kontron/bSL6. Notable in the log diff is that the
CSE and SATA drivers are hooked up now.

Change-Id: I8635fc53ca617b029d6fe1845eaef6c5c749db82
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66485
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-09-15 13:07:11 +00:00
Nico Huber c0fc38eed8 sconfig: Allow to specify device operations
Currently we only have runtime mechanisms to assign device operations to
a node in our devicetree (with one exception: the root device). The most
common method is to map PCI IDs to the device operations with a `struct
pci_driver`. Another accustomed way is to let a chip driver assign them.

For very common drivers, e.g. those in soc/intel/common/blocks/, the PCI
ID lists grew very large and are incredibly error-prone. Often, IDs are
missing and sometimes IDs are added almost mechanically without checking
the code for compatibility. Maintaining these lists in a central place
also reduces flexibility.

Now, for onboard devices it is actually unnecessary to assign the device
operations at runtime. We already know exactly what operations should be
assigned. And since we are using chipset devicetrees, we have a perfect
place to put that information.

This patch adds a simple mechanism to `sconfig`. It allows us to speci-
fy operations per device, e.g.

  device pci 00.0 alias system_agent on
          ops system_agent_ops
  end

The operations are given as a C identifier. In this example, we simply
assume that a global `struct device_operations system_agent_ops` exists.

Change-Id: I2833d2f2450fde3206c33393f58b86fd4280b566
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66483
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-09-15 13:06:47 +00:00
Elyes Haouas f1ba7d6c8f soc/intel/xeon_sp: Use "if (!ptr)" in preference to "if (ptr == NULL)"
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I664f5b7d354b0d9a7144c25604ae4efbdd9ba9a9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67593
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
2022-09-15 13:03:28 +00:00
Elyes Haouas 3de1253318 mb/ocp: Use "if (!ptr)" in preference to "if (ptr == NULL)"
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: Ie5fc0a8230cdcc24ad1d2d94cc6d019ff10aac48
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67608
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
2022-09-15 13:03:08 +00:00
Elyes Haouas 6a8029c2c9 soc/intel/meteorlake: Use "if (!ptr)" in preference to "if (ptr == NULL)"
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: Ia2508abe62a194f2921d5535937ba82a60967ca3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67612
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-09-15 13:02:53 +00:00
Elyes Haouas aebccac7e1 src/security: Use "if (!ptr)" in preference to "if (ptr == NULL)"
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I3def65c016015d8213824e6b8561d8a67b6d5cf0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67579
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-09-15 13:02:33 +00:00
Elyes Haouas a6b41f2fd0 mb/google/mistral/verstage.c: Change loglevel prefix
BIOS_ERR is inappropriate since the message is informational.
Use BIOS_INFO instead.

Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I91be3f47ae93c8262e430a06cacec3d2c29ebd58
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67539
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-09-15 13:01:59 +00:00
Jeremy Compostella e1465e2157 util/ifittool: Error out if microcodes do not fit the FIT table
parse_microcode_blob() returns success when it reaches max_fit_entries
microcode. It makes the FIT table size verification in
fit_add_microcode_file() useless. This patch makes
parse_microcode_blob() error out if max_fit_entries is reached.

Note that this size verification is critical as a FIT table only
partially listing the microcode patches can lead to boot failures as
recently observed on Raptor Lake-P.

BRANCH=firmware-brya-14505.B
BUG=b:245380705
TEST=compilation errors out when trying to stitch more than
     CONFIG_CPU_INTEL_NUM_FIT_ENTRIES microcode patches.

Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Change-Id: Id9c5fb6c1e264f3f5137d29201b9021c72d78fde
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67454
Reviewed-by: Selma Bensaid <selma.bensaid@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Zhixing Ma <zhixing.ma@intel.com>
2022-09-15 13:01:42 +00:00
Jeremy Compostella 2c021383c0 cpu/intel/haswell: Allow up to six microcodes in the FIT table
Haswell and Broadwell platforms usually stitch six microcode
patches. It has worked so far with the default value of four thanks a
bug which is being fixed by `util/ifittool: Error out if microcodes do
not fit the FIT table' commit.

BUG=b:245380705
TEST=Jenkins build without failing on the FIT table size

Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Change-Id: I23bf79a3e8918499f6c51e6ef829312d5872181a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67466
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-09-15 13:01:13 +00:00
Tim Van Patten 3ed3138eeb zork/Kconfig: Move SOC_AMD_COMMON_BLOCK_ACPI_DPTC
Move enabling SOC_AMD_COMMON_BLOCK_ACPI_DPTC from
soc/amd/picasso/Kconfig to mainboard/google/zork/Kconfig and
conditionally enable it only for Morphius boards.

This reduces which boards/variants have DPTC enabled to only those that
actually use it.

BRANCH=none
BUG=b:217911928
TEST=Build zork

Signed-off-by: Tim Van Patten <timvp@google.com>
Change-Id: Iddebcf5dbadae135c8110e2afd9ad76ef7dcc09d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67637
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-14 22:12:40 +00:00
Tim Van Patten 9b3112c875 acpi/soc: Conditionally include dptc.asl
Conditionally include dptc.asl based on the Kconfig value
SOC_AMD_COMMON_BLOCK_ACPI_DPTC.

BRANCH=none
BUG=b:217911928
TEST=Build zork
TEST=Build guybrush
TEST=Build skyrim
TEST=Build majolica

Change-Id: Idd94af8e8b2d7973abc0fb939e4600189e21656a
Signed-off-by: Tim Van Patten <timvp@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67620
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-14 22:12:10 +00:00