Commit Graph

49228 Commits

Author SHA1 Message Date
Elyes Haouas 135ab119a2 mb/gizmosphere/*/irq_tables.c: Use ALIGN_UP macro
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I19412b595b3a1d2026fce5a84ddbd6356abe5a3f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67508
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-09-12 15:28:17 +00:00
Elyes Haouas 726bf18065 mb/pcengines/apu{1,2}/irq_tables.c: Use ALIGN_UP macro
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I5331c7127905524517efa50158bde8d6a1c5f1eb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67507
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-09-12 15:27:51 +00:00
Elyes Haouas 2cd41c6371 mb/asus/f2a85-m/irq_tables.c: Use ALIGN_UP macro
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I223282147b3265133b8b249368cfe4cdf4cafa5c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67506
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-09-12 15:27:30 +00:00
Elyes Haouas d0827aace3 mb/asrock/*/irq_tables.c: Use ALIGN_UP macro
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I38ea4e9bf0d8e2d93b86413cd9b1a2fb0a547e1c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67505
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-09-12 15:27:05 +00:00
Elyes Haouas e378cdbb61 mb/amd/*/irq_tables.cmb/*/*/irq_tables.c: Use ALIGN_UP macro
Change-Id: I2bd5e09f51918fe4c7e954edf54ab4d9bc629fd1
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61919
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-09-12 15:26:42 +00:00
Maxim Polyakov 593b0f1f23 intelp2m: Add Go Managing Dependencies System support
Add go.mod containing the full name of the project according to the
docs [1]: review.coreboot.org/coreboot.git/util/intelp2m, and also,
based on this, rename the internal packages to point to the absolute
path. This will allow Go Managing Dependencies System to integrate
packages from intelp2m to third-party Go written on the Go language [1].
This also requires fixing the Golang compiler version in go.mod: use
go1.18 [2], the latest up-to-date version.

[1] https://web.archive.org/web/20220910100342/https://go.dev/doc/modules/managing-dependencies
[2] https://web.archive.org/web/20220910100206/https://tip.golang.org/doc/go1.18

[ TEST ]
1) Import the coreboot project into some go project:

$cd path/to/go-project
$go get review.coreboot.org/coreboot.git
go: downloading review.coreboot.org/coreboot.git v0.0.0-20220903004133
-39914a50ae16
go: added review.coreboot.org/coreboot.git v0.0.0-20220903004133
-39914a50ae16

Thus, 'go get' correctly downloaded the contents of the repository.

2) Import intelp2m:

$cd path/to/go-project
$go get review.coreboot.org/coreboot.git/util/intelp2m
review.coreboot.org/coreboot.git/util/intelp2m imports
	./config: "./config" is relative, but relative import paths are
not supported in module mode
review.coreboot.org/coreboot.git/util/intelp2m imports
	./parser: "./parser" is relative, but relative import paths are
not supported in module mode

Thus, the problem is in the package names, but after this patch, the
import should be without errors.

3) Import a repository with an incorrect url:

$cd path/to/go-project
$go get review.coreboot.org/coreboot/test
go: unrecognized import path "review.coreboot.org/coreboot/test":
reading https://review.coreboot.org/coreboot/test?go-get=1:
404 Not Found

This has not happened in previous cases.

Change-Id: I12efae31227129b8c884af10fb233f398c4094e7
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64724
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2022-09-12 12:55:05 +00:00
Reka Norman 5004e93053 Revert "drivers/mrc_cache: Don't compute checksum if TPM hash is used"
This reverts commit f83b7d494e.

It turns out we have tests which use `futility validate_rec_mrc` to
validate the MRC cache, which includes verifying the data checksum.
Revert this to allow the tests to pass while we figure out how to fix
this.

BUG=b:245277259, b:242667207
TEST=None

Signed-off-by: Reka Norman <rekanorman@chromium.org>
Change-Id: Id913d00584444c21cb94668bdc96f4de51af7cee
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67432
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-09-12 12:45:35 +00:00
Tim Van Patten b4b85ebf60 soc/amd: Remove unsupported DPTC tablet mode settings
The following boards are setting DTPC tablet mode values without
corresponding device tree values, meaning they are effectively setting
"random" values for tablet mode:
1. Cezanne
2. Mendocino

The device tree has tablet mode disabled, so the code should never be
exercised, but this CL removes it entirely to cleanup "dead" code.

BRANCH=none
BUG=b:217911928
TEST=Build nipperkin
TEST=Boot skyrim

Signed-off-by: Tim Van Patten <timvp@google.com>
Change-Id: Ide96f255b69670d1b4c37ca2f94cc3504a958b57
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67181
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-09-12 12:42:04 +00:00
Wilson Chou c8a86954f3 device: Clear lane error status
Refer to PCI Express Base rev6.0 v1.0, 4.2.7 Link Training and Status
State Rules, Lane Error Status is normal to record the error when link
training. To make sure Lane Error Status is correct in OS runtime,
add a Kconfig PCIEXP_LANE_ERR_STAT_CLEAR that clears the PCIe lane error
status register at the end of PCIe link training.

Test=On Crater Lake, lspci -vvv shows
bb:01.0 PCI bridge: Intel Corporation Device 352a (rev 03)
(prog-if 00 [Normal decode])
Capabilities: [a30 v1] Secondary PCI Express
	LnkCtl3: LnkEquIntrruptEn- PerformEqu-
	LaneErrStat: LaneErr at lane: 0

Signed-off-by: Wilson Chou <Wilson.Chou@quantatw.com>
Change-Id: I6344223636409d8fc25e365a6375fc81e69f41a5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67264
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
2022-09-12 12:41:13 +00:00
Jeremy Compostella 46ffccd753 util/ifittool: Fix buffer overflow with padded microcode patches
Some microcode patches are padded with zeros, which make
parse_microcode_blob() read beyond the end of the buffer.

BRANCH=firmware-brya-14505.B
BUG=b:245380705
TEST=No segmentation fault with a padded microcode patch

Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Change-Id: Id9c5fb6c1e264f3f5137d29201b9021c72d78fdd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67460
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Cliff Huang <cliff.huang@intel.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-09-12 12:33:36 +00:00
Srinidhi N Kaushik f4a8a92cc2 src/soc/intel/mtl: Remove Storage UPD
This change removes all references to HybridStorageMode
UPD since it has been deprecated starting from FSP v2344_00

BUG=b:245167089
TEST=build coreboot mtlrvp

Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: I16eb33cb1260484b0651d40211323c6ae986a546
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67428
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-09-12 12:32:12 +00:00
Tim Wawrzynczak 7f287d23bc mb/google/brya/acpi: Move dGPU power checks earlier
Linux always "turns on" a PowerResource when it boots, regardless of
_STA, so the _ON routine should be idempotent. In this case, it all is,
except for the LTR restore, which would restore a value of 0 when _ON is
run the first time, which means that LTR is disabled on the root port
from then on, as the save/restore routines will keep saving/restoring
that 0. THis patch fixes the problem by moving the power checks from
PGON/PGOF to GCOO/GCOI.

BUG=b:244409563
TEST=boot agah and verify that LTR is still enabled on the root port

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I4ed78323608eede5b8310598f1f1115497ab2b5b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67278
Reviewed-by: Cliff Huang <cliff.huang@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-09-12 12:31:24 +00:00
Tim Wawrzynczak d6ac209c74 mb/google/brya/acpi: Remove erroneous _PR0/_PR3
The Linux kernel runtime D3 framework expects a PCIe device to have a
power resource in order to be properly power-manageable. The _PR0/_PR3
values were pointing at the PEG0 Device, which is not a PowerResource,
so this must have confused the RTD3 framework and RTD3 was not
functional. Removing the _PR0/_PR3 fixes the problem.

BUG=b:243888246
TEST=echo auto > /sys/bus/pci/devices/0000:01:00.0/power/control;
sleep 10;
echo on > /sys/bus/pci/devices/0000:01:00.0/power/control
After this there are no longer errors seen in dmesg about failing
to place the device into D0.

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I83fa1e5fabd3257b097c10e7a13c9861872685ea
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67212
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Cliff Huang <cliff.huang@intel.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-09-12 12:31:12 +00:00
Tim Wawrzynczak 63aca9233b mb/google/brya/acpi/power: Clean up ASL code
Mostly there are too many extraneous `\_SB.PCI0.` prefixes, also a few
minor cleanups, but nothing functional.

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I79d919d2f04f57232f8f6a4e4d0690833faeb834
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66810
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-09-12 12:25:07 +00:00
Tim Wawrzynczak 7bc8fd58a3 mb/google/brya/acpi: Save/restore/clear some registers over GCOFF
Similar to the prior CL (commit db8ad5e), do the same register dance
before/after GCOFF.

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I8fecba40c5a5af11e24f82db07face3ce10481bf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67086
Reviewed-by: Anil Kumar K <anil.kumar.k@intel.corp-partner.google.com>
Reviewed-by: Cliff Huang <cliff.huang@intel.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-12 12:24:51 +00:00
Lean Sheng Tan cf46099979 soc/intel/adl: Disable D3cold when legacy S3 is enabled
D3Cold isn't supported in S3.

Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com>
Change-Id: I072f47737ef38c44b6a676019e9a73868ff17e5e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67413
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-12 12:24:09 +00:00
Michał Żygowski ff7725e742 drivers/intel/ptt: Use the correct detection method
On some platforms the HFSTS4 bit 19 does not indicate active PTT.
Instead of ME HFSTS4, use TXT FTIF register to check active TPM for
the current boot. Discrete TPM shall be deactivated when PTT is
enabled so this always should return true value of PTT state.

Leave the old method for backwards compatibility if TXT FTIF would not
be applicable for older microarchitectures.

Based on DOC #560297.

TEST=Check if PTT is detected as active on MSI PRO Z690-A DDR4 WIFI

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I3a55c9f38f5bb94fb1186592446a28e675c1207c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63956
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
2022-09-12 12:23:19 +00:00
Vinod Polimera 042ba16ef8 qualcomm/sc7280: remove unnecessary malloc and early return on failure
Instead of just printing the fatal errors, do early return so that
boot up time will be reduced during display init failure. Remove malloc
allocation and make tu a local variable.

Change-Id: I51f7a86d143128d2c426fb8940ff34a66152b426
Signed-off-by: Vinod Polimera <quic_vpolimer@quicinc.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66975
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-12 12:22:34 +00:00
Tim Van Patten 9244358536 soc/amd: Refactor DPTC Tablet Mode
Refactor AMD DPTC tablet mode in preparation for adding low/no battery
DPTC settings.

1. Refactor and simplify acpigen_write_alib_dptc() into the following
   functions:
   - acpigen_write_alib_dptc_default()
   - acpigen_write_alib_dptc_tablet()
2. Add device tree register value dptc_tablet_mode_enable to control
   whether DPTC tablet mode is enabled for a variant.
3. Add dptc.asl to perform the necessary ACPI checking before modifying
   the DPTC settings.

BRANCH=none
BUG=b:217911928
TEST=Build zork
TEST=Build nipperkin
TEST=Boot skyrim

Change-Id: I2518fdd526868c9d5668a6018fd3570392e809c0
Signed-off-by: Tim Van Patten <timvp@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66994
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-09-12 12:21:01 +00:00
Tarun Tuli 14bed61ba1 mb/google/rex: Complete several remaining GPIO configs
Lists of GPIO PINS being updated:
SPKR_INT_L_R
RST_HP_L
SOC_HDMI_HPD_L
SOCHOT_ODL
SOC_FPMCU_INT_L
EN_PP3300_WLAN

BUG=b:24410269
TEST=Build and boot Google/Rex to ChromeOS.

Change-Id: If2fb354f931217c09a6c1c81ca780cb121b24468
Signed-off-by: Tarun Tuli <taruntuli@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67449
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-10 19:01:57 +00:00
Kapil Porwal 53105a5226 mb/google/rex: Enable touchpad
Enable touchpad for Google Rex.

BUG=b:245866939
TEST=Build and boot to Google Rex. Verify touchpad works.

Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: I49fdd72bf3350085e82411b95edcd6a9a09d2df5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67471
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Shaunak Saha <shaunak.saha@intel.corp-partner.google.com>
2022-09-10 19:01:38 +00:00
Kapil Porwal 56c0f80244 mb/google/rex: Add GPE route for GPP_B
Add GPE route for GPP_B.

BUG=b:245866939
TEST=Build and boot to Google Rex.

Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: I28066a6cc75908f8ceefbdbf8c088c56833606ea
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67469
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Shaunak Saha <shaunak.saha@intel.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-09-10 19:01:25 +00:00
Subrata Banik 2bce51ea2a soc/intel/meteorlake: Hook up common code for thermal configuration
Thermal configuration registers are now located behind PMC PWRMBASE
for MeteorLake as well (same as ADL). Hence, using thermal common code
to sets the thermal low threshold as per mainboard provided
`pch_thermal_trip`.

Note: These thermal configuration registers are RW/O hence, setting
those early prior to FSP-S helps coreboot to set the desired low
thermal threshold for the platform.

TEST=Dump thermal configuration registers PWRMBASE+0x150c etc on
Google/rex prior to FSP-S shows that registers are now programmed
based on 'pch_thermal_trip' and lock register BIT31 is set.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I1d6b179a1ed43f00416d90490e0a91710648655e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67462
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-09-10 19:00:56 +00:00
Subrata Banik 8b518776da soc/intel/meteorlake: Update `pch_thermal_trip` for MTL
This patch updates `pch_thermal_trip` as per Intel MTL vol1
chapter 14.

Additionally, dropped the `FIXME` tag for `pch_thermal_trip`.

TEST=Able to boot the Google/rex to ChromeOS.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I86f97c9245fe953832d3b408aa902d6a41e55651
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67461
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-09-10 19:00:49 +00:00
Subrata Banik f5afc1a5a2 soc/intel/meteorlake: Drop redundant `MCHBAR` programming in romstage
This patch drops redundant MCHBAR programming in romstage as bootblock
already done with MCHBAR setting up.

TEST=Able to boot Google/Rex to ChromeOS and MCHBAR is set to correct
value as per iomap.h

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ic2c05f47ab22dc7fe087782a1ce9b7b692ea157e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67455
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-09-10 19:00:39 +00:00
Subrata Banik a3ad319fbf soc/intel/meteorlake: Disable FSP UPDs related to virtualization
This patch disables FSP UPDs (`VtdDisable` and `VmxEnable`) as kernel
cmdline still passes `intel_iommu=off` to turn off virtualization.

BUG=b:241746156
TEST=Able to boot Google/rex to ChromeOS UI.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I21e178a93e311889f2ab7d1a08230d21b051f45e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67452
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-09-10 18:59:37 +00:00
Nicholas Chin e2542a1af1 Documentation/community: Update leadership meeting link
Update the Google Meet link to match the one found in the meeting
agenda and the reminders sent on the various community forums.

Change-Id: Ic4b8e0bb01e57850ea199c62b66a16e4d14de5c5
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67459
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Georgi <patrick@coreboot.org>
2022-09-09 20:28:12 +00:00
Jakub Czapiga 90072900b3 tests: Disable unnecessary warnings
Unit-tests had more strict warning setings than main build. Sometimes it
can cause unit-tests builds to fail even if code compiles correctly when
building normal coreboot image.

Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: Ia219ccc8631b069436497eb45a1552a0910f7aa1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67453
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <patrick@coreboot.org>
2022-09-09 19:07:44 +00:00
Tarun Tuli 2b523ce631 mb/google/brya: Invoke power cycle of FPMCU on startup
Add functionality such that the FPMCU is power cycled and has its reset
sequenced on boot.

This has been added such that we do not need to update the bootblock.
We are required to do this as bootblock exists in read-only flash for
devices that have already been manufactured and so have no method of
updating the sequencing there.

Power remains off during coreboot (after briefly being turned on in the
unchangeable bootblock).

Once control is handed over to the Kernel, it takes care of sequencing
the power and reset appropriately and ensures the FPMCU is unpowered for
>200ms on boot.

BUG=b:240626388
TEST=Confirmed FPMCU is still functional on Vell and Anahera.
Confirmed power is off for approximately 6 seconds on boot (target
>200ms).
Confirmed reset is de-asserted approx 5ms after power application
(target >2.5ms)

Change-Id: I9694f8837e0a72eaed42a5eeee92b0f120269086
Signed-off-by: Tarun Tuli <taruntuli@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66915
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-09-09 14:59:13 +00:00
Lean Sheng Tan 0f08d37d20 mb/prodrive/atlas: Set i225 PCIe RP as built in
Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com>
Change-Id: I4436a9d75cb06f2f51979f2bc57d48fa3dbb9e00
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67411
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-09 13:47:58 +00:00
Lean Sheng Tan dfe2ef082f mb/prodrive/atlas: Enable resizable BAR support
Allow up to 4GiB resizable BAR support.

Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com>
Change-Id: I097483ba8b4479211f67f29a42754d1a51379771
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67379
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-09-09 13:47:25 +00:00
Lean Sheng Tan 6435576c46 mb/prodrive/atlas: Configure Acoustic noise mitigation
- Enable Acoustic noise mitigation
- Set slow slew rate to fast/4 for VCCIA and VCCGT
- Disable fast slew rate for deep package C states for VCCIA and VCCGT

Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com>
Change-Id: Ia344d9d939c3323bac82afdf25d5fff81081f9c8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67380
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
2022-09-09 12:02:16 +00:00
ot_zhenguo.li e125bea5a0 soc/mediatek/mt8186: Enable lastbus debug hardware
Lastbus is a bus debug tool. When the bus hangs, the bus transmission
information before resetting will be recorded.

The watchdog cannot clear it and it will be printed out for bus hanging
analysis.

TEST=build pass.
BUG=none

Signed-off-by: ot_zhenguo.li <ot_zhenguo.li@mediatek.corp-partner.google.com>
Change-Id: Iff39486dfad556a3104b2f2b6811c34c2ded6954
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67437
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-09-09 10:45:08 +00:00
Runyang Chen 2b1fdb034a soc/mediatek/mt8186: Enable the protection of DEVAPC
Enable the protection for DEVAPC registers of AO domain.

TEST=build pass.
BUG=b:244250435

Signed-off-by: Runyang Chen <runyang.chen@mediatek.corp-partner.google.com>
Change-Id: I8535438d4c7da29c9dcd97be9a2af05ea4690064
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67434
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-09 10:44:30 +00:00
Runyang Chen 23a6d6c7e7 soc/mediatek/mt8186: Complete DEVAPC settings
In the previous patch (CB:60317), only basic settings were added. Now
complete DEVPAC settings on MT8186.

1. Update permission setting
2. Update master domain setting:
  - domain 4: SCP
  - domain 5: SPM
3. Set domain remap
  - MMSYS (4-bit to 2-bit)

TEST=test on kernel correctly.
BUG=b:204229221

Signed-off-by: Runyang Chen <runyang.chen@mediatek.corp-partner.google.com>
Change-Id: I40a9b115fb21b6b955fde358241f4483b85e3db3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67433
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-09 10:44:12 +00:00
Sen Chu a292f41fae soc/mediatek/mt8186: Enable CPU power hardware tracking for PMIC MT6366
1. There are two power sources for CPU:
   - Logic power (VPROC).
   - SRAM power (VSRAM_PROC).
2. There is a constraint between VPROC and VSRAM_PROC:
   - 0mV <= VSRAM_PROC - VPROC <= 250mV.

With software control, the constraint might not always hold. Therefore,
we enable hardware tracking from PMIC MT6366 to ensure the constraint
is met automatically.

BUG=b:236353282, b:241615706
TEST=meet the constrain correctly when adjusting the voltage.

Signed-off-by: Sen Chu <sen.chu@mediatek.corp-partner.google.com>
Change-Id: I6012c57e60c009f1d599b57aab1c2526ee789208
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67436
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-09 10:43:43 +00:00
V Sowmya ad0288a843 mb/google/nissa: Disable the stylus GPIO pins based on fw_config
TEST=Boot to OS on nivviks/nirwen and check that stylus GPIOs are
configured based on fw_config.

Signed-off-by: V Sowmya <v.sowmya@intel.com>
Change-Id: Ibbe9f379abe10a741642e11d4833d3a53489693a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66929
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-09 10:43:19 +00:00
Bora Guvendik 323bddb1bd mb/intel/adlrvp: Enable Cr50 TPM over SPI for adlrvp_rpl
Configure GPIO pins, add Kconfig options and enable
TPM device in devicetree.

Add H1 TPM IRQ GPIO pin in gpio.c

BUG=none
BRANCH=firmware-brya-14505.B
Cq-Depend: chromium:3774914
TEST=Boot the image and check the successful TPM
communication in verstage,romstage & ramstage from
coreboot logs.

Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: I1b4119373f69954d620dc09e637a7571312a5fc1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65987
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Selma Bensaid <selma.bensaid@intel.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
2022-09-09 10:43:01 +00:00
Tony Huang 8754965db1 mb/google/dedede/var/shotzo: Config I2C times for touchscreen/audio
Config I2C high / low time in device tree to ensure I2C
CLK runs accurately at I2C_SPEED_FAST (400 kHz).

EE measured touchscreen/audio runs at 385.5/397.9kHz after tuning.

BUG=b:244403643
BRANCH=firmware-dedede-13606.B
TEST=Build and check after tuning I2C clock is under 400kHz

Change-Id: I7d9503e5f92295432e31f09ae791eaa18eac9d4d
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67242
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
2022-09-09 03:39:48 +00:00
Bora Guvendik fa03a9f059 mb/google/brya/var/skolas4es: Configure _DSC for camera devices
Configure _DSC to ACPI_DEVICE_SLEEP_D3_COLD so that the driver skips
initial probe during kernel boot and prevent privacy LED blink.

BUG=b:194979741
BRANCH=firmware-brya-14505.B
TEST=Build and boot skolas to OS. Verify entries in SSDT.

Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: I3c32dd71ab454227b15913bda7f542230e5568db
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67021
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-09-09 03:38:55 +00:00
Matt DeVillier 2cf52d80a6 mb/*/{device,override}tree: Set touchpads to use detect (vs probed) flag
Historically, ChromeOS devices have worked around the problem of OEMs
using several different parts for touchpads/touchscreens by using a
ChromeOS kernel-specific 'probed' flag (rejected by the upstream kernel)
to indicate that the device may or may not be present, and that the
driver should probe to confirm device presence.

Since c636142b, coreboot now supports detection for i2c devices at
runtime when creating the device entries for the ACPI/SSDT tables,
rendering the 'probed' flag obsolete for touchpads. Switch all touchpads
in the tree from using the 'probed' flag to the 'detect' flag.

Touchscreens require more involved power sequencing, which will be done
at some future time, after which they will switch over as well.

TEST: build/boot at least one variant for each baseboard in the tree.
Verify touchpad works under Linux and Windows. Verify only a single
touchpad device is present in the ACPI tables.

Change-Id: I47c6eed37eb34c044e27963532e544d3940a7c15
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67305
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-09-09 03:38:19 +00:00
Lean Sheng Tan 003fe294fe mb/prodrive/atlas: Disable POST codes by default
Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com>
Change-Id: Ib1dd9826cedfd0a3f1ed719cf2e2927f09f783fe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67427
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-08 21:47:43 +00:00
Lean Sheng Tan d75deb1d22 mb/prodrive/atlas: Update VBT data binary
The previous VBT binary was not properly configured, there were DP
display issues on some of the ports and resulted in hangs when FSP
debug was used. The updated VBT fixes all the issues.

Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com>
Change-Id: I788240e36a9a90a5342ee9761f2c61ebf4caa9a4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67426
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-08 21:47:27 +00:00
Daisuke Nojiri 55fe9ee03c mb/google/grunt: Enable AC wake
This patch enables AC plug/unplug for resume.

BUG=b:188457962
BRANCH=grunt
TEST=Verified AC plug/unplug wakes up Treeya.

Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Change-Id: I10480f8224b909fefe42d46d7c03fc9d3fe5abfe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67389
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-09-08 21:47:13 +00:00
Daisuke Nojiri 8c24006711 mb/google/zork: Enable AC wake
This patch enables AC plug/unplug as resume signals.

BUG=b:188457962
BRANCH=Zork
TEST=Verified AC plug wakes up Ezkinil.

Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Change-Id: Ib1af6ff9f18544ec6a86e34588fb4d9e8cd3bab2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67262
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
2022-09-08 21:47:08 +00:00
Subrata Banik 4cc8a6ccce soc/intel/meteorlake: Hook up PAVP to Kconfig
Expose configuration of Intel PAVP (Protected Audio-Video Path, a
digital rights protection/management (DRM) technology for multimedia
content) to Kconfig.

TEST=Able to boot Google/rex to ChromeOS.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I416346995d744990054c8e0c839ada82c84b7550
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67423
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-08 16:42:05 +00:00
Dtrain Hsu 7afa1bae2b mb/google/brya/var/kinox: Update the DPTF parameters and fan table
Follow the Thermal_paramters_list-0902.xlsx to modify DPTF parameters
and fan table.

1. Modify CRT of TSR0 - TSR3 to 97.
2. Modify TCC offset to 6.
3. Update new fan table.

BUG=b:244657172
TEST=emerge-brask coreboot

Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: I751bc5442f64428c383034755cd5d74fbd0ea91e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67314
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-08 16:13:10 +00:00
Dtrain Hsu ed688abe51 mb/google/brya/var/kinox: Modify fan speed/duty table
Modify fan speed/duty table follow "Duty table.xlsx".

BUG=b:244262869
TEST=Boot to ChromeOS. Using SDV system, enter duty value, and then
system feedback fan speed.

Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: Id5e885b96624d5fc31f1d42e3582c3ab01e08458
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67307
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-by: Ricky Chang <rickytlchang@google.com>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2022-09-08 16:12:57 +00:00
Dtrain Hsu 384dfacbca acpi/acpigen_dptf: Increase DPTF_MAX_FAN_PERF_STATES to 20
The Kinox fan speed/duty table has 20 elements so raise the
DPTF_MAX_FAN_PERF_STATES from 10 to 20.

BUG=b:244262869
TEST=Boot to ChromeOS. Using SDV system, enter duty value, and then
system feedback fan speed.

Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: Iacd3ef0da926df5d174b215ab8ea4adc1a8b672e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67390
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Ricky Chang <rickytlchang@google.com>
Reviewed-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2022-09-08 16:12:04 +00:00
Ivy Jian 66757b121a mb/google/rex: Add WWAN poweron sequencing
The PCIe WWAN module used on rex requires control over 4 signals to
successfully power it on. It is desirable to do this before passing
control to the payload, because the modem requires a ~10 seconds
initialization phase before it can be used.

The corrected sequence looks like:
1) Drive device into full reset and enable power in bootblock
2) Deassert FCPO in romstage, after power rails stabilize
3) Deassert WWAN_RST#, then WWAN_PERST# in ramstage

BUG=b:244077118
TEST=FM350 could be enumerated via lspci
Measured signals to check start-up Timing Sequence, tpr/ton1/ton2.
Tpr = 572mS
Ton1 = 6.3s
Ton2 = 6.3+4.17ms

Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Change-Id: I6cda9348ef7f54efe5ba2358040596a1c2da1b13
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67332
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-08 16:00:04 +00:00