Add a new callout definition for AgesaGetTempHeapBase and displace
AgesaHeapRebase (which was merged too soon) in the ordering. Also
add its structure.
AGESA will be modified to ask coreboot for the location for temporary
storage of heap data at the end of InitPost. The old methodology is
to use 0xb0000 but the change will allow coreboot to determine the
location.
BUG=b:74518368
Change-Id: I0bc894d7842cf4b3eb728a90704277b17f4bf7be
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/26145
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The TP_Perf_STRUCT was missing from pi/00670F00. So I copied the file
from src/vendorcode/amd/pi/00630F01/Include/IdsPerf.h and removed
everything that we don't need. I did have to change
MAX_PERFORMANCE_UNIT_NUM so it matches the size used by pi/00670F00.
This struct is used to extract the timestamps from AGESA.
BUG=b:64549506
TEST=built on grunt
Change-Id: I06ec82348e3d10f2430c1192a925a49389ae4414
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/26235
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Was never used for the boards in our tree.
Change-Id: Ib9e9ab25ccb8d1d556fdeb8bb4c6558f25bb81b6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26041
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Vendor code is compiled as a library, thus the whole library is included
into the final image. However, not all procedures are required, they are
there because original AGESA code had them. We cannot remove them, in order
to facilitate porting of fixed AGESA code. Therefor add #if throughout the
code to allow the control if unneeded procedures will be build.
BUG=b:78610011
TEST=Build and boot grunt; build kahlee and gardenia.
Change-Id: I68f9e359b2331f715a3b85486c4181866985afdf
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/26135
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Vendor code has several headers included into source code that are not
needed in order to build them. Remove unneeded #include. This is part of
controlling the build of unneeded procedures within vendor code.
BUG=b:78610011
TEST=Build grunt.
Change-Id: Id7d451b6be564632836fc64fd343131edb85183a
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/26134
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
While built, this code was never called.
Change-Id: Ie8216d8f4636330d38ea02aab83bc9e440864f17
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21305
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Syncronise HT init code with f12 vendorcode.
Constructor for HT init is not required since init itself
is not called.
Change-Id: I0552c4d019c700f84d98473978afb18fe4eea1e8
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26040
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Create libagesa as a thin and deterministic archive file,
this could reduce build time and used space.
Change-Id: Icfd1f3fbf54f7e61ab528fa7686331182959c7d5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/22068
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Fix (assumed) regression with commit
ac63b41 vendorcode/amd/agesa: Fix variable length array declaration
The code used sizeof() on the struct where array length was
previously adjusted, but only f14 case was fixed accordingly.
Change-Id: Ib83660d5e102e13b4ffad19fb78f695ac4a871dc
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26036
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Definition of S_PSTATE only allowed PStateStruct[0], while it is
effectively used as a flexible array. Since sizeof(S_PSTATE) is
reduced here by sizeof(S_PSTATE_VALUES), we have to account for
that when calculating PStateLevelingSizeOfBytes.
In S_PSTATE context, PStateStruct[PStateMaxValue] is valid reference.
GCC 7.2.0 warns about an out of bounds array subscript.
```
CC libagesa/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuPstateLeveling.o
src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuPstateLeveling.c: In function 'PStateLevelingMain':
src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuPstateLeveling.c:524:65: error: array subscript is above array bounds [-Werror=array-bounds]
PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[k].PStateEnable = 0;
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~^~~
[1] https://gcc.gnu.org/onlinedocs/gcc/Zero-Length.html
Change-Id: If9598a951c6b882432689b677a956c44650c7083
Found-by: gcc (Debian 7.2.0-2) 7.2.0
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21297
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Remove Fch.h from being included in
src/vendorcode/amd/pi/00670F00/agesa_headers.h. It is not needed.
BUG=b:69220826
BRANCH=master
TEST=build Gardenia and Grunt systems.
Change-Id: Ifde58421d20c813ae5708b1d9c6ec76433051d33
Signed-off-by: Garrett Kirkendall <garrett.kirkendall@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/25808
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Remove unused header files in
src/vendorcode/amd/pi/00670F00/agesa_headers.h. This is a first
clean up. Hopefully more headers will be removed in other commits.
Header files cannot be removed at this time. They are used by files in
vendorcode/amd/pi/00670F00/.
BUG=b:77944801
BRANCH=none
TEST=build Gardenia and Grunt
Change-Id: I99b77f6ba41ded30122a01bbe709681312561436
Signed-off-by: Garrett Kirkendall <garrett.kirkendall@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/25644
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The term MTRR has been misspelled in a few places.
Change-Id: I3e3c11f80de331fa45ae89779f2b8a74a0097c74
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/25568
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This imports common BDK sources that will be used in subsequent
patches.
The BDK is licensed under BSD and will be reduced in size and optimized to
compile under coreboot.
Change-Id: Icb32ee670d9fa9e5c10f9abb298cebf616fa67ad
Signed-off-by: David Hendricks <dhendricks@fb.com>
Reviewed-on: https://review.coreboot.org/25524
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
AgesaHeapRebase is an optional callout that allows AGESA to use a
coreboot-managed heap base address. Its internal default location
is determined by AMD_HEAP_START_ADDRESS which is defined as 4 MB.
Add a #define that AGESA may use once the feature is available.
BUG=b:74518368
Change-Id: Id23455779b1c8c4931ad1a3122587e09ad237ecc
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/25456
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Fsp revison 7.x.2A.20 also updated MemInfoHob.h to fix SMBIOS Type 17
Offset 15h Speed report incorrectly issue.
BUG=None
TEST=Boot up with meowth platform and run dmidecode to see two dimm
entries under Type 17.
Change-Id: Ie1c4df162e75535ad458709452a76de01e31907e
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/25378
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
AGESA.bin was updated in the binary repo, so update the submodule pointer.
Among other changes, this added a callback "AGESA_HALT_THIS_AP", which
requires updated header files.
BUG=b:70338633
TEST=build kahlee.
Change-Id: I5a07f1c539d00aed34cfe45d6d7ef60c1dc56566
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/25183
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The Arch2008 spec describes an AmdS3FinalRestore Entry Point that
coreboot has been missing. Add the helper function that can call
into the blob to execute this.
BUG=b:69614064
Change-Id: Ic72feb0406cd1d0d5c23e391c2464e12c9e10007
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/23442
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Update the shared AGESA headers to 1.3.0.9.
This depends on 3rdparty/blobs/pi/amd/00670F00/ binaries updated
to the same version.
BUG=b:72679320
TEST=build and boot Grunt
Change-Id: I783b7318e8273913f753b70f12bfe8b71274e27f
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/23547
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Base patch to create Firmware Version Info (FVI) for CannonLake coreboot
platform using CannonLake FSP new feature.
Expectation is that, FSP will provide version information of all Firmware
ingredient its equip with (i.e. CPU Ref Code, uCode version, MCH Ref Code,
CSE Sku type, CSE version, System Agent Ref Code, OpRom Version, GOP version,
PCH Ref Code version etc.)
Change-Id: Ic388e036709190e8d5c5010f4ea87223291f21d0
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/23385
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch ensures MemInfoHob.h file can make use of existing UEFI
headers as is rather than redefining the same structure locally.
TEST=Download BIOS_Version_122.3 from external github and
build MemInfoHob.h without any compilation error.
Change-Id: Ic1e0ad94d8e40ac2aefe9fbcea7d684a97c864b4
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/23355
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The HeapAllocateBuffer and HeapDeallocateBuffer functions are not used.
Change-Id: I491a796d87afd0e37051f9caabfff3f70d4d803c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/22069
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
With no boards left using AGESA_LEGACY, wipe out remains
of that everywhere in the tree.
Change-Id: I0ddc1f400e56e42fe8a43b4766195e3a187dcea6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/18633
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* Move code from src/lib and src/include into src/security/tpm
* Split TPM TSS 1.2 and 2.0
* Fix header includes
* Add a new directory structure with kconfig and makefile includes
Change-Id: Id15a9aa6bd367560318dfcfd450bf5626ea0ec2b
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-on: https://review.coreboot.org/22103
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Update FSP header files to match FSP v77_12
Following fields have been added in FSP-S UPD:
- SkipPunitInit (Skip P-unit Initialization)
- HgSubSystemId (Sub system Vendor ID VGA)
Change-Id: I6c4c2580b2d0d76038b495be31744c04cc0dc959
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Reviewed-on: https://review.coreboot.org/22820
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Now that the AGESA binary is split into two sections load the
post-memory AGESA binary into ram. It needs to be an rmdoule
so that it can be relocated into ram.
agesawrapper_amdinitenv() entry
CBFS: 'VBOOT' located CBFS at [10000:cfd40)
CBFS: Locating 'AGESA_POST_MEM'
CBFS: Found @ offset 875c0 size 11c5e
Decompressing stage AGESA_POST_MEM @ 0xc757ffc0 (183452 bytes)
Loading module at c7580000 with entry c7580000. filesize: 0x2bafc
memsize: 0x2bb0d
Processing 1112 relocs. Offset value of 0xc7780000
AGESA call 00020001 using c75818fe
AGESA call 00020003 using c75818fe
Fch OEM config in INIT ENV Done
agesawrapper_amdinitenv() returned AGESA_SUCCESS
BUG=b:68141063,b:70714803
TEST=Booted kahlee.
Change-Id: Ic0454e0d6909cb34ae8be2f4f221152532754d61
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/22976
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
By splitting the binary files for platform initialization, the
post-memory code can be modified to stop executing in place (--xip).
This change creates two separate sections in CBFS for AGESA and loads
the appropriate file at the correct stage.
BUG=b:68141063
TEST=Booted kahlee with split agesa enabled.
Change-Id: I2fa423df164037bc3738476fd2a34522df279e34
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/22974
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
There is a new UPD PcieRpClkSrcNumber introduced in FSP V2.9.2 to
configure clock source(s) of PCIe Root Ports. This UPD is used
to disable clock source(s) of disabled PCIe Root Port which
has active device connected.
CQ-DEPEND=CL:*520658,CL:*520659
BUG=b:
BRANCH=None
TEST= Build and boot soraka
Change-Id: Ia4e4d22be8b00a72de68ddde927a090d3441a76e
Signed-off-by: Balaji Manigandan B <balaji.manigandan@intel.com>
Reviewed-on: https://review.coreboot.org/22692
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Stage addition to CBFS allows relocation to happen on the fly. Take
advantage of that by adding AGESA binary PI as a stage file so that
each instance will be relocated properly within CBFS. Without this
patch Chrome OS having multiple CBFS instances just redirects the
AGESA calls back into RO which is inappropriate.
BUG=b:65442265,b:68141063
TEST=Enabled AGESA_BINARY_PI_AS_STAGE and used ELF file. Booted and
noted each instance in Chrome OS build was relocated.
Change-Id: Ic0141bc6436a30f855148ff205f28ac9bce30043
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/22833
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Ensure that soc/amd/common/blocks/include is the only #include
path for the AMD common code. This removes the duplicate soc/amd/common
include as well using the correct #include header in AGESA.c.
BUG=b:69262110
Change-Id: I50d85b28514fd905df415f0cc052b9924ee4e741
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/22828
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Move AGESA related headers in soc/amd/common to
soc/amd/common/block/include/amdblocks.
BUG=b:69262110
TEST=Build with no error gardenia and kahlee (no code change, headers moved).
Change-Id: I5d3064625ddf8caaf370aabaf93165c6817f1ca0
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/22772
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Instead of repeatedly walking cbfs for the AGESA blob and parsing it
cache the resulting dispatcher value. There's only one dispatcher table
so use it. The resulting change is that this work is done one time per
stage.
BUG=b:70401101
TEST=Booted and noted only one lookup per stage.
Change-Id: Iaa4aecc384108d66d7c68fc5fb9ac1c3f40da905
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/22789
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Marshall Dawson