The COMe module connector implements 8 GPIO lines from the CPLD/EC pins.
Use the Kempld GPIO driver[1] to configure these pins in accordance with
the COM Express Module Base Specification [2].
TEST = Set different logic states for the pin configured as outputs and
check them with an oscilloscope.
[1] CB:47595 , Change-Id: Id767aa451fbf2ca1c0dccfc9aa2c024c6f37c1bb
[2] page 79-81, PICMG (R) COM.0 Revision 3.0 COM Express (R) Base
Specification - March 31, 2017.
Change-Id: I7d354aa32ac8c64f54b2bcbdb4f1b8915f55264e
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54380
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
There is no existing documentation on how `device ref` and aliases work
in the devicetree, and the behavior around devices not being in the same
location is difficult to discern as well as somewhat unexpected.
This should help prevent confusion leading to bugs such as the one fixed
by https://review.coreboot.org/c/coreboot/+/57298
Change-Id: I4b30f7d531cfc3453d6523a76084f1969125b4bf
Signed-off-by: Peter Marheine <pmarheine@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57354
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Platforms that rely on the FSP for parts of the hardware initialization
likely won't boot successfully when no FSP binaries are added during the
build, so print a warning at the end of the build in this case.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Suggested-by: Nico Huber <nico.h@gmx.de>
Suggested-by: Martin Roth <martinroth@google.com>
Change-Id: I6efc184ecc4059818474937fd31574f703c9bdc6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57368
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Haswell has its Mini-HD device and is at card0, so we need to search
for the PCH HD Audio device instead of using card0.
Change-Id: I2bc420fdbe9731ae835f63add85db79f04201da4
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34357
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch also adds LynxPoint and WildcatPoint-LP IOBP registers,
which is used to get the USB and SATA configuration values for
autoport.
Change-Id: I1f11640fdff59a5317f19057476f7e48c2956ab9
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41473
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
These defines are copy-paste leftovers from Kunimitsu. However, neither
Saddle Brook nor KBLRVP use memory-down, so drop the unneeded defines.
Change-Id: I396aeaa634f619be7be0ee97c0cab1c682f53ff2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57231
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Disable devicetree devices disabled in the `SerialIoDevMode` array.
These devices get disabled by FSP-S, and coreboot doesn't see them.
Change-Id: I8dbb45c96eae5188e5999df9a458f06f6b196adf
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57229
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Nico Huber <nico.h@gmx.de>
All KBLRVP variants select the `INTEL_LPSS_UART_FOR_CONSOLE` Kconfig
option and set `UART_FOR_CONSOLE` to `2`, so that UART #2 is used as
coreboot console. However, the LPSS console driver requires the LPSS
UART to be memory-mapped (and not I/O-mapped, like Super I/O UARTs).
KBLRVP variant RVP8 uses `PchSerialIoLegacyUart` for UART #2, which
makes FSP-S configure UART #2 in legacy, I/O-mapped mode. This most
likely results in the UART console not working after FSP-S has run.
This change updates RVP8 to use `PchSerialIoSkipInit` for UART #2, like
the other KBLRVP variants do.
Change-Id: Ic5c78f5895fe1dd5e7be6ef7aec3de6940dd2475
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57228
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
This is most likely a copy-paste remnant, and will never be needed for
RVP8: the SDXC device does not exist on PCH-H (and RVP8 uses a PCH-H).
Change-Id: I69059a88dcdb032beaab5fb03981dccbae0db02e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57227
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
The I2C #4 and I2C #5 devices do not exist on PCH-H. Disable the devices
using the PCH-H variants' overridetrees (the base devicetree enables I2C
#4), set the `SerialIoDevMode` entries to `PchSerialIoDisabled` and drop
inapplicable I2C #4 voltage settings.
Change-Id: I56f34fa2004993d2123ccd5c1008fd71682ec2bd
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57226
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Get rid of several unused PCH PCI device macros. These macros expand to
a call to the `pcidev_path_on_root_debug()` function, which only exists
to debug bad code. If needed, these macros should be reimplemented with
the `pcidev_path_on_root()` function instead.
Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 remains identical.
Change-Id: I366e064f3fe708b55fb381aee25b2795b1c61142
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55529
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
The `dev_optimize()` function is neither defined nor used anywhere in
the tree. Drop its unnecessary declaration.
Change-Id: I902bda3244c6496a04f364fad3ecbbdd118dd543
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57398
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
These two files are the only places where the `others` keyword is
capitalised. Use lowercase for consistency with the rest of the tree.
Change-Id: I6b785e28d1d00a11b802a44348a7132ceb6b599d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57399
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change adds a new Kconfig `SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES`
that can be selected by mainboard to reserve hotplug resources for
USB4 at the SoC level. `ADL_ENABLE_USB4_PCIE_RESOURCES` is dropped
from soc/intel/alderlake and instead the newly added Kconfig is now
used. This new Kconfig is added so that the same config can be used
across different platforms. In following changes, this Kconfig is
utilized by TGL as well.
Change-Id: Id7c359a0e255c43c2732f6cbe287bc7da14a46e3
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57124
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Mainboard information can be found in the included documentation.
Change-Id: I9dfc58bb99e14cd9dac2ac53afc0ea11d2252aa9
Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57191
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
There are multiple HECI clients in the CSE. heci_send_receive() is
sending HECI messages to only the MKHI client. Add an argument to
heci_send_receive() function to provide flexibility to the caller to
select the client for which the message is intended.
With the above change heci_send() and heci_receive() functions are
no longer required to be exposed.
In the follow-up patches there will be messages sent to one other
client.
BUG=None
BRANCH=None
TEST=Build and boot brya. HECI message send and receive to MKHI client
is working. Also, MEI BUS message to disable bus is working.
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Change-Id: Icde6d0155b62472b6a7caadc5fc8ea2e2ba6eb0c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57295
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Add tpch device information for thermal functionality under dptf
for alderlake soc based platform.
BUG=b:198582766
BRANCH=None
TEST=Build FW and test on brya0 board
Change-Id: Iad8e8bc0b7a104bbe582bc477936d0d00087f1d1
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57097
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Add new thermal control mechanism for pch device under dptf driver.
This provides support of different control knobs for FIVR.
BUG=b:198582766
BRANCH=None
TEST=Build FW and test on brya0 board
Change-Id: I035d2844b9ba6a9532ae006fc1c43e34cb94328a
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57096
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Configure I2C high / low time in device tree to ensure I2C
CLK runs under I2C_SPEED_FAST (400 kHz).
Measured I2C frequency just as below after tuning:
Touchpad: 386.7kHz
Touchscreen: 387.4kHz
Audio: 385.7kHz
P-sensor: 378.1kHz
BaUG=b:197247706
BRANCH=dedede
TEST=Build and check I2C clock is under 400kHz
Signed-off-by: stanley.wu <stanley1.wu@lcfc.corp-partner.google.com>
Change-Id: Ic5d5660181f36f161ae04cbf5003f6d7ad4bc16f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57297
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Henry Sun <henrysun@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Add MT53E512M32D1NP-046 WT:B supported memory part in the
mem_parts_used.txt and generate the SPD ID for the part. Manufacturer
is Micron, and the memory part is 1anm Tech, difference to 1xnm Tech
on MT53E512M32D2NP-046.
BUG=b:194223174
BRANCH=dedede
TEST=Build the gooey board.
Change-Id: I7b83126a2bf98bb9d0ca05d397c288e0d99ed781
Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57310
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add PMC IPC commands information for FIVR control functionality.
BUG=b:198582766
BRANCH=None
TEST=Build FW and test on brya0 board
Change-Id: Iccb43b7ba4f0765499bf1844efbbb526bd671a8f
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57095
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Currently maximum VBT data size for Jasper Lake is 8KB, but Bugzzy
would use VBT data over 8KB. This change makes use of Kconfig option to
increase the maximum VBT data size to 9KB for Jasper Lake.
BUG=b:194029827
BRANCH=dedede
TEST=build and boot bugzzy and verify fw screen is loaded
Change-Id: I0abe1ba5609b48a8a8b15f88bec28342ce26c78f
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57201
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Guybrush based boards must usa a dedicated eSPI alert#.
Must be open drain to prevent power leaks.
Keep guybrush reference board in-band since alert# may not be connected.
BUG=b:198409370
TEST=Build guybrush and nipperkin, boot guybrush
BRANCH=None
Change-Id: I4b23bfc6a1167aebfde5acd524fda043b63163dc
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57313
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Use the support from the previous patch to have coreboot lock the PAM
registers instead of the FSP when the lockdown configuration is set to
coreboot.
Change-Id: Ib6fce70d6b0386906850884880dadbf45597452d
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57185
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Use the support from the previous patch to have coreboot lock the PAM
registers instead of the FSP when the lockdown configuration is set to
coreboot.
Change-Id: I6ae22f9df4834508dfa304050fad44d45df45334
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57184
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Use the support from the previous patch to have coreboot lock the PAM
registers instead of the FSP when the lockdown configuration is set to
coreboot.
Change-Id: I10f859f30b260d012f0bc8755f32413d8b2cf267
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57183
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Rename two functions that have `walk` in their name but do not perform
any walk. The new names are derived from the comments just above these
functions' definitions. Also, remove these now-redundant comments.
Change-Id: I380a5b60b3f4e820e8f6d6f960826de97c0446be
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57361
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Error out when the FSP binaries that are supposed to be added aren't
specified.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Suggested-by: Nico Huber <nico.h@gmx.de>
Change-Id: Ie5f2d75d066f0b4e491e9c8420b7a0cbd4ba9e28
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57219
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Like USE_AMD_BLOBS and USE_QC_BLOBS in the case of the AMD and Qualcomm
repos, FSP_USE_REPO controls if the Intel FSP repo will get checked out
and will be available during the Jenkins runs. ADD_FSP_BINARIES will get
selected in drivers/intel/fsp2_0/Kconfig when FSP_USE_REPO is selected.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I72faa6f9e5f2b06ab7cd43595ae0b49bf4d39630
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57349
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
The overrides set the options to the same value as drivers/intel/fsp2_0/
Kconfig does, so drop the overrides.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I53922786382a2e7d29b3df560a1998f41e1d2ea8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57350
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Normally, selecting FSP_USE_REPO will select FSP_FULL_FD which then will
configure the proper paths for FSP_M_FILE and FSP_S_FILE. The override
in these two boards caused FSP_M_FILE and FSP_S_FILE being empty despite
ADD_FSP_BINARIES being selected by FSP_USE_REPO which is an invalid case
that needs to be avoided, so remove the board-level override of those
two options.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I20c8cebea8327d59f0f33d05b824a74bf2121f4b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57347
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
The ADD_FSP_BINARIES override in the mainboard's Kconfig caused this
option to not be selected when FSP_USE_REPO is selected. Remove the
override to fix this problem. These two boards are the only ones in tree
that had an override for this option, so now the ADD_FSP_BINARIES option
is only defined in drivers/intel/fsp2_0/Kconfig.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I23439f3134eef9460625addbff7efd64c5f65ae5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57346
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This option is neither selected nor usable for the only remaining SoC
that uses this code, so drop the remaining parts. configure_hudson_uart
isn't called anywhere and isn't even compiled, since it's guarded by an
#if CONFIG(HUDSON_UART) block and the HUDSON_UART Kconfig option isn't
selected anywhere. Both the offsets used in the iomux_write8 calls and
the UART controller itself aren't listed in the BKDG #52740 Rev 3.05 for
the AMD Family 16h Models 30h-3Fh APUs which is the only SoC that uses
this code, so the code didn't even apply for this chip.
TEST=Timeless build for pcengines/apu2 results in identical binary.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I3f462d1f83a0f1ba851329ebebb1f3263267fdc6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56785
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This config selected ADD_FSP_BINARIES even though HAVE_INTEL_FSP_REPO is
only defined for Apollolake and not Geminilake that resides in the same
SoC directory and uses the same Kconfig file. This results in the paths
to the FSP binaries not being defined, in which case the
ADD_FSP_BINARIES option shouldn't be selected.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I95123c4930b44a3b76c87768e130eb7359bbf625
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57351
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Since the FSP binaries for Picasso are present in the amd_blobs repo,
select the ADD_FSP_BINARIES option if the Kconfig option to check out
that repo is set.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I9a8571730cf271ad5e113e5df87700882b3c5475
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57348
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
This patch ensures mp_run_on_all_aps() is passing 'MP_RUN_ON_ALL_CPUS'
macro rather hardcoding `0` while running `func` on all APs.
Change-Id: Icd34371c0d4349e1eefe945958eda957c4794707
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57342
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
EGPIO132 is the last documented GPIO on the GPIO controller in the NDA
version of the BKDG for AMD Family 16h Models 30h-3Fh Processors (#52740
Rev 3.06) which is the only SoC using this code, so define
SOC_GPIO_TOTAL_PINS as 133, since the internal GPIO numbers are
0-indexed. This definition will be needed the subsequent patch that'll
add the remote GPIO support to the common AMD GPIO code to make sure
that the compiler can optimize out the code path needed to support the
remote GPIO access which isn't available on this platform anyway.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I877d462c5e753c9bbb3461dbb10cde2adc2cb12c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56809
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
If a USB_MUX_EVENT happens while the AP is in S3 during powerdown
transtion (S0->S3->S5), this will cause the device to boot again after
it has finished sequencing down to S5. Since S3 is not POR for ChromeOS
devices anymore, change this event to wake from S3 and S0ix to just
S0ix.
BUG=b:197039097
TEST=abuild
Change-Id: I91e5e0ab8301377817875b6fa9e3c0e1f96c1465
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57341
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Add NixOS configurations for bootable live systems containing a set of
tools which might be useful for firmware development in general and for
working on coreboot.
There are two configurations provided. One for console-only and a
graphical one, which is mostly the same as the console image but it
comes with Gnome Shell as window manager and some graphical tools in
addition.
An image can be built using `build-console.sh`, respectively
`build-graphical.sh`. The resulting iso image can be found in
`result/iso/`.
The console image results in ~700MB, while the graphical one results in
~2GB.
Change-Id: Iaf49d198e99781434bd89d2a8a125a4988b77e1c
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50194
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
This patch updates debug message to specifically the case when SMBIOS
table 7 write would abort due to either `unknown` CPU or CPU `doesn't
have support for deterministic cache cpuid leaf`.
Change-Id: I288593b3f78ab858bf66c689e7cfb6ba2ff746d0
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57337
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Don't attempt to fill the SMBIOS table if the CPU doesn't support
deterministic cache CPUID.
TEST=Able to fix the hang issue seen on ASRock E350M1 with commit hash
e2b5fee.
Change-Id: Id65dc963e235f7080370a32cf69bcc4bee94d28f
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57306
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Swift Geek (Sebastian Grzywna) <swiftgeek@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
`cpu_get_cache_info_leaf()` function is responsible to report leaf
value for CPU that have support for deterministic cache cpuid. As per
available datasheets from AMD and Intel the supported CPUID leafs are
0x8000_001d for AMD and 0x04 for Intel. Hence, this CL skips returning
default leaf value as `0`.
TEST=Verified fixes: e2b5fee3b0 (arch/x86: smbios write 7 table using
deterministic cache functions) hang issue on ASRock E350M1.
Change-Id: Iee33b39298e7821ac5280d998172b58a70c8715b
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57305
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Maxim Polyakov