Picasso currently declares the BAR region between TOM and IO_APIC_ADDR.
This region includes MMCONF. We don't want to map any PCI BARs in this
region. This also matches what intel does.
See soc/intel/braswell/acpi/southcluster.asl for an example.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I9474fd6ac75a7245b3c35151c38186e913219bb0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50894
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
This differs slightly from picasso. The PCI BAR region is between TOM1
and CONFIG_MMCONF_BASE_ADDRESS. This matches what the Intel platforms
are doing. It also matches what linux derives from the e820 tables:
> [mem 0xd0000000-0xf7ffffff] available for PCI devices
Picasso currently declares the region between TOM and IO_APIC_ADDR.
This region includes MMCONF. We don't want to map any PCI BARs in this
region.
TEST=Boot majolica and check logs
pci_bus 0000:00: root bus resource [io 0x0000-0x0cf7 window]
pci_bus 0000:00: root bus resource [io 0x0d00-0xffff window]
pci_bus 0000:00: root bus resource [mem 0x000a0000-0x000bffff]
pci_bus 0000:00: root bus resource [mem 0x000c0000-0x000dffff]
pci_bus 0000:00: root bus resource [mem 0xd0000000-0xf7ffffff]
pci_bus 0000:00: root bus resource [bus 00-3f]
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I4ff02012795e2166e3a4197071b1136727089318
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50893
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This will also be used for cezanne. Stoney also has a similar function,
but it hard codes the scope path. I didn't have a device setup to test
if switching to this function was a no-op. So I left it.
TOM2 isn't used by any ASL, so we could remove it later.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I7c8f476a7735fea61a3244b97988e3ead3b42e79
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50892
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
The devices were copied from picasso with the following modifications:
* UART{2,3} were deleted
* I2C{0,1} were added
* eMMC was removed since it hasn't been validated
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Iddfb975e9292785d0951dd7bb31c1997d2185abd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50573
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Enable the building of guybrush variants and configure the first variant
also called guybrush.
BUG=b:180419462
TEST=builds
Signed-off-by: Mathew King <mathewk@chromium.org>
Change-Id: I3bed620378f9152277b4943ead1017f61a21ea82
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50845
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Move wait for TXT and early ME init out of `collect_system_info`, and
then drop the first call to it. Also drop a useless register read.
Tested on out-of-tree HP 630, still boots.
Change-Id: I9b167f44cbd96864bf1e8b616576af19cbbfd90c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49581
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
As per document 336067-007US (C620 PCH datasheet), add macros for all
bits in the SMI_STS register. These will be used in common code.
Change-Id: I1cf4b37e2660f55a7bb7a7de977975d85dbb1ffa
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50915
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This file is never built. Plus, `CONFIG_STACK_BOTTOM` does not exist.
Change-Id: I111b20e3443dca701ee8666d44261a00a161d83f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50909
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
The SoC can be selected in the corresponding option choices directly.
Change-Id: I226c500dd7370f4610b0117a9e70d727f1d66951
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50908
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Rowan was the only Oak variant that used TPM2. However, it was removed
in commit 0aa1f9e905 (google/oak: Delete rowan). Since the other three
variants use TPM1, remove now-unnecessary Kconfig options from Oak.
Change-Id: If19df00463f63f1101475f59b5ecea5a9724a9ab
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50907
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Replace it with `HAVE_ACPI_RESUME`, which defaults to n for this board.
Change-Id: Ibb07c0d001ded8d7ff991bf63607872bf4b79c8e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50904
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
CrashLog is a diagnostic feature for Intel TGL based platforms.
It is meant to capture the state of the platform before a crash.
The state of relevant registers is preserved across a warm reset.
BUG=None
TEST=CrashLog data generated, extracted, processed, decoded sucessfully on delbin.
Signed-off-by: Francois Toguo <francois.toguo.fotso@intel.com>
Change-Id: Ie3763cebcd1178709cc8597710bf062a30901809
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49943
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Remove extra parameter in phy_dll_bypass_set, since it does not
depend on the channel at hand.
Signed-off-by: Moritz Fischer <moritzf@google.com>
Change-Id: Iae09a6053daf58bf12604e1903c754dc9f1e986f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50965
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: ron minnich <rminnich@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Sometimes the USB device will be lost after DUT resume.
Adjust USB phy settings for all USB ports to fix the failed symptom.
BUG=b:174538960
BRANCH=zork
TEST=USB devices stay connected after running suspend test
Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Change-Id: I25bca968bb4a740161b36e2082d1e500ae648712
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50020
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Peichao Wang <pwang12@lenovo.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch includes the romstage changes for the
shadowmountain board.
BUG=b:175808146
TEST= Build and boot shadowmountain board till early ramstage.
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Change-Id: Ifd0bbcea9d4916d82bb1e3c275dd79d97a79727a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49731
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Little point to replicate a string already provided both
as a global Kconfig and global mainboard_part_number.
Change-Id: I1fd138c711ebbb37c39b2c8f554b1f2e1a364424
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50719
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: ron minnich <rminnich@gmail.com>
Added file acpi/sleep.asl is really a copy from persimmon with debug
statement and some comments removed.
Added file acpi/gpe.asl is slightly modified copy from persimmon with
changes that seem valid, considering the other changes present in ASL
for the board.
Rename existing usb.asl to usb_oc.asl for consistency.
Change-Id: I493ad1c110380378bad80e49cd888f47fbe41a92
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50649
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Do this for consistency with later platforms.
Change-Id: Ia4903b40a8f617c59868aaa116115fa23603438c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50645
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Variable OSVR had a static value of 3 and OSFL() did not
actually call _OSI or _OS methods.
The conditional in HDA _INI method of OSVR is dropped and
use of DMA NoSnoop attribute remains disabled to retain
previous behaviour. For soc/amd/picasso a different decision
was made in CB:40782 as HDA _INI method was just dropped and
default configuration enables use of DMA NoSnoop attribute.
Change-Id: I967b7b2afbb43253cccb4b77f6c44db45e2989e4
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50592
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
CB:40785 ("soc/amd/hda: Move HDA PCI device from DSDT to SSDT") moved
the HDA device in ACPI from DSDT to SSDT. During this, _INI method
generated in SSDT incorrectly inverted the values for NSEN, NSDO and
NSDI. This change fixes the mistake so that the _INI in SSDT matches
the original _INI in DSDT for HDA device.
Change-Id: I294b561a479b77ab8afb5f3e0de367ad24f3a764
Reported-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50927
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This is already the case on x86 but not on the ARM platforms, and
{read,write}[bwl] are using volatile pointers, too, so follow suit.
Change-Id: I6819df62016990e12410eaa9c3c97b8b90944b51
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50918
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Introduce a new flag to disable turbo called 'cpu_turbo_disable'.
Keep the default and enable turbo on all platforms.
Change-Id: Ia23ce4d589b5ecc5515474eea52a40788ae3d3b5
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50797
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
coreboot sets up CLK_PM, ASPM, and L1ss automatically based on related
bits in "Link Capability Register" and "L1 PM Substates Capabilities
Register". coreboot overrides these configs even if the driver sets
them. Therefore, setting up CLK_PM, ASPM, and L1ss in the driver is
redundant and useless.
BUG=b:177955523
BRANCH=zork
TEST="lspci -vvvv" prints are identical with and without this patch;
LV2_LINK_CTRL(0x90) is 0x00110102 with and without this patch.
Signed-off-by: Victor Ding <victording@google.com>
Change-Id: I17c19f4271da426ac2b926b948378dc88131e95a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50871
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Now that multiple device trees are supported (chipset, base,
override), base_chip_instance parameter for override device needs to
be set to the base chip instance of the corresponding device in
base/primary tree. This can be achieved by using `get_chip_instance()`
instead of using base_dev->chip_instance in `update_device()`.
TEST=Verified that coreboot.rom generated using timeless shows no
change for all boards.
Change-Id: I42e3f4b83c55f3479b95dbbd7a3721558c32b1c8
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50868
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
coreboot sets up certain configs (e.g. L1ss) based on the device's
reported capacities; however, this BayHub lv2 driver modifies some
of its capacities after coreboot uses them. Therefore, coreboot may
make incorrect configs based on out-of-date capacities.
This patch moves the driver from ".init" to ".enable" so that the
capacities are set before the rest of coreboot queries them.
BUG=b:177955523
BRANCH=zork
TEST="lspci -vvvv" reported "PCI-PM_L1.2-" and "ASPM_L1.2-" on L1SubCtl1
of both PCI device "00:01.3" and "02.00.0"
Signed-off-by: Victor Ding <victording@google.com>
Change-Id: I857b7c7c6732bbd26de561052affa3a3e7e25737
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50869
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Add rank_mask based on the rank number and iterate based on that rather
than iterating all values.
Note: LPDDR4 uses a different rank mask.
Ported from u-boot.
Signed-off-by: Moritz Fischer <moritzf@google.com>
Change-Id: I1bff9d20d3d66984c49073aa21212708039d578f
Signed-off-by: Moritz Fischer <moritzf@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50888
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Add rank_mask based on the rank number and iterate based on that rather
than iterating all values.
Note: LPDDR4 uses a different rank mask.
Ported from u-boot.
Signed-off-by: Moritz Fischer <moritzf@google.com>
Change-Id: I85f449af9f946ad677808800cdbe59e2001202c3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50887
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: ron minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This adds the SMM finalization to Cezanne.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I1a2b433d92df2a76979e2e6a3d1dde996303ba78
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50801
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This adds the rkclk_ddr_reset() function equivalent for the RK3399.
Signed-off-by: Moritz Fischer <moritzf@google.com>
Change-Id: If1da85064d75bdf49b7555d09257409443c25e8a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50889
Reviewed-by: ron minnich <rminnich@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add support for resetting PHY PCTRL for both channel 0 and 1.
On the ROCKPro64 board this allows getting past a pctl_cfg() failure.
Signed-off-by: Moritz Fischer <moritzf@google.com>
Change-Id: I9f807e318ffc63c568d04518c3edd02c1064e185
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50890
Reviewed-by: ron minnich <rminnich@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Clear PI_175 interrupts before attempting training in all relevant
calls.
Ported from u-boot.
Signed-off-by: Moritz Fischer <moritzf@google.com>
Change-Id: Ib73f58265db62494282dbec42ec4bf2950617e12
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50886
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: ron minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This is a µATX mainboard with a LGA1151 socket and two DDR4 DIMM slots.
There are two possible BOM configurations: Sid has no legacy devices,
whereas Manny provides two serial ports, a parallel port, a PCI slot
and PS/2 keyboard/mouse connectors. These boards also have different
Super I/O models: Manny uses an ITE IT8625E, whereas legacy-free Sid
comes with an ITE IT8656E instead.
This coreboot port has been done using a Sid board, thus support for
Manny-specific features is missing. Booting should still be possible,
though: none of these legacy features is essential.
The board has an unpopulated 6-pin header, wired to PCH UART 2. This
can be used to retrieve coreboot logs.
Working:
- Both DIMM slots (Micron CT4G4DFS8213.8FA11, Hynix HMA851U6AFR6N-UH)
- PCH SerialIO UART 2 to get coreboot logs
- Rear USB ports
- Realtek RTL8111 GbE NIC
- Integrated graphics on DVI with libgfxinit
- At least one SATA port
- Flashing internally with flashrom
- S3 suspend/resume
- VBT
- SeaBIOS 1.14 to boot Arch Linux (kernel linux-5.10.15.arch1-1)
Untested:
- Audio
- VGA: DP2VGA chip uses DDI E, and libgfxinit doesn't support DDI E yet
- Front USB headers
- Non-Linux OSes
- PCI slot
- IT8625E peripherals: serial, parallel and PS/2 ports
Change-Id: Iadf11c187307a24b15039a5a716737d9d74944e6
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48386
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The new name is more consistent with the rest of the MSR definitions.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I5666d9837c61881639b5f292553a728e49c5ceb2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50855
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Raul E Rangel