The pspv[1,2]_mbox struct is only used in psp_gen[1,2].c, so move those
definitions from the common psp_def.h to the specific psp_gen[1,2].c
files. Also fix the struct name in the comment about pspv1_mbox.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I0c95e9a6e292b90e0d147c57f59828a9b41e4b82
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63960
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Now the bootblock is not limited to 64K so integrating vboot into the
bootblock reduces the binary size. intel/apl is an exception since the
bootblock size is limited to 32K.
Change-Id: I5e02961183b5bcc37365458a3b10342e5bc2b525
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52788
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Sabrina added the ALERT_ENABLE bit. Set it to enable the eSPI_ALERT#
line.
BUG=b:227282870
TEST=Boot skyrim and verify keyboard works
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I2a193ca454692bf13b707401079bd9edf026ef5f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63843
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
This bit is new on sabrina. We need to enable it after initialization
has completed.
BUG=b:227282870
TEST=Boot skyrim to OS and verify keyboard works
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I795275993589e20c1d09674232ecff782c491335
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63842
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
We don't currently have ALIB plumbed through. Disable the ALIB call to
remove ACPI errors during boot.
BUG=b:228496169
TEST=Boot skyrim and no longer see ALIB errors
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Iad45bcda326597ebfc8b9c403de5b4a934b0bbc6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63841
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use BHD instead of BDT as the name of cookie macro. Use L2 to make it
clear it is for level 2. The 'BHD2' is misleading, which is going to
be used for combo entry. The definition in psp_verstage is also changed.
Change-Id: Ia10ac5e873dab6db7d66e63773a7c63f504950b2
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55411
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
PSP verstage can start at address 0 and use 200KB of PSP SRAM for
execution. Modify both the PSP SRAM start address and size for use by
PSP verstage.
BUG=b:220848544
TEST=Build Skyrim BIOS image with PSP verstage enabled.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I73e13b82faa0f443570a0c839e7699a79bdae024
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63732
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
In Sabrina, PSP verstage uses a unified SVC call ID with sub-commands.
Update the SVC calls for Sabrina to pass the SVC_VERSTAGE_CMD (command
ID) with individual subcommands and the corresponding parameters.
BUG=b:220848545, b:217414563
TEST=Build the Skyrim BIOS image with PSP verstage enabled.
Change-Id: I56be51aa1dfb00e5f0945014600de2bbbec289db
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63729
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Commit 3e1943ec46 (soc/amd/cezanne: Force
resets to be cold) forced all resets on Cezanne to be cold resets to
work around a bug. Since the bug is fixed on Sabrina, this workaround
copied over from the Cezanne code isn't needed here, so sort-of revert
what the patch referenced above changed for Cezanne in the Sabrina code.
BUG=b:229105416
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I785e43124a9a969eeb129454e6e15dc245625250
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63741
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
PSP needs SPL file to boot. Introduce the support to add SPL file.
Currently Sabrina does not have a specific SPL file. Use Cezanne SPL
file as a placeholder.
BUG=b:224618411
TEST=Build and boot to OS in Skyrim after adding Sabrina specific SPL
file.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I222bb81b2babddc778b2cff858ef7979f85ac0e6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63313
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Chause doesn't get to x86 bootblock without the SPL table binary in the
PSP directory table, so I assume that Majolica won't get to x86
bootblock either, since the Cezanne SoC default is not to include any
SPL table binary. This was caused by a combination of
commit 6c5ec8e31c (amdfwtool: Add options
to support mainboard specific SPL table) that caused a regression in
amdfwtool and commit c5b912f788
(soc/amd/cezanne: Allow to specify SPL table path in Kconfig) that
removed the default for the Cezanne SoC. Fix this by adding the default
SPL table file back to the fw.cfg file which will get ignored by
amdfwtool when a mainboard selects SPL_TABLE_FILE and specifies another
SPL table binary.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ica960e5422da50899a2d9c192863188174e0bcff
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61896
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Since Sabrina uses the image slot header (ISH) that depends on the AMD
A/B recovery scheme that depends on the multi-level PSP directory
support, the multi-level support gets automatically selected by passing
Sabrina as SoC name to amdfwtool, so passing the --multilevel command
line switch to amdfwtool isn't needed.
TEST=Timeless build results in identical binary for chausie
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I98154d5b47daca6ae7952ffd3175d98ea3e01845
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63235
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
The fch_i23c_pad_init implementation was written without looking at any
reference code and turned out to not work properly on hardware. Before
this function writes to the MISC_I23C_PAD_CTRL registers, the value read
back is 0x3000003c which results in the I2C bus communication to work
while the 0x300003fc the code writes to the register breaks the I2C
communication. Removing the code that sets bits 6..9 fixes the I2C bus
communication.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: Ie6758b3d13c59b20ce810225fca8a365713b7a2b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63234
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Contradicting the PPR #57243 version 1.56, the I2C3 pad control register
in the MISC ACPIMMIO region is the same new I23C pad type as the
corresponding registers for I2C0..2 and not the older I2C pad control
register type used on Picasso and Cezanne. All I2C pads being of the new
I23C type is in line with the GPIOMUX settings for the pins used by
I2C0..3 that can alternatively connect the pins to an I3C controller.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I51b0ddf8ba2ccfee823e3d4d26a77b11825b1029
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63233
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
According to PPR #57243 version 1.56, the IOMUX setting 2 of the pins 19
and 20 is the I3C3 controller and not the I2C3 controller.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I9688f1816aa840c64441495ed451997a474b306f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63232
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
When masking out bits with an and mask, the bit mask needs to be
inverted.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I9739d7150e230fbbe6523413de9c07d7340f3c61
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63222
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
I23C_PAD_CTRL_SLEW_N_SHIFT is 6 and not 7 which matches both with the
PPR #57243 revision 1.53 and with I23C_PAD_CTRL_SLEW_N_MASK which covers
both bits 6 and 7.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I622717bebaffe34b6df5e578b082dc10e2a98256
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63216
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
On x86 ramstage is always relocated at runtime in cbmem so there is no
need to have this configurable in Kconfig.
Change-Id: I01b2335d0b82bea8f885ee5ca9814351bbf2aa3c
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63215
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Now that the amdfwtool support for Sabrina is in place, change the
SoC name parameter passed to amdfwtool from Cezanne to Sabrina.
The fw.cfg file still points to the Cezanne binaries, but since
commit 9cb0a05dfb (soc/amd/sabrina: Add
prompt for AMDFW_CONFIG_FILE) this can be overridden via the Kconfig
config file in the build. As soon as the Sabrina PSP binaries are
available in 3rparty/amd_blobs, the fw.cfg file will be updated to use
the correct ones for Sabrina.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I53a8de222e39bd2b92c07661b6c52a02fb651609
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63189
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The PSP_S0I3_RESUME_VERSTAGE Kconfig symbol is only defined in the
Cezanne Kconfig, so drop this from the Sabrina makefile.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I9571a302d427981cdf750a1cb3b7f4db9d61a87c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63188
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The way to select the pads has changed from Cezanne.
BUG=b:226635441
TEST=Build skyrim
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I96baf6b9c169ed61d221352b29ac676bca40da21
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63095
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This is done to work around a hang when SMU writes to port80. Remove it
after the issue is fixed.
BUG=b:224618411
TEST=Build and boot to OS in Skyrim.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: Ic152c295954d33ef1acddb3b06f0c6bbfbfb38ae
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63122
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
SMU locks up sometimes if the port80 enable bit is cleared in the ESPI
Decode register. Add a config to choose between clearing the entire ESPI
Decode Register vs retaining the port80 enable bit.
BUG=None
TEST=Build and boot to OS in Skyrim.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: Ia5ee012ac4858d6dd43827274169edf622a70489
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63118
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
The Sabrina microcode update files are 3200 bytes large and not 5568
like it is the case on Cezanne where this file was originally copied
from.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I12209d523096781195ba8957ec797d8c80eecbe5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63127
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Fixes building with clang.
Change-Id: I7027f3681e18b8ca0d2f0c899412806082846463
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63050
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
SMMINFO is already set up in S5, so it should be skipped in S3 resume
TEST=builds
Change-Id: I58e25075a007505e53962525ec4d9acd2ce6c7ae
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63088
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
SMMINFO is already set up in S5, so it should be skipped in S3 resume
TEST=builds
Change-Id: Ia58000ce9dac5ecb69ca39354f7775524e439bd0
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63087
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
SMMINFO is already set up in S5, so it should be skipped in S3 resume
BUG=b:194990818
TEST=Build guybrush
Change-Id: I30ee6d7006ddac4dbdae9825bd4fa6eac7fd48cb
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63025
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
For SoC that don't support LPC any more the definition of the PSP soft
fuse chain bit 15 has changed. Earlier SoCs that still supported a
physical LPC bus used this bit to determine if the I/O port 0x80 POST
code are sent to LPC or eSPI. Newer SoCs like Sabrina don't have a
physical LPC bus any more and on those this bit selects if the PSP debug
output is sent to the SoC's MMIO UART or an UART on I/O port 0x3F8 that
the needs to be decoded to eSPI.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I0bffb6efacc585a1d02a0455b32f7cf8662b3232
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63049
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
This will allow configuring the concerned config through an external
defconfig file.
BUG=None
TEST=Ensure that AMDFW_CONFIG_FILE is configurable.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I97817a822c8c41822e699adc31f0e7452f93fdb9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62971
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The Pubkey(0), PSP bootloader(1) and IKEK(0x21) should be put to
level 2 only for A/B recovery for Sabrina, which is going to be the
long term and A/B recovery layout only. So the amdfwtool should be
changed for Sabrina.
The old levels of these 3 FWs are for Cezanne, which doesn't use AB
recovery now. Just set the specific field levels in generic Cezanne
folder for demo. Leave the fw.cfg in Guybrush unchanged.
Change-Id: I11092b52927b2c526a5be719104ba39a790b6fa8
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62329
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
The current behavior does not actually check if a device is present
before enabling the corresponding gpp_clkx_clock_request_mapping bits
which may cause issues with L1SS. This change sets the corresponding
gpp_clkx_clock_request_mapping to off if the corresponding device is
disabled.
BUG=b:202252869
TEST=Checked that value of GPP_CLK_CNTRL matched the expected value
when devices are enabled/disabled, checked that physically removing a
device that is marked as enabled also disables the corresponding clk req
BRANCH=guybrush
Signed-off-by: Robert Zieba <robertzieba@google.com>
Change-Id: I77389372c60bdec572622a3b49484d4789fd4e4c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61259
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
TypeId0x01_PspBootLoader_AB_Stage1_CZN.sbin is bootloader for A/B
recovery. Both bootloader can be put in the fw.cfg. The amdfwtool
decides which booloader is dropped in the directory.
Change-Id: I099b4c98d64dba935bf3ea2b7f191da83b9bd95e
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56937
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
On boards where PSP uses ESPI to write postcodes, update the verstage to
do it after ESPI initialization.
BUG=b:224543620
TEST=Build and boot to OS in Nipperkin. Ensure that there are no
attempts to write the post code from PSP verstage before ESPI
initialization.
Change-Id: I1b78931c741c75dc845c9b34e3b2b896221f2364
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62880
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mohan Viswanathan
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Despite the SMBus device being function 0 of the FCH PCI device, the
MMIO resource of the FCH IOAPIC is on the LPC device which is function 3
of the same PCI device, so move the FCH IOAPIC initialization code to
the LPC device. Since the HPET was enabled in the same function, also
move it to the LPC device initialization.
TEST=On Mandolin both IOAPICs are still correctly detected by Linux.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I585afd463c1c00cd87ced0617e7802503c5deba5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58334
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Some counters are not being initialized and are relying on mainboards to
set their values. If the mainboards have not implemented these
functions it leads to indeterminate behavior.
BUG=b:224987813
TEST=builds
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: I254e26080319478b1b5b1f5c353a7966cfac63b3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62872
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Some counters are not being initialized and are relying on mainboards to
set their values. If the mainboards have not implemented these
functions it leads to indeterminate behavior.
BUG=b:224987813
TEST=builds
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: I14903980fd921cad24c39cadd533349c14cc1cd3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62871
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Some counters are not being initialized and are relying on mainboards to
set their values. If the mainboards have not implemented these
functions it leads to indeterminate behavior.
BUG=b:224987813
TEST=builds
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: I8d4f5b1124d4017b04bcaf7044216fd696dce63d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62863
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
The current SMM framework only allows the mainboard code to handle GPEs.
i.e., Events 0 - 23. This change allows the mainboard code to handle any
SMI events not handled by the SoC code. This will allow the mainboard
code to handle `SMITYPE_ESPI_SMI`.
BUG=b:222694093
TEST=Build guybrush
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I81943e8cb31e998f29cc60b565d3ca0a8dfe9cb2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62598
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Now that SMM can write to CBMEM we can simply replay the transfer buffer
cbmem console to move it into the main cbmem console.
replay_transfer_buffer_cbmemc() relies on the EARLY_RAM linker symbols.
Since the SMM rmodule get linked with a different linker script than
bootblock/romstage it doesn't have access to these symbols. In order to
pass these symbols into SMM, we parse the bootblock.map file and
generate an early_ram.ld script. This script is then used when linking
SMM.
I replay the buffer in `smm_soc_early_init` because this call happens
before `console_init()`. `console_init()` prints the SMM header and we
want to append the verstage contents before printing the header to avoid
confusion.
BUG=b:221231786
TEST=Perform S0i3 cycles and verify PSP verstage logs now show up when
doing `cbmem -c`.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I64d33ccdee9863270cfbcaef5d7c614349bd895c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62402
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Log the platform boot mode reported by PSP verstage to PSP stage 1
bootloader. This helps to improve the debuggability.
BUG=b:193050286
TEST=Build and Boot to OS in Nipperkin. Ensure that the platform boot
mode is logged in the verstage logs.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I752ee56f2af48215a770d799432d02f0609757cd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62668
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Rename SPIROM_BASE_ADDRESS_REGISTER to SPI_BASE_ADDRESS_REGISTER to
clarify that this isn't the address the SPI flash gets mapped, but the
address of the SPI controller MMIO region. This also aligns the register
name with the PPR.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ifd9f98bd01b1c7197b80d642a45657c97f708bcd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62578
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
This patch aims to make timestamps more consistent in naming,
to follow one pattern. Until now there were many naming patterns:
- TS_START_*/TS_END_*
- TS_BEFORE_*/TS_AFTER_*
- TS_*_START/TS_*_END
This change also aims to indicate, that these timestamps can be used
to create time-ranges, e.g. from TS_BOOTBLOCK_START to TS_BOOTBLOCK_END.
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: I533e32392224d9b67c37e6a67987b09bf1cf51c6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62019
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
