Currently, the address size field of AT24 NVM is incorrect, and
Linux v5.4 kernel logs the message below:
at24 i2c-PRP0001:02: Bad "address-width" property: 13
The valid size of the AT24 NVM is 16 bits so modify the value from
0x0D to 0x10.
BUG=b:177655681
BRANCH=none
TEST=Boot volteer and check the kernel log and see "Bad address-width"
error message is not shown.
Signed-off-by: Daniel Kang <daniel.h.kang@intel.com>
Change-Id: Ice6c3eac1e023b981217e1d7dc06587fc46b1a02
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49633
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Bingbu Cao <bingbu.cao@linux.intel.com>
TEST=Majolica still gets to SeaBIOS. Like before this patch the PSP
still has the recovery flag set in its return value, but we likely still
have some problem in the amdfw part or miss some PSP initialization in
FSP.
Change-Id: I9f343452ef2ea6b01f9b2fd0cf6371218d046046
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50537
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
The RTC functionality will be used by elog.
Change-Id: I3a8d0a353620f64207d5ba8e17c145090f0c7506
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50543
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
The same functionality will eventually be needed on Cezanne.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib49124c2c774ad3352ea2f7d8d827388029be041
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50401
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
This reverts commit 3ac3c4ebac ("abuild: Allow disabling mainboards").
This mechanism helped getting Chrome OS' coreboot divergence sorted
out in the 2015/2016 timeframe but hasn't been used by anybody since
then. Let's not encourage people to push non-working builds without
good reason and discussion (the result of which could be that we
re-introduce this mechanism).
Change-Id: I8e2f2e1a5d4617baa49cbcb1a640a1ea270007ef
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50518
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Issue fixed in commit d152837 so don't allow use of _HID and _ADR at same time.
Change-Id: I52beba66230a3542a7039f496b51be0aa4bdcce4
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50384
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Was copy-pasted from another board and is completely useless.
Change-Id: Iedb03284b4509597cff5d39dda4f98669f2e814b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50502
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Desktop boards do not have any backlight control.
Change-Id: Ie9f5f4d7e6ae09b3d664d53e4c03157fd4ed088e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50501
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The southbridge ASL already includes this file.
Change-Id: I492d4c860a50ac98acbcb3a51fa4d47c94baade3
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50500
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The southbridge common SPI support already does this.
Tested on Asrock B85M Pro4, internal flashing and MRC cache still work.
Change-Id: I7ce0ca584cd3d42a10cdb74f45742f1eadc01bfa
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50479
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Not all TCO status bits have a corresponding enable bit. Masking out the
status register with the enable register causes these events to be lost.
Tested on Asrock B85M Pro4, BIOSWR_STS events are now detected.
Change-Id: I49abb5a4a99e943e57e0aaa6f06ff63bdf957cd3
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50478
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Lynxpoint PCH-H does not have SerialIO, so do not generate its SSDT.
Change-Id: Ie816ebd470df93a45826498bf21be59ff0a813bf
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50477
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
IASL complains that creation of named objects within a method is highly
inefficient. Avoid this by moving these named objects out of the method.
Change-Id: Iabfb20dcb3f655658844d99ab7a3b479684d9d19
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50475
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Platform code will overwrite these values anyway, so do not program them
in mainboards.
Change-Id: I7571d336a1402c6cfae5835a95dc706a28106271
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49751
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Datasheet is not publicly available. Derive which registers to dump from
IT8625E, since there are mainboards that can use either chip depending
on BOM configuration. Default values are taken from an HP 280 G2 running
a coreboot build that does not configure the Super I/O.
Change-Id: Icc8c56e9cd19e940e85176ac51b8ef978275eb71
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50457
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
As per HID over I2C Protocol Specification[1] Version 1.00 Section 7.4,
the interrupt line used by the device is required to be level triggered.
Hence, this change updates the configuration of the HID over I2C devices
to be level triggered.
References:
[1] http://download.microsoft.com/download/7/d/d/7dd44bb7-2a7a-4505-ac1c-7227d3d96d5b/hid-over-i2c-protocol-spec-v1-0.docx
BUG=b:172846122
TEST=./util/abuild/abuild
Change-Id: Ifdc3f061d919c8db9001c7a4cc26eb21117958d7
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50453
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Furquan Shaikh <furquan@google.com>
As per HID over I2C Protocol Specification[1] Version 1.00 Section 7.4,
the interrupt line used by the device is required to be level triggered.
Hence, this change updates the configuration of the HID over I2C devices
to be level triggered.
References:
[1] http://download.microsoft.com/download/7/d/d/7dd44bb7-2a7a-4505-ac1c-7227d3d96d5b/hid-over-i2c-protocol-spec-v1-0.docx
BUG=b:172846122
TEST=./util/abuild/abuild
Change-Id: Ice096777077bd2e9cfbaf744371fc372c0c05606
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50452
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Since SMM is in TSEG on the platforms which is the default, drop the
SMM_TSEG condition for the default of SMM_TSEG_SIZE.
Change-Id: I7bd965c0794efa12ea4886a55522cc5193a1d3ac
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50498
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This adds the apcb binary for Bilby.
Change-Id: I1487369bc72734e875c5a701f27ed2d6af41cd01
Signed-off-by: Ritul Guru <ritul.bits@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50496
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Sometimes boards enable it by default, making the Kconfig option
impossible to disable without messing with the Kconfig files. This
shouldn't happen, so report on such occurrences early.
TEST=Tried building GOOGLE_KOHAKU through abuild with -x, without
-x and both cases after having added a "select CHROMEOS" for testing
and it failed in the "without -x with select" scenario while properly
configuring and passing all other builds.
Change-Id: Ieb6bcbf3e9ca8cd4ced85c7c9ffaa39505f5a9b7
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50494
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The corresponding bit is marked as reserved in the PPR. Also there's no
BKDG for Picasso any more; the BKDG was mostly replaced by the PPR. Also
fix the style of the comment.
Change-Id: Iffdbb9e951cb140e4352ab0f198f72a71ba798dc
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50495
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Was copy-pasted from bd82x6x and no mainboard actually needs it.
The few globals moved outside the GNVS will be removed, relocated or
replaced with acpigen later.
Change-Id: I590a355f1bd1e54365b2e329cfdc62384446a15c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49280
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Was copy-pasted from i82801ix and no mainboard actually needs it.
Change-Id: I400424540b52dc5d43aba15720b18ad57ea2ebda
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49279
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Variable PICM was not inside GNVS region and can use a static
initialisation value.
For most AMD platforms PICM default changes from 1 to 0.
Fix comments about PICM==0 used to indicate use of i8259 PIC for
interrupt delivery.
Change-Id: I525ef8353514ec32941c4d0c37cab38aa320cb20
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49905
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The value should be set by OSPM using some combination of
_OSI() queris in the \_SB._INI() method.
To maintain previous behaviour with this commit, boards where
GNVS osys initialisation was removed now do the same in ASL.
Change-Id: Id4957b12a72fbf7fa988e7ff039e47abcc072e1c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49353
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Initialize variable to 1 to indicate AC power supply.
If platform has EC it will set this correctly based on
whether plugged on the charger or not.
Change-Id: I3f834cf7563b9e512fcab34cdb7a27a9f0fd31c0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49352
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change enables vboot support. To use it add CHROMEOS=y to your
config.
TEST=Boot majolica and see verstage run, and then see depthcharge load.
coreboot-4.13-1730-g881092709a5e Fri Feb 5 23:50:28 UTC 2021 verstage starting (log level: 8)...
Phase 1
FMAP: area GBB found @ 805000 (458752 bytes)
VB2:vb2_check_recovery() Recovery reason from previous boot: 0x0 / 0x0
Phase 2
Phase 3
FMAP: area GBB found @ 805000 (458752 bytes)
FMAP: area VBLOCK_A found @ 30000 (8192 bytes)
FMAP: area VBLOCK_A found @ 30000 (8192 bytes)
VB2:vb2_verify_keyblock() Checking keyblock signature...
VB2:vb2_verify_digest() HW RSA forbidden, using SW
VB2:vb2_rsa_verify_digest() HW modexp forbidden, using SW
FMAP: area VBLOCK_A found @ 30000 (8192 bytes)
FMAP: area VBLOCK_A found @ 30000 (8192 bytes)
VB2:vb2_verify_fw_preamble() Verifying preamble.
VB2:vb2_verify_digest() HW RSA forbidden, using SW
VB2:vb2_rsa_verify_digest() HW modexp forbidden, using SW
Phase 4
FMAP: area FW_MAIN_A found @ 32000 (3137280 bytes)
VB2:vb2api_init_hash() HW crypto forbidden by TPM flag, using SW
VB2:vb2_verify_digest() HW RSA forbidden, using SW
VB2:vb2_rsa_verify_digest() HW modexp forbidden, using SW
Saving secdata firmware
Saving secdata kernel
Saving nvdata
Slot A is selected
FMAP: area FW_MAIN_A found @ 32000 (3137280 bytes)
CBFS: mcache @0x02017000 built for 9 files, used 0x1ec of 0x800 bytes
CBFS: Found 'fallback/romstage' @0x0 size 0x753c in mcache @0x02017000
BS: verstage times (exec / console): total (unknown) / 116 ms
coreboot-4.13-1730-g881092709a5e Fri Feb 5 23:50:28 UTC 2021 romstage starting (log level: 8)...
Family_Model: 00a50f00
FMAP: area FW_MAIN_A found @ 32000 (3137280 bytes)
CBFS: Found 'fspm.bin' @0x15440 size 0x2257d in mcache @0x02017138
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I43f0c6e33649332057f41f8813a86571b06032f1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50343
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Only the ACPI enable/disable functionality is implemented and sleep is
also not implemented yet. This will be added in future patches.
Change-Id: I7701944023ce2e86586679c32c4138d4488768a1
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50488
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This doesn't select HAVE_ACPI_TABLES, so no ACPI tables will be
generated for now. There's also no globalnvs.asl that corresponds to
nvs.h yet. The added nvs.h has some currently unused fields, but still
having them in the struct aligns it with Picasso and also might reduce
the noise in future ACPI patches a bit. When most of the ACPI code for
Cezanne has landed, we need to do a cleanup though.
Change-Id: I3d658d284fa67e4da43a89d74686445fd5e93b1f
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50487
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
signed int should only be used when we need negative values and in those
cases the value shouldn't became negative.
Change-Id: Iefac021260ff363c76bf5cd3fe3619ea1dbabdba
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50486
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The MCA MSRs aren't getting cleared and no microcode update gets applied
for now. Both will be added later.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I38ce5d11787ffefdd0183c5540ae2683158cbee8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50482
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Daniel Kang