Commit Graph

30055 Commits

Author SHA1 Message Date
Kyösti Mälkki 157b189f6b cpu/intel: Enter romstage without BIST
When entry to romstage is via cpu/intel/car/romstage.c
BIST has not been passed down the path for sometime.

Change-Id: I345975c53014902269cee21fc393331d33a84dce
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34908
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-08-18 19:03:22 +00:00
Kyösti Mälkki 146c098233 mainboards: Remove floating __PRE_RAM__ comments
Change-Id: I110e54175a81b6a651213e0f18ddc1e3e71160cf
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34920
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-08-18 09:54:08 +00:00
Kyösti Mälkki 184a1176f3 amdfam10-15: Rename DCACHE_BSP_STACK_SIZE
The original name DCACHE_BSP_STACK_SIZE will be exclusively
used to define the fixed size of BSP stack when it is located
near the beginning of CAR region. This implementation has the
stack located at the very end of CAR region.

Remove other fam10-15 exclusive configs from global space.

Change-Id: I8b92891be2ed62944a9eddde39ed20a12f4875c0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34880
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-08-18 08:09:21 +00:00
Huayang Duan 126d4198a9 mediatek/mt8183: Add SAMSUNG 4GB LPDDR4X discrete DDR support
BUG=b:80501386
BRANCH=none
TEST=Boots correctly and stress test passes on Kukui.

Change-Id: I27164f0909edb9d9398835e292fb845f0e342391
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34532
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Huayang Duan <huayang.duan@mediatek.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-16 19:52:44 +00:00
Christian Walter f4aa501eca soc/intel/cannonlake: Add 4E/4F to early io init
This is needed for the AST2500 to work, because it uses 4E/4F.

Change-Id: Ie47474e9bf1edfe98555a148469c41283e9a4ea6
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34862
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2019-08-16 10:42:27 +00:00
Christian Walter ccac15a4dd soc/intel/cannonlake: Add more PCI Ids for Coffeelake
Change-Id: I92e2adb32d19ff49bdef353e1f191c4960ce0d18
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34861
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
2019-08-16 10:42:05 +00:00
Philip Chen 4055cd8b03 soc/intel/common/dptf: Add support for mode-aware DPTF
This change ports some previous work for Skylake:

cb58683ef5 soc/intel/skylake: Add support for mode-aware DPTF

...to common DPTF code so that we can support mode-aware DPTF for other
Intel platforms.

BUG=b:138702459
BRANCH=none
TEST=Manually test on hatch:
(1)Add DPTF_TSR0_TABLET_PASSIVE and DPTF_TSR1_TABLET_PASSIVE
to hatch baseboard dptf.asl
(2)Flash custom EC FW code which updates DPTF profile number when
entering/exiting tablet mode
(3)On DUT, see /sys/class/thermal/thermal_zone2/trip_point_{1,2}_temp
updated when device mode is switched (tablet/clamshell)

Signed-off-by: Philip Chen <philipchen@google.com>
Change-Id: I5e7b97d23b8567c96a7d60f7a434e98dd9c69544
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34785
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-16 04:27:55 +00:00
Peichao Wang aa3c0a5fad mb/google/hatch: Create Akemi variant
This is based on the hatch variant

BUG=b:138879565
TEST=FW_NAME="akemi" emerge-hatch coreboot depthcharge intel-cmlfsp
chromeos-bootimage look for image-akemi.*.bin generated under the
/build/hatch/firmware/

Change-Id: I1a868839e2c598f8052d37c99713bc58b21e887c
Signed-off-by: Peichao Wang <peichao.wang@bitland.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33824
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-08-16 04:27:40 +00:00
Kyösti Mälkki 8699724a07 amd/picasso: Unify SMM relocation
Change-Id: I62104894b5a956523f509d88d49e45a0bd1c587d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34749
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-16 00:37:31 +00:00
Kyösti Mälkki 0d4d09cad1 amd/stoneyridge: Unify SMM relocation
Change-Id: I02ad07e049cb74ccb52ba3d41eb16c58a2cfb38b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34748
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-16 00:37:00 +00:00
Kyösti Mälkki 1dbf31014f amd/stoneyridge: Rename ramtop.c to memmap.c
Use a name consistent with the more recent soc/intel.

Change-Id: I4d67a7c3107758c81a67e1668875767beccfcdb0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34879
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2019-08-16 00:36:37 +00:00
Kyösti Mälkki 047a9e4ddc amd/picasso: Rename ramtop.c to memmap.c
Use a name consistent with the more recent soc/intel.

Change-Id: I491e609bed00dc79c628b321c74ad7f4cc31b5fe
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34878
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2019-08-16 00:36:26 +00:00
Kyösti Mälkki 66cabe7ba2 soc/amd/common: Refactor S3 helpers
Make the prototypes match what drivers/amd/agesa would
rather see, in preparation to use the same code with
open-source AGESA.

Change-Id: I1506ee2f7ecf3cb6ec4cce37a030c05f78ec6d59
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31490
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2019-08-16 00:35:49 +00:00
David Wu 434a975b97 mb/google/hatch/var/kindred: Configure GPIOs for eMMC SKUs
Configure GPIOs for eMMC SKUs

BUG=b:132918661
TEST=Verify SSD is disabled when SKU ID = 2/4/21/22

Change-Id: I9f678a40555dbc841487811cc1f680b211a51a89
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34795
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2019-08-15 20:08:40 +00:00
David Wu aa9aff7b81 mb/google/hatch/var/kindred: Disable SATA controller for eMMC SKUs
Disable SATA controller and SATA port 1 for eMMC SKUs

BUG=b:132918661
TEST=Verify SSD is disabled when SKU ID = 2/4/21/22

Change-Id: I6d95ff94b079a564f74c19739370101899843f00
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34789
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-15 20:08:20 +00:00
David Wu 460a1758aa mb/google/hatch/var/kindred: Configure GPIOs for SSD SKUs
Configure GPIOs for SSD SKUs

BUG=b:132918661
TEST=Verify eMMC is disabled when SKU ID = 1/3/23/24

Change-Id: Ief48a2fd2fa078aa5d89aec01f99af75510334b2
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34851
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-15 20:07:47 +00:00
David Wu 8444e3c47a mb/google/hatch/var/kindred: Disable eMMC for new SKU ID 23 and 24
1. Disable eMMC controller for new SKU ID 23 and 24
2. Disable HS400 mode

BUG=b:132918661
TEST=Verify eMMC is disabled when SKU ID = 1/3/23/24

Change-Id: I0d893f0f7339e7b1a1e6b56d1598c0a361c8d604
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34788
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2019-08-15 20:07:36 +00:00
Kyösti Mälkki 2c430c8c5b intel/smm: Define struct ied_header just once
Change-Id: I6fc083aa30d05c11c1b6db7b3facacf5ae857c92
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34855
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-08-15 06:58:45 +00:00
Kyösti Mälkki faf20d30a6 soc/intel: Rename some SMM support functions
Rename southbridge_smm_X to smm_southbridge_X.
Rename most southcluster_smm_X to smm_southbridge_X.

Change-Id: I4f6f9207ba32cf51d75b9ca9230e38310a33a311
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34856
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-15 06:55:59 +00:00
Kyösti Mälkki f091f4daf7 intel/smm/gen1: Rename header file
Change-Id: I258fccc5e1db0bedb641c8af8cb9727954d4d7c1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34869
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-08-15 06:53:52 +00:00
Patrick Rudolph 5ec97cea67 soc/*: mp_run_on_all_cpus: Remove configurable timeout
Some timeouts given were too small when serial console is enabled due to
its spinlock making code runtime worse with every AP present.

In addition we usually don't know how long specific code runs and how
long ago it was sent to the APs.

Remove the timeout argument from mp_run_on_all_cpus and instead wait up
to 1 second, to prevent possible crashing of secondary APs still
processing the old job.

Tested on Supermicro X11SSH-TF.

Change-Id: I456be647b159f7a2ea7d94986a24424e56dcc8c4
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34587
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2019-08-15 06:45:34 +00:00
Johnny Lin 1bc6bf1152 drivers/ipmi: make IPMI KCS status and command register spacing configurable
The default is 1 (byte) spacing.

Tested on Mono Lake with 4 (32-bit) spacing

Change-Id: I47412c32e6db8f58b4fde8150adcbce349ca18a7
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34835
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-08-15 06:45:08 +00:00
Kyösti Mälkki 621142aa60 intel/ice,sky,cannon: Drop unused EMRR and UNCORE_EMRR code
There was no code present to call wrmsr with the data we
prepared in the structs. The MSRS are already set up by FSP,
just reference with the more recent names of PRMRR and UNCORE_PRMRR.

Change-Id: Ib49e7af52e1170a1304975ff0ae63f99e106dffe
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34824
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-08-15 05:57:43 +00:00
Kyösti Mälkki 07b7d8c630 soc/intel: Drop spurious includes
Change-Id: I2fff107e38abdd34f2d80d4d258be4c429d371e7
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34868
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-08-15 05:57:07 +00:00
Kyösti Mälkki 7cdb047ce7 cpu/x86/smm: Promote smm_memory_map()
Change-Id: I909e9b5fead317928d3513a677cfab25e3c42f64
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34792
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-15 05:46:59 +00:00
Kyösti Mälkki 544878b563 arch/x86: Add postcar_frame_common_mtrrs()
As most platforms will share the subset of enabling
both low RAM WB and high ROM WP MTRRs, provide them
with a single function.

Add possibility for the platform to skip these if
required.

Change-Id: Id1f8b7682035e654231f6133a42909a36e3e15a1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34809
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-15 05:32:44 +00:00
Kyösti Mälkki 5bc641afeb cpu/intel: Refactor platform_enter_postcar()
There are benefits in placing the postcar_frame structure
in .bss and returning control to romstage_main().

Change-Id: I0418a2abc74f749203c587b2763c5f8a5960e4f9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34808
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-08-15 05:31:29 +00:00
Kyösti Mälkki b3267e002e cpu/intel: Replace bsp_init_and_start_aps()
Change-Id: I7176efdd1000789a093a1b4e243b4b150e6bb06f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34864
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-15 04:59:12 +00:00
Kyösti Mälkki 826f35421e intel/denverton_ns: Drop unused save_gpio_route
Change-Id: I58131d77ba23024cd23e38584f8062d330d2564f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34867
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: David Guckian
2019-08-15 04:42:21 +00:00
Kyösti Mälkki 89d7fd8100 mainboard/google: Fix indirect includes
Change-Id: Ie79702efab519b16cff45ccad61b95e7d8c2fbac
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34854
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-15 04:41:35 +00:00
Kyösti Mälkki a347630641 intel/smm/gen1: Split alternative SMRR register function
The non-alternative one will have inlined version available
with the new header.

Change-Id: I208ac84fdf5d8041a1901cc2331769cd3a8d6bea
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34839
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-08-15 04:40:32 +00:00
Kyösti Mälkki 4913d8aed0 cpu/x86/smm: Define single smm_subregion()
At the moment we only have two splitting of TSEG,
one with and one without IED. They can all use
same implementation.

Make configuration problems of TSEG region assertion
failures.

Rename file from stage_cache.c to tseg_region.c to
reflect it's purpose.

Change-Id: I9daf0dec8fbaaa1f4e6004ea034869f43412d7d5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34776
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: David Guckian
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-15 04:39:17 +00:00
Hung-Te Lin b1af16a424 mb/google/kukui: Report panel manufacturer name
The src/lib/edid now supports reporting manufacturer name so we should
define that in MIPI panels and print out in initialization.

BUG=None
TEST=emerge-kukui coreboot; boots properly

Change-Id: If844da84ecca31307127b14c66bbe17c408699f3
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34853
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-08-15 03:04:26 +00:00
Hung-Te Lin 6673e8ec6a lib: edid: Move manufacturer name from private extra to public info
When debugging usually we want to print out a full identifier for panel,
that should be manufacturer and part number. Previously the edid only
contains ascii_string (which is usually the part number) but we should
export manufacturer name as well.

Change-Id: I0020fdd5b9f9331b25825876e0de4dc7e26b0464
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34852
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-08-15 03:04:08 +00:00
Hung-Te Lin e366ba14eb soc/mediatek: Change DSI init commands to take flexible length array
The fixed size of init command in lcm_init_table is wasting lots of
space and we should change to packed array since the command buffer
already provides length information.

With this change, BOE panel init commands have been reduced from 4848
bytes to 1309 bytes.

BUG=b:80501386,b:117254947
TEST=emerge-kukui coreboot chromeos-bootimage; Boots properly

Change-Id: I359dde8e6f2e1c0983f4677193bb47a7ae497ca6
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34778
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-15 03:03:49 +00:00
Hung-Te Lin 00e1ee9242 mb/google/kukui: Support eDP panels via PS8640
Some Kukui variants may have eDP panels connected via a PS8640 MIPI bridge
which we may retrieve EDID dynamically.

BUG=b🅱️137517228
TEST=emerge-jacuzzi coreboot chromeos-bootimage; boots and see display.

Change-Id: I85aac5255e6a3e6019299670486214ecffbf9801
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34516
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-15 00:54:12 +00:00
Peichao Wang 1d5fc281c8 mb/google/kukui: Add panel for Kodama
Declare the following panel for Kodama:
- BOE TV101WUM-N53

BUG=b:138156559
TEST=builds Kodama image and working properly

Change-Id: I129cb6bf084b76da3ad33b7a19e38e884442b1aa
Signed-off-by: Peichao Wang <peichao.wang@bitland.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34505
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-15 00:53:58 +00:00
Hung-Te Lin bca33b43f7 mb/google/kukui: Add panel for Kukui
Support Kukui rev 2 panel (via SSD2858).

BUG=b:129299873
BRANCH=none
TEST=Build as Kukui and boots on Rev 2 unit.

Change-Id: Icc16c4297eb3c6b6a4770a36661a2e3cab418048
Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33571
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-08-15 00:53:43 +00:00
Jitao Shi 3324e3f814 mb/google/kukui: Add panels for Krane
Declare the following panels for Krane:
- BOE TV101WUM-NL6
- AUO KD101N80-45NA

The edid info and init command are from:
https://crrev.com/c/1565758

BUG=b:129299873
BRANCH=none
TEST=Builds krane image and boots properly.

Change-Id: Id19c6c2b4c1c728c39aa26301adf7d6fb5046403
Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33413
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-08-15 00:53:21 +00:00
Hung-Te Lin 2c307a0bed mb/google/kukui: Initialize display
Many devices in Kukui family will be using MIPI panels, which needs
hard-coded EDID and initialization commands. And because each device may
have its own layout and ID, there should be very few devices sharing
same panel configuration. As a result, we want to put panel data (EDID
and init commands) into board-specific modules, provided by
`get_panel_description` function.

The panel numeric ID is identified by ADC 2, and is currently available
as higher 4 bits of sku_id(). After ID is retrieved, the
get_panel_description should return a reference to the EDID and table of
init commands. The default implementation is to simply return NULL, and
the data for real devices should be provided by panel_*.c in further commits.

BUG=b:80501386,b:117254947
BRANCH=none
TEST=boot correctly on Kukui

Change-Id: I19213aee1ac0f69f42e73be9e5ab72394f412a01
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32511
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-08-15 00:51:31 +00:00
Hung-Te Lin 32ddc0d9f7 soc/mediatek/mt8183: Add DSI driver
The MT8183 display serial interface (DSI) is based on MIPI
Alliance Specification, supporting high-speed serial data
transfer between host processor and peripheral devices such
as display modules.

DSI supports both video mode and command mode data transfer
defined in MIPI spec, and it also provides bidirectional
transmission with low-power mode to receive messages from
the peripheral.

Reference: MT8183 Application Processor Functional Spec,
 6.7 Display Serial Interface (DSI)

BUG=b:80501386,b:117254947
BRANCH=none
TEST=Boots correctly on Kukui

Change-Id: Ic413f524ca0b36f0b01f723a71fe9745e2710cd2
Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31591
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-08-15 00:51:05 +00:00
Hung-Te Lin 75e4314675 soc/mediatek: dsi: Support sending MIPI init commands
For systems with real MIPI panels (8173/oak was using PS8640 eDP
bridge), we have to send DCS commands to initialize panel.

BUG=b:80501386,b:117254947
TEST=make -j # board = oak and boots

Change-Id: Ie7c824873465ac82a95bcb0ed67b8b9866987008
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34773
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-15 00:19:40 +00:00
Hung-Te Lin 3b217d5c69 soc/mediatek: dsi: Refactor video timing calculation
The video timing should be based on PHY timing. Some values can be
ignored on 8173 because of fixed values in PHY but should be calculated
for newer platforms like 8183.

BUG=b:80501386,b:117254947
TEST=make -j # board = oak and boots

Change-Id: Id3ad2edc08787414a74188f5050460e98222caf4
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34772
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-08-15 00:09:06 +00:00
Hung-Te Lin ff0945e8ec soc/mediatek: dsi: Refactor PHY timing calculation
The PHY timing should be calculated by data rate (Mbps). However for
8173 some values were hard-coded so we want to introduce a new
mtk_phy_timing structure and a weak function mtk_dsi_override_phy_timing
that allows per-SOC customization to apply PHY timings.

BUG=b:80501386,b:117254947
TEST=make -j # board = oak and boots

Change-Id: I1176ca06dda026029ff431aca7f9e21479eed670
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34771
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-08-14 21:16:09 +00:00
Andrey Petrov 4a73bf8378 soc/intel/fsp_broadwell_de: Populate SMBIOS tables with memory information
Add code to read SPD data, parse it and save into SMBIOS table. This is
implemented for socketed DDR4 chips only. For soldered-down memory this
is not implemented and probably won't be ever needed.

TEST=tested on OCP Monolake mainboard, and found dmidecode -t memory to
work. The stack has also been tested on an out-of-tree board.

Signed-off-by: Andrey Petrov <anpetrov@fb.com>
Change-Id: I1162eb4484dab46f1ab9fe3426eecc4d9378e8e2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34681
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2019-08-14 03:35:52 +00:00
Andrey Petrov 3f85edbcc5 dram: Add basic DDR4 SPD parsing
Add ability to decode basic fields of DDR4 SPDs and produce SMBIOS table
17. XMP, schemas, extended field parising is totally not yet implemented.
Also, put CRC function used in DDR2, DDR3 and DDR4 ina  common file.

Signed-off-by: Andrey Petrov <anpetrov@fb.com>
Change-Id: If3befbc55cf37e1018baa432cb2f03743b929211
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34680
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2019-08-14 03:35:29 +00:00
Andrey Petrov bb9506121f soc/fsp_broadwell_de: Implement SMBus read/write over IMC
Add read/write functions to hook it up with existing SPD retrieval code.

Signed-off-by: Andrey Petrov <anpetrov@fb.com>
Change-Id: I9f5993dc795badf72751a4e6c9d974119a653e30
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34679
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-14 03:35:07 +00:00
Andrey Petrov f377fafd94 common/block/imc: Add Integrated Memory Controller (IMC) driver
IMC is found on certain Xeon processors. On such platforms SPDs are not
connected to SMBus on PCH but to dedicated IMC-owned pins. The purpose
of this driver is to expose access to the i2c/smbus controller associated
with IMC.

Datasheet used: Intel Xeon Processor D-1500 Product Family, Volume 2,
reference 332051-001

This driver is largely based on i2c-imc.c Linux driver.
https://lwn.net/Articles/685475/

TEST=single/double reads and single writes on Xeon-D1500.
Hardware: Open Compute Project Monolake platform.

Signed-off-by: Andrey Petrov <anpetrov@fb.com>
Change-Id: Idbcda1c2273b9a5721fcd9470b4de182192779e7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34678
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-14 03:34:42 +00:00
Andrey Petrov c0193c9237 soc/intel/fsp_broadwell_de: Enable early integrated UART
In order to use internal UART it needs to 'enabled'. This is normally done
by FSP. However sometimes internal UART is needed before FSP is invoked.

TEST=check if printk() show up in early romstage. Tested on OCP Monolake.
Tested on out-of-tree mainboard to see if UART on LPC still works.

Signed-off-by: Andrey Petrov <anpetrov@fb.com>
Change-Id: I88a7b1a38abf9a09137f6dd75a5a9dee104daaca
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34683
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-13 22:35:41 +00:00
Furquan Shaikh 8ce36ac548 drivers/i2c/generic: Add "compatible" property to _DSD
This change adds support for allowing devices to provide a
"compatible" property string that can be used when _HID is set to
PRP00001. This is used to allow Linux kernel drivers to match the
device to appropriate driver based on the OF-style compatible
string.

Reference:
https://www.kernel.org/doc/Documentation/acpi/enumeration.txt

BUG=b:129162037
TEST=Verified that atmel touchscreen gets enumerated correctly on
kohaku using PRP0001 and compatible string.

Change-Id: I8a306854c67ab2f056ea8774df46599ef0c55761
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34813
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2019-08-13 19:47:54 +00:00