Commit Graph

37087 Commits

Author SHA1 Message Date
Subrata Banik 8c0dda2183 soc/intel/cannonlake: Align gpio_op.asl with TGL
Also drop gpio_common.h in favor of intelblocks/gpio_defs.h macros.

TEST=Able to build and boot CNL and CML platform.
1) Dump and disassemble DSDT, verify unified methods like GRXS,
GTXS etc. are there.
2) Verify no ACPI error seen while running 'dmesg' from console.
3) abuild --timeless to ensure there are no other functional changes.

Change-Id: I78d712eeba56b9c098dc6a6f11e4e51cb2529b10
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45654
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-27 03:01:31 +00:00
Subrata Banik 1bfb74c14c soc/intel/{jsl,tgl}: Fix GRXS function to get GPIO number proper
This patch ensures that GRXS perform PAD_CFG0_RX_STATE mask first
and then right shift PAD_CFG0_RX_STATE_BIT to get correct GPIO number.

Change-Id: I96611936f70f79e9dc5ee9414ec68cef00d0d13a
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45738
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-27 03:01:04 +00:00
Zoltan Baldaszti be58923fed payloads/external: add support for BOOTBOOT payload
BOOTBOOT is a multi-platform, architecture agnostic boot protocol.
The protocol describes how to boot an ELF64 or PE32+ executable inside
an initial ram disk image into clean 64 bit mode. This version uses
libpayload to do that. Depending on the lib's configuration, initrd
can be in ROM as a cbfs file or a Flashmap partition; on disk a GPT
partition or a file on a FAT formatted ESP partition.
For more information see https://gitlab.com/bztsrc/bootboot

Change-Id: I8692cde0730338026a7760a293c1e37f66004bc0
Signed-off-by: Zoltan Baldaszti <bztemail@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45482
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-09-26 23:08:07 +00:00
Kyösti Mälkki 871c8734b9 soc/intel/apollolake: Drop select SMP
The SOC has MAX_CPUS>1 so this is redundant.

Change-Id: Icb4c7551031f4e32e01198261ee9ae9b95f18142
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43818
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-26 23:07:09 +00:00
Kyösti Mälkki 57550a28b8 cpu/qemu-x86: Drop select SMP
With MAX_CPUS==1, this has the effect of removing spinlock
implementation. But since is_smp_boot() evaluates false and
SMM uses separate smi_semaphore, there is no concurrency to
protect against with a spinlock.

Change-Id: I7c2ac221af78055879e7359bd03907f2416a9919
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43865
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-26 23:06:50 +00:00
Kyösti Mälkki e92abdf207 mb/emulation/qemu-i440fx: Remove TRACE=y from test build
Looks like the option is generally not compatible with
garbage collections. Nothing is inlined, is_smp_boot()
no longer evaluates to constant false and thus the symbols
from secondary.S would need to be present for the build
to pass after we set SMP=n.

Change-Id: I1b76dc34b5f39d8988368f71a0a2f43d1bc4177e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43817
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-26 23:06:43 +00:00
Paul Fagerburg 96fd529a92 lib/Makefile.inc: fix name of config string
The config string is HAVE_SPD_IN_CBFS, without the "BIN".

Signed-off-by: Paul Fagerburg <pfagerburg@google.com>
Change-Id: I728f64b2dd93b0e3947983b9b3701e185feff571
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45739
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-09-26 19:33:49 +00:00
Patrick Rudolph 819c206742 ironlake: Fix compilation on x86_64
Use correct datasize to compile on x86_64.
Tested on Lenovo T410 with additional x86_64 patches.

Change-Id: I213b2b1c5de174b5c14b67d1b437d19c656d13fd
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37371
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-26 17:31:08 +00:00
Angel Pons a32df26ec0 arch/x86: Introduce `ARCH_ALL_STAGES_X86_32`
Nearly every x86 platform uses the same arch for all stages. The only
exception is Picasso. So, factor out redundant symbols from the rest.

Alder Lake is not yet complete, so it has been skipped for now.

Change-Id: I7cff9efbc44546807d9af089292c69fb0acc7bad
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45731
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-09-26 11:42:28 +00:00
Angel Pons 2db7790795 arch/x86: Introduce `ARCH_ALL_STAGES_X86_64`
Though only one platform uses it, this will save some redundancy.

Change-Id: Ic151efe5dd9b7c89f779ac3e10c3a045f07221d3
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45730
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-09-26 11:42:22 +00:00
Raul E Rangel 2c6fcab228 vc/amd/fsp/picasso: Update to UPD 1.0.1.3
This adds eMMC preset settings.

It also fixes some formatting and a comment.

BUG=b:159823235
TEST=Build test

Cq-Depend: chrome-internal:3251807
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ic5caff594157e03d792b999ca60274cf53c708e2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45096
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-25 23:22:50 +00:00
Jason Glenesk bc5214342f soc/amd/picasso: Generate ACPI pstate and cstate objects in cb
Add code to generate p-state and c-state SSDT objects to coreboot.
Publish objects generated in native coreboot, rather than the ones
created by FSP binary.

BUG=b:155307433
TEST=Boot morphius to shell and extract and compare objects created in
coreboot with tables generated by FSP. Confirm they are equivalent.
BRANCH=Zork

Change-Id: I5f4db3c0c2048ea1d6c6ce55f5e252cb15598514
Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45340
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-09-25 22:49:56 +00:00
Abe Levkoy ebd234e059 mb/google/volteer: Wake on AC connect and disconnect
Add AC connect and disconnect to S0ix lazy wake sources.

BUG=b:161466940
BRANCH=master
TEST=Connect and disconnect charger in S0ix; observe wake

Change-Id: I30046a379ff75c33b991e355cc8d142241ee8b2e
Signed-off-by: Abe Levkoy <alevkoy@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45669
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-25 22:42:42 +00:00
Angel Pons 6fd9adbecb nb/intel/x4x/x4x.h: Clean up cosmetics
Align groups of definitions, reflow long lines and adjust whitespace.

Tested with BUILD_TIMELESS=1, Asus P5QL PRO remains identical.

Change-Id: I75723fe087ef16f74ca93f6faa4d3468d7958a5c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45420
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-09-25 19:43:19 +00:00
Angel Pons 2a8ceefb27 nb/intel/x4x/iomap.h: Rename to memmap.h
It primarily contains definitions for MMIO windows. Also, remove
includes from files not directly using the definitions it contains.

Tested with BUILD_TIMELESS=1, Asus P5QL PRO remains identical.

Change-Id: Id28080d9b2924463dd3720492d5e717d65fa0071
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45419
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-25 19:43:07 +00:00
Angel Pons 8f0b3e546a nb/intel/pineview: Place raminit definitions in raminit.h
There's no need to have implementation details in a public header.

Tested with BUILD_TIMELESS=1, Foxconn D41S remains identical.

Change-Id: I0bfd6ee72347249302ee073081f670b315aa40e4
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45388
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-09-25 19:42:43 +00:00
Angel Pons ac4e4b423f nb/intel/gm45/gm45.h: Clean up cosmetics
Align groups of definitions, reflow long lines and adjust whitespace.

Tested with BUILD_TIMELESS=1, Roda RK9 remains identical.

Change-Id: I2969274c6b50f56994e45ada5d016504addfc13e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45434
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2020-09-25 19:41:35 +00:00
Angel Pons 9c2d15ff7f nb/intel/gm45: Drop unused `DEFAULT_HECIBAR` macro
Change-Id: I9e074689cd5a11d58b788b789654f3a3beb83a65
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45433
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-09-25 19:40:59 +00:00
Angel Pons 3378de12f6 nb/intel/gm45: Drop casts from DEFAULT_{MCHBAR,DMIBAR}
There's no need to wrap these macros with casts. Removing them allows
dropping `uintptr_t` casts in other files. Changes the binary, though.

Change-Id: I1553cbeee45972d6deba8cb9969c69fceeb19574
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45432
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-25 19:40:44 +00:00
Ronak Kanabar e60155ff13 volteer: Create boldar variant
Create the boldar variant of the volteer reference board by copying
the template files to a new directory named for the variant.

(Auto-Generated by create_coreboot_variant.sh version 4.2.0).

Add "memory/Makefile.inc" generated by gen_part_id.go

BUG=b:162202257
BRANCH=None
TEST=util/abuild/abuild -p none -t google/volteer -x -a
make sure the build includes GOOGLE_BOLDAR

Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Change-Id: I92b4b917448d8e5e9176cb983adf7b209956d2c2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45648
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2020-09-25 16:45:07 +00:00
Kane Chen fb2f356d89 mb/google/zork: Modify I2C3 CLK for Woomax to meet I2C specification
Modify I2C3 setting to follow I2C specification(lower than 400kHz).
Original setting:
.rise_time_ns = 125
.fall_time_ns = 37

Change to:
.rise_time_ns = 110
.fall_time_ns = 34

BUG=b:169207742
BRANCH=None
TEST=emerge-zork coreboot chromeos-bootimage

Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com>
Change-Id: I0f0b791c3e701ebf6b336a8cb259eeb74c46af5a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45644
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-09-25 15:09:42 +00:00
Kane Chen 4dcccc8365 mb/google/zork: Modify USB 2.0 PHY parameters for Woomax
Modify USB 2.0 PHY parameters for improve usb eye diagram.
1. USB 2.0 TypeC port0:
.com_pds_tune = 0x03,
.sq_rx_tune = 0x3,
.tx_fsls_tune = 0x3,
.tx_pre_emp_amp_tune = 0x03,
.tx_pre_emp_pulse_tune = 0x0,
.tx_rise_tune = 0x1,
.rx_vref_tune = 0xf,
.tx_hsxv_tune = 0x3,
.tx_res_tune = 0x01,

2. USB 2.0 TypeC port3:
.com_pds_tune = 0x03,
.sq_rx_tune = 0x3,
.tx_fsls_tune = 0x3,
.tx_pre_emp_amp_tune = 0x03,
.tx_pre_emp_pulse_tune = 0x0,
.tx_rise_tune = 0x1,
.rx_vref_tune = 0xf,
.tx_hsxv_tune = 0x3,
.tx_res_tune = 0x01,

BUG=b:169207729
BRANCH=zork
TEST=emerge-zork coreboot chromeos-bootimage

Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com>
Change-Id: I764238485a1a81eb0d4740ac58c80a43f965f550
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45641
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-25 15:02:07 +00:00
Subrata Banik 1861ca4bb8 soc/intel/tigerlake: Remove extra '_' from GPIO PIN name
Fix typo GPD__SLP_SUSB -> GPD_SLP_SUSB

Change-Id: I2beddb5665dc2f6a28b9c02e240b12da137c1b17
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45685
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-25 14:35:54 +00:00
Elyes HAOUAS 3f56b87c51 Documentation/getting_started/kconfig.md: Add a note about Kconfig defaults
When the declaration is done after the default, menuconfig will see that
symbol defined at the first place where kconfig tool will find it.
For example, if we run menuconfig and search for 'MAINBOARD_VENDOR', we
will see it defined at ""src/mainboard/51nb/Kconfig" which is odd.

Change-Id: I215a1817e60e6deb6931679f139d110ba762d3c8
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45127
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-09-25 08:41:45 +00:00
Subrata Banik 3bcb6c7319 soc/intel: Use ASL 2.0 syntax for GPIO ASL helper function
Migrate ASL helper function like GRXS, GTXS, STXS, CTXS to ASL 2.0
syntax across CNL, ICL, JSL, SKL.

TEST=Able to build and boot Hatch, EVE and ICLRVP platform.
Dump and disassemble DSDT to ensure GRXS,GTXS etc functions
implementation remain unchanged prior and after this CL.

Change-Id: I0ebf1f86031eae25337d2dbeabb8893d9f19a14b
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45677
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-25 03:03:14 +00:00
Subrata Banik 8d4176109d soc/intel/{jsl,tgl}: Refactor gpio_op.asl
Also align GPMO ASL function with TGL.

Change-Id: Ia40af2cba9867838a1f99141481a5e78cffa0111
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45688
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-09-25 03:02:49 +00:00
Huayang Duan 63ee16075e soc/mediatek/mt8183: Enable CA perbit mechanism
LPDDR4x has 6 CA PINs, but for some 8GB LPDDR4X DDR, the left margin
of some CA PIN window is too small than others. Need to enable the CA
perbit mechanism to avoid those risks.

BUG=none
BRANCH=kukui
TEST=Boots correctly on Kukui

Change-Id: I58e29d0c91a469112b0b1292da80bcb802322d47
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41965
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-25 01:33:11 +00:00
Michael Niewöhner 92c1546c01 mb/clevo/cml-u: remove the duplicate WiFi PCIe device in devicetree
Change-Id: Ibb46bbf0c889bb8b3fd1a4c0331dc719baffc7a2
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45678
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-25 00:29:53 +00:00
Felix Singer 44df56edce mb/clevo: Rename l140cu to cml-u
In addition to CB:45664, rename clevo/l140cu to clevo/cml-u being able
to add more variants under a generic mainboard later.

Change-Id: I9c16e24830ebb80752df302aa2e63d9df8edad95
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45665
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-25 00:28:37 +00:00
Felix Singer 1f4b3cdeb0 mb/clevo/l140cu: Make usage of variant mechanism
Clevo mainboards can be grouped by their common platform. Therefore,
restructure the mainboard directory as a first step, so that the variant
mechanism is used.

This moves most of the code into the variant dir, since the L140CU is
the only variant at the moment.

Change-Id: I9ad1c06f9db854cac1dd420c53dc0c9f010ed716
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45664
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-24 23:35:13 +00:00
Angel Pons a25eaffb69 soc/intel/alderlake: Select ACPI_INTEL_HARDWARE_SLEEP_VALUES
This resolves a Kconfig warning regarding unmet dependencies.

Change-Id: I9e70a4d333afefcb27c097aa9ce84e5effc0d7c3
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45655
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-09-24 18:59:39 +00:00
Michael Niewöhner 733c462c13 soc/intel/cnl: drop lpit.asl in favor of common version
Drop lpit.asl from CNL and switch to the common one in the three boards
currently using it.

The only difference between the two is the usage on macros in common
code instead of plain integer values.

Change-Id: Iefbd18db7f4c560dce16c4119fde4f4cfbeafb84
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45549
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-24 18:55:19 +00:00
John Zhao c8e309779f mb/google/volteer: Enable CnviBtAudioOffload
This change enables CnviBtAudioOffload. FSP is invoked to configure
BT over USB and BT I2S pins for cAVS connection.

BUG=b:169045123
TEST=Verifed CnviBtCore and CnviBtAudioOffload settings and FSP
configuration. Booted up to kernel on Volteer.

Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I1780da0824d145a79743d5cffdea4821236d4f74
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45586
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Naveen M <naveen.m@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-09-24 18:48:56 +00:00
John Zhao c16fc8a49c soc/intel/tigerlake: Add support for CnviBtCore and CnviBtAudioOffload
This change adds configuration support for both of CnviBtCore and
CnviBtAudioOffload.

BUG=b:169045123
TEST=Built and boot up to kernel on Volteer.

Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: Id4bf41f07c4a53de17e9eb91a8ddfb1083cbf83e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45585
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com>
Reviewed-by: Naveen M <naveen.m@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-24 18:48:44 +00:00
Sheng-Liang Pan 7626e4b3ae mb/google/volteer/var/voxel: Update gpio settings for EVT
Based on EVT schematic and gpio table of voxel, update gpio settings for
voxel EVT.

BUG=b:156841729
TEST=FW_NAME=voxel emerge-volteer coreboot chromeos-bootimage

Signed-off-by: Pan Sheng-Liang <sheng-liang.pan@quanta.corp-partner.google.com>
Change-Id: Idf88d83ad6d873283eb1eb8a45459ae3e74df124
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45173
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-24 18:37:20 +00:00
Paul Fagerburg 39dbb86bbe templates: add ddr4-spd-empty.hex to SPD_SOURCES
We need at least one SPD in SPD_SOURCES when creating a new variant
of trembyle or dalboz, or else coreboot won't build. Add the empty
DDR4 SPD so that we can build the new variant.
Add an empty mem_parts_used.txt so that the developer can add the
supported memory parts and regenerate spd/Makefile.inc using
spd_tools.

BUG=b:169199396
TEST=create a new variant of dalboz or trembyle and observe that
the build succeeds.

Signed-off-by: Paul Fagerburg <pfagerburg@chromium.org>
Change-Id: I764690c76529780186d0a1d156a623821f9d6972
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45638
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
2020-09-24 15:29:50 +00:00
Maxim Polyakov 0c5dd9febb soc/intel/common/smbus: Add support for Apollo Lake SoC
Previously, SMBUS support was not required for Apollo Lake, since the
SPD was read inside FSP-M, during memory initialization. However, the
Kontron mAL-10 COMe module contains Nuvoton HWM chip that is connected
to the processor via SMBUS. This patch adds SMBUS common driver support
for Apollo Lake to initialize this HWM.

TEST = After loading the nct7802 module on the Kontron mAL-10 with Linux
       OS, we can read the hwm registers, see temperature and fan speed:

coretemp-isa-0000
Adapter: ISA adapter
Package id 0:  +52.0°C  (high = +110.0°C, crit = +110.0°C)
Core 0:        +52.0°C  (high = +110.0°C, crit = +110.0°C)
Core 1:        +52.0°C  (high = +110.0°C, crit = +110.0°C)
Core 2:        +53.0°C  (high = +110.0°C, crit = +110.0°C)
Core 3:        +53.0°C  (high = +110.0°C, crit = +110.0°C)

nct7802-i2c-0-2e
Adapter: SMBus CMI adapter cmi
in0:          +3.35 V  (min =  +0.00 V, max =  +4.09 V)
in1:          +1.92 V
in3:          +1.21 V  (min =  +0.00 V, max =  +2.05 V)
in4:          +1.68 V  (min =  +0.00 V, max =  +2.05 V)
fan1:           0 RPM  (min =    0 RPM)
fan2:        1729 RPM  (min =    0 RPM)
fan3:           0 RPM  (min =    0 RPM)
temp1:        +53.5°C  (low  =  +0.0°C, high = +85.0°C)
                       (crit = +100.0°C)  sensor = thermistor
temp4:        +53.0°C  (low  =  +0.0°C, high = +85.0°C)
                       (crit = +100.0°C)
temp6:         +0.0°C

Change-Id: I408ef84ede27a45fb057e22b2757fa6e66277ddd
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44475
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-24 11:52:00 +00:00
Felix Singer da3375ed41 mb: Copy system76/lemp9 to clevo/l140cu
Copy system76/lemp9 to clevo/l140cu, since it's a Clevo notebook
actually and both have the same mainboard.

This commit is meant to create a working copy for clevo/l140cu. The only
changes are names. Further patches will follow to make this mainboard
more generic.

Since system76/lemp9 is based on System76's EC firmware, EC stuff does
not work correctly yet. This will be fixed in another patch.

Tested on TUXEDO InfinityBook S 14 v5 and PCZ Lafité Pro 14.

Change-Id: I7c2993256fd9123a8013df5ba8292ea1ead10f74
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45624
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-09-24 06:19:12 +00:00
Subrata Banik 80835a10e1 soc/intel/alderlake/romstage: Fix compilation issue
Refer to commit 490546f (soc/intel: rename get_prmrr_size) for details.

Change-Id: I4a83feedcdb337ba9613a07215196bc223fb46d1
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45651
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-24 06:17:58 +00:00
Felix Held 32be9f9045 mb/google/zork: simplify flashmap file
Now that we're using fmaptool to parse the .fmd file, we can use some
short forms and omit unnecessary information.

BUG=b:157068645
TEST=None
BRANCH=zork

Change-Id: I81c121d4fce13a9d2aad4477955cb4770794d244
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45597
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-09-23 23:36:25 +00:00
Felix Held fc6a4c6c49 mb/amd/mandolin: simplify flashmap file
Now that we're using fmaptool to parse the .fmd file, we can use some
short forms and omit unnecessary information.

BUG=b:157068645
TEST=Timeless build for amd/mandolin resulted in identical binary.
BRANCH=zork

Change-Id: I196c7857f165e75b543c1bda650e044b5ad0664e
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45596
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-09-23 23:34:19 +00:00
Felix Held 77a63ef0fd soc/amd/picasso: use output of fmaptool to find APOB region
Parse the generated fmap_config.h file instead of the .fmd file supplied
by the board to determine the size and location of the APOB region.
Parsing the generated file allows to write .fmd files without having to
take into account that the shell script part in Picasso's Makefile.inc
can only parse a subset of the .fmd syntax.

BUG=b:157068645
TEST=Timeless build for amd/mandolin resulted in identical binary.
BRANCH=zork

Change-Id: I6ed1903a8157374d78d2865621baa15774d2a7d7
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45595
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-23 23:33:58 +00:00
Pablo Stebler 9ac91d220f util/intelmetool: Fix the BootGuard dump feature
Read the correct bits for measured and verified boot, print information
about some other bits.

Signed-off-by: Pablo Stebler <pablo@stebler.xyz>
Change-Id: Ie79d6da33032aee94d716bf0698b5501bbc424fa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45516
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-23 20:58:28 +00:00
Shreesh Chhabbi ca128a0eb4 mb/intel/tglrvp: Enable Intel Speed Shift Technology for Tigerlake RVP
BUG=none
TEST=Build for Tigerlake RVP and boot to OS. Test if following sysfs is populated.
cat /sys/devices/system/cpu/intel_pstate/

Signed-off-by: Shreesh Chhabbi <shreesh.chhabbi@intel.corp-partner.google.com>
Change-Id: Ie3d9691e149a6fbc19c6691896126d04c680fde3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45609
Reviewed-by: Shreesh Chhabbi <shreesh.chhabbi@intel.com>
Reviewed-by: Ravishankar Sarawadi <ravishankar.sarawadi@intel.com>
Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-23 18:52:28 +00:00
Jamie Ryu 5b7daa224c soc/intel/tigerlake: Configure FSP UPDs for minimum assertion widths
Configure FSP UPDs for the chipset minimum assertion widths and
power cycle duration per mainboard variants.

* PchPmSlpS3MinAssert: SLP_S3 Minimum Assertion Width Policy
* PchPmSlpS4MinAssert: SLP_S4 Minimum Assertion Width Policy
* PchPmSlpSusMinAssert: SLP_SUS Minimum Assertion Width Policy
* PchPmSlpAMinAssert: SLP_A Minimum Assertion Width Policy
* PchPmPwrCycDur: PCH PM Reset Power Cycle Duration
* Check to avoid violating the PCH EDS recommendation for the
  PchPmPwrCycDur setting.

BUG=b:159108661

Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Change-Id: I8180d95a2185c3786334e10613f47e77b7bc9d5f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44557
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-23 16:24:42 +00:00
Marx Wang 81ab88b416 mb/google/octopus: Set ModPhyIfValue to default value 0x12
0x12 will be more stable according to validation result on SD card and
USB devices.

BUG=b:163382089
BRANCH=none
TEST=check if SD cards and USB devices work properly

Signed-off-by: Marx Wang <marx.wang@intel.com>
Change-Id: Ic98f27b6164daa3667009300439c61fed43a4a0b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45573
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Henry Sun <henrysun@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-23 15:21:28 +00:00
Felix Held d57c1286de util/cbfstool/fmaptool: generate defines for all fmap sections
Add defines for the start and size of the FMAP sections to the
optionally generated header file. For the defines the name of the
corresponding FMAP section is used without the full path, since every
section name should be unique anyway as documented here:
Documentation/lib/flashmap.md

BUG=b:157068645
TEST=Generated header file contains expected defines.
BRANCH=zork

Change-Id: Ie31161cfd304b69a3cb4bb366bf365d979e77c64
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45594
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-09-23 13:39:21 +00:00
Felix Held c99bd4a6c9 util/cbfstool/fmd: make flashmap_flags bitfield struct elements unsigned
One bit wide bitfields should always be unsigned, since they can only be
either 0 or -1, but never 1 which is assigned to that bit field in some
cases. Making this unsigned allows it to have the values 0 or 1 which is
what we want there.

BUG=b:157068645
BRANCH=zork

Change-Id: I99c236df583528848b455ef424504e6c2a33c5d6
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45593
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-09-23 13:39:14 +00:00
Michael Niewöhner c521d1587c lib/Makefile.inc: drop redundant conditional on CONFIG_HAVE_SPD_IN_CBFS
Change-Id: I56d13540b2c6b66d5c674ae3d5bab0ac9505df58
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45154
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-23 11:11:20 +00:00
John Zhao 000193aa90 mb/dell: Fix uninitialized variables usage
Coverity detects uninitialized variables through PASS_BY_REFERENCE
usage. Fix this issue by initializing variables before their uage.

Found-by: Coverity CID 1429765, 1429772, 1429780
TEST=None

Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: Ie583b072a76949fb3f17c1271a6427ee942db0ce
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45611
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2020-09-23 09:36:33 +00:00