Commit Graph

7660 Commits

Author SHA1 Message Date
Kyösti Mälkki 1cca340942 Use defines for some i82801ex/gx registers
Change-Id: I0069ec26278b82d61ce5bcfb94d77647dfd3254b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/2530
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-02-28 00:36:55 +01:00
Stefan Reinauer 8f4647a24b ARMv7: drop special handling for stages.c
This is a leftover from when we were debugging
this code. Let's make it easier to understand.

Change-Id: Ia3d0ab1504ff9dd9634d5f393d3c59fe1e43a0c0
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2543
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-28 00:00:50 +01:00
Stefan Reinauer fd611f9c2c Drop CONFIG_WRITE_HIGH_TABLES
It's been on for all boards per default since several years now
and the old code path probably doesn't even work anymore. Let's
just have one consistent way of doing things.

Change-Id: I58da7fe9b89a648d9a7165d37e0e35c88c06ac7e
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2547
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-28 00:00:30 +01:00
Stefan Reinauer 9c29cfae8c Fix microcode selection code
The ARM CPUs we know of don't have CPU microcode updates,
so don't show the selection in Kconfig.

Also simplify (and fix) the microcode selection in the Makefile
that would try to include microcode even though none is available.

Change-Id: I502d9b48d4449c1a759b5e90478ad37eef866406
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2540
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
2013-02-27 21:01:53 +01:00
Ronald G. Minnich eeb36326b9 Google/snow: update the GPIO emulation.
Add two more GPIOs (total 6) as needed by the Google Snow laptop.
These are faking out settings for now. This code is tested and working.

Change-Id: I2077ffb8b85958eefdf54e19763d57cc1178ce89
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/2538
Reviewed-by: Peter Stuge <peter@stuge.se>
Tested-by: build bot (Jenkins)
2013-02-27 19:27:45 +01:00
Jens Rottmann fc14874352 Persimmon: remove HDMI Audio, PCI device 00:01.1 from devicetree.cb
Commit 8487229b (Persimmon doesn't have HDMI so the GNB HD Audio should be
disabled.) turned off the device in AGESA.  Now remove it from
devicetree.cb, too.  This prevents the following boot message:

PCI: Left over static devices:
PCI: 00:01.1
PCI: Check your devicetree.cb.

Also clarify the line's comment a bit for the Fam14 boards which still
retain this device (to counter the loss of information ;-).

Change-Id: Ib671ed2e0d04bdef2869e8d70208d6e55cdea3fd
Signed-off-by: Jens Rottmann <JRottmann@LiPPERTembedded.de>
Reviewed-on: http://review.coreboot.org/2537
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
2013-02-27 17:05:46 +01:00
Hung-Te Lin fdfd89f213 selfboot: Report correct entry point address in debug message.
Entry point in payload segment header is a 64 bit integer (ntohll). The debug
message is currently reading that as a 32 bit integer (which will produce
00000000 for most platforms).

Change-Id: I931072bbb82c099ce7fae04f15c8a35afa02e510
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: http://review.coreboot.org/2535
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
2013-02-27 10:26:26 +01:00
Aaron Durbin 62f100b028 smm: Update rev 0x30101 SMM revision save state
According to both Haswell and the SandyBridge/Ivybridge
BWGs the save state area actually starts at 0x7c00 offset
from 0x8000. Update the em64t101_smm_state_save_area_t
structure and introduce a define for the offset.

Note: I have no idea what eptp is. It's just listed in the
haswell BWG. The offsets should not be changed.

Change-Id: I38d1d1469e30628a83f10b188ab2fe53d5a50e5a
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2515
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-27 03:03:50 +01:00
Marc Jones da3087f67d Mainboard SMI S state handler was using the wrong defines
The PCH register bit definition for sleep type is a little confusing.
For example, 7 is S5. To make this simpler for the mainbaord developer,
the mainboard smi sleep hander is called as mainboard_sleep(slp_typ-2).
A couple mainboard SMI handlers were using the PCH define for slp_ty,
so S3 code would be run for S5 and S5 code would never be run.

Change-Id: Iaecf96bfd48cf00153600cd119760364fbdfc29e
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/2514
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-27 03:03:05 +01:00
Kyösti Mälkki db4f875a41 IOAPIC: Divide setup_ioapic() in two parts.
Currently some southbridge codes implement the set_ioapic_id() part
locally and do not implement the load_vectors() part at all.
This change allows clean-up of those southbridges without introducing
changed behaviour.

Change-Id: Ic5e860b9b669ecd1e9ddac4bbb92d80bdb9c2fca
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/300
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-02-27 00:27:45 +01:00
Kyösti Mälkki e614353194 Unify setting 82801a/b/c/d IOAPIC ID
Remove obscure local copy of writing the ioapic registers.

Change-Id: I133e710639ff57c6a0ac925e30efce2ebc43b856
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/2532
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-02-26 23:38:49 +01:00
Paul Menzel cf4ecfbe01 AMD Inagua: buildOpts.c: Adapt whitespace to coding style
Mainly replace spaces by tabs and format comments correctly.

Commit »Inagua: Indent and wihtespace cleanup« (f03360f3) [1] was
unfortunately incomplete and also used spaces instead of tabs in
some cases.

Hopefully fix this once and for all to have a template for the
other boards.

[1] http://review.coreboot.org/547

Change-Id: If15c797581dfefe2a57cd6f26e5bdac4cdd014dd
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/2526
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-02-26 23:20:57 +01:00
Jens Rottmann 030902b774 AGESA: skip s3_resume.h if CONFIG_HAVE_ACPI_RESUME is disabled
Commit »AMD S3: Introduce Kconfig variable 'S3_DATA_SIZE'« (22ec9f9a) [1]
introduced a check throwing an error if S3_DATA_SIZE isn't big enough.

However without CONFIG_HAVE_ACPI_RESUME the variable S3_DATA_SIZE
isn't defined at all and compilation will fail if s3_resume.h is
included.

This patch makes it again possible turn off HAVE_ACPI_RESUME relatively
easily in Parmer/Thatcher/Persimmon's Kconfig if you don't care about S3
and don't want flash writes on every boot.

[1] http://review.coreboot.org/2383

Change-Id: I999e4b7634bf172d8380fd14cba6f7f03468fee3
Signed-off-by: Jens Rottmann <JRottmann@LiPPERTembedded.de>
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: http://review.coreboot.org/2528
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
2013-02-26 23:10:59 +01:00
Gabe Black 89ccc9285e libpayload: Add a pointer for user data on the USB MSC data structure.
This is so the user of libpayload can attach data to the device which it can
retrieve when the device is referred to later, for instance in usbdisk_remove.
Otherwise, there's no direct connection from the usbdev_t structure to any
bookkeeping in the host firmware.

Change-Id: I36fe693b0dcd2098e359c26744e376e73bd3a723
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: http://review.coreboot.org/2513
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.huber@secunet.com>
2013-02-26 21:20:14 +01:00
Jens Rottmann 5e70766f14 AMD Fam14 boards: reduce unnecessary differences, 2nd attempt
This patch reduces unnecessary differences between AMD Inagua, Persimmon,
Union Station, South Station and Asrock E350M1. It's only cosmetical, but
makes them a little bit easier to compare.

This is the remainder of the original http://review.coreboot.org/2464,
parts of which somehow got lost in a flurry of refactoring and splitting
patches.

Change-Id: I034228be9edaaa4122506763d7bb4158f8e0ec53
Signed-off-by: Jens Rottmann <JRottmann@LiPPERTembedded.de>
Reviewed-on: http://review.coreboot.org/2529
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
2013-02-26 16:53:16 +01:00
Gabe Black 37ef52d44b libpayload: Correct a constant used for scanning for USB controllers.
When checking to see if a PCI device exists at a particular bus/dev/func,
libpayload was checking the vendor and device id fields together against a 16
bit 0xffff. The two fields together are 32 bits, however, so the check was
never true, and all dev/func combinations on a particular bus would be
checked. That was slightly wasteful, but had relatively small impact.

Change-Id: Iad537295c33083243940b18e7a99af92857e1ef2
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: http://review.coreboot.org/2521
Tested-by: build bot (Jenkins)
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2013-02-26 07:39:06 +01:00
Gabe Black b4523bb691 libpayload: Change the measurement interval for get_cpu_speed to 2 ms.
The interval used to be about 55 ms which is excessively long. Coreboot only
waits for 2 ms and gets a reasonable answer. That should be good enough for us
as well.

Change-Id: I4d4e8b25b6ba540c9e9839ed0bbaa1f04f67cce1
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: http://review.coreboot.org/2520
Tested-by: build bot (Jenkins)
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2013-02-26 07:38:41 +01:00
Dave Frodin 502533f656 Revert "AMD S3: Program the flash in a bigger data packet"
This reverts commit ca6e1f6c04.
The packet size changes ends up corrupting the flash when booting
Persimmon. I did figure out that the maximum number of bytes that
can be sent is actually 8 bytes according to the sb800 spec. There
must be additional problems beyond that since setting the packet
size to 8 still causes problems.

Change-Id: Ieb24247cf79e95bb0e548c83601dfddffbf6be59
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/2509
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-by: Zheng Bao <zheng.bao@amd.com>
2013-02-26 03:34:08 +01:00
Mike Loptien a96d24d672 AMD Southbridge: Add RTC init to lpc_init
Adding RTC init code to the Southbridge initialization
code in 'lpc_init'.  This initializes the RTC so that the
Date Alarm register is set to a valid value (0x00) at
startup.  By setting the Date Alarm register to 0x00,
it does not get evaluated along with the seconds,
minutes, and hours when running 'fwts s3'.
Information about fwts (Firmware Test Suite) can be
found here:
https://wiki.ubuntu.com/Kernel/Reference/fwts

This is the same edit made to the CIMX SB800 titled
'AMD/Persimmon: Add RTC init to CIMX SB800' with commit
ID: c4d3d which can be viewed here:
http://review.coreboot.org/#/c/2488/

Change-Id: Iddb7a3cbabe736b511cde03d7dc0a4a0b1c7fd90
Signed-off-by: Mike Loptien <mike.loptien@se-eng.com>
Reviewed-on: http://review.coreboot.org/2510
Reviewed-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
2013-02-25 19:28:43 +01:00
Martin Roth 7675d8a481 Supermicro H8SCM & H8QGI: Fix printk warnings
Changes:
 - Fix printk warnings for these two platforms by getting rid of the
   l length specifier and casting to unsigned int.
   This gets rid of a bunch of warnings like this one:
     agesawrapper.c:279, GNU Compiler 4 (gcc), Priority: Normal
     format '%lu' expects argument of type 'long unsigned int',
       but argument 3 has type 'UINT32' [-Wformat]

Notes:
 - This is the same change that was done for Tyan s8226 in change:
   ddff32eb - http://review.coreboot.org/#/c/2451/
   Tyan S8226: Fix printk warnings

 - I have not tested this change on either of these platforms, I have
   just compiled it.

Change-Id: I46b4c13fde7473cd2a084c7c7cb5c893f1731b02
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/2502
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-02-25 19:02:21 +01:00
Martin Roth 4f5a433a98 AMD Southstation: Fix final warning
Changes:
 - Add #include of delay.h in mainboard.c to pick up declaration of
   mdelay function.

Notes:
 - This fixes this warning:
   mainboard.c:69, GNU Compiler 4 (gcc), Priority: Normal
   implicit declaration of function 'mdelay' [-Wimplicit-function-declaration]

Change-Id: I72f333cd87215a7fc1e62d1d7ee4b2395444b03e
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/2501
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-02-25 19:00:52 +01:00
Paul Menzel 4fc600442b AMD Fam14 boards: Set P_BLK length to 6 for all processors
Currently on for example on AMD Persimmon and ASRock E350M1 Linux
complains, that the PBLK length is invalid [1].

        ACPI: Invalid PBLK length [0]

Consequently, frequency scaling might not work correctly, though for
these two boards it seems to work according to PowerTOP.

Indeed, according to the ACPI specification [2], setting PBlockLength
to 0 is only allowed if there is no PBlockAddress. Otherwise it has to
be set to 6.

        18.5.93 Processor (Declare Processor)

        […]

        PBlockAddress provides the system I/O address for the processors
        register block. Each processor can supply a different such
        address. PBlockLength is the length of the processor register
        block, in bytes and is either 0 (for no P_BLK) or 6. With one
        exception, all processors are required to have the same
        PBlockLength. The exception is that the boot processor can have
        a non-zero PBlockLength when all other processors have a zero
        PBlockLength. It is valid for every processor to have a
        PBlockLength of 0.

And that is exactly what Linux is checking in
`drivers/acpi/processor_driver.c` [3].

        static int acpi_processor_get_info(struct acpi_device *device)
        {
        […]
                /*
                 * On some boxes several processors use the same processor bus id.
                 * But they are located in different scope. For example:
                 * \_SB.SCK0.CPU0
                 * \_SB.SCK1.CPU0
                 * Rename the processor device bus id. And the new bus id will be
                 * generated as the following format:
                 * CPU+CPU ID.
                 */
                sprintf(acpi_device_bid(device), "CPU%X", pr->id);
                ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Processor [%d:%d]\n", pr->id,
                                  pr->acpi_id));

                if (!object.processor.pblk_address)
                        ACPI_DEBUG_PRINT((ACPI_DB_INFO, "No PBLK (NULL address)\n"));
                else if (object.processor.pblk_length != 6)
                        printk(KERN_ERR PREFIX "Invalid PBLK length [%d]\n",
                                    object.processor.pblk_length);
                else {
                        pr->throttling.address = object.processor.pblk_address;
                        pr->throttling.duty_offset = acpi_gbl_FADT.duty_offset;
                        pr->throttling.duty_width = acpi_gbl_FADT.duty_width;

                        pr->pblk = object.processor.pblk_address;

                        /*
                         * We don't care about error returns - we just try to mark
                         * these reserved so that nobody else is confused into thinking
                         * that this region might be unused..
                         *
                         * (In particular, allocating the IO range for Cardbus)
                         */
                        request_region(pr->throttling.address, 6, "ACPI CPU throttle");
                }
        […]
        }

This issue has proliferated to all AMD based boards so fix it for
all of them by setting P_BLK length to 6.

The DSDT of for example AMD Parmer and AMD Thatcher also set it
to 6 everywhere so this solution is taken instead of setting the
P_BLK system I/O base to 0 for all but the first processor which
is how it is done for earlier AMD based boards.

As note having to set this manually should not be needed and
this should be autogenerated as done for most of the Intel boards
and the AMD K8 based boards (`src/cpu/amd/model_fxx/powernow_acpi.c`).

[1] http://www.coreboot.org/pipermail/coreboot/2013-January/073636.html
[2] http://acpi.info/DOWNLOADS/ACPIspec40a.pdf
[3] http://git.kernel.org/?p=linux/kernel/git/torvalds/linux.git;a=blob;f=drivers/acpi/processor_driver.c;h=e83311bf1ebdaaaea1adbf2de1351cca907d3465;hb=5da1f88b8b727dc3a66c52d4513e871be6d43d19#l351

Tested-by: Paul Menzel <paulepanter@users.sourceforge.net>
• ASRock E350M1:
Tested-by: Paul Menzel <paulepanter@users.sourceforge.net>
• AMD Persimmon:
Tested-by: Martin Roth <martin.roth@se-eng.com>
Change-Id: Ie79fe4812532d124cc81747c75a4f3d88d00531c
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/2189
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin.roth@se-eng.com>
2013-02-25 18:55:31 +01:00
Jens Rottmann a48918f75d Persimmon, Inagua: PCI devs 12.1, 13.1 (USB) don't exist, but 14.6 (GEC) does
USB ports 0-4 are handled by PCI devices 12.0 (OHCI) and 12.2 (EHCI). 12.1
simply does not exist, so remove it from devicetree.cb.  While at it make the
comment more detailed.  Likewise for all USB ports.

USB device 14.6 is the Broadcom GbE MAC integrated in the Hudson-E1.  Add it
to devicetree.cb.  It's used on Inagua (on), but not on Persimmon (off).

Change-Id: Idea27b3390fa4470f2592e79fdd633d5a218b97b
Signed-off-by: Jens Rottmann <JRottmann@LiPPERTembedded.de>
Reviewed-on: http://review.coreboot.org/2463
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
2013-02-25 18:54:45 +01:00
Paul Menzel 12d60247ab AMD boards: ACPI DSDT: Use COREBOOT for the OEM Table ID field
The DSDT header contains the fields OEMID and OEM Table ID. See
for example ACPI specification 4.0a [1]

    5.2.11.1 Differentiated System Description Table (DSDT)

on page 135. There Table 5-16 contains the descriptions.

Field         Byte Length  Byte Offset  Description
===================================================
OEMID         6            10           OEM ID
OEM Table ID  8            16           The manufacture model ID.

Currently in coreboot there is no common method what to put in
these fields.

Mostly Intel based boards populate it with "CORE  " ore "COREv4"
and AMD based boards populate it with the board vendor and
model number, abbreviated appropriately to fit into these fields.

On most boards the proprietary vendor BIOS seems to leave these
fields – displayed with `sudo dmidecode` under System Information –
blank

    To Be Filled By O.E.M.

and fill out the Base Board Information with the board vendor and
model name.

In [2] Jens Rottmann argues that the this is really just the table
ID used for naming it and that »99% of the DSDT code is not board
specific«.

Both approaches seem to have their advantages, but using the
second one, developers often seem to forget to update them (for
example AMD Thather).

The current situation is at least not optimal. and therefore at
least unify the string in the OEM Table ID. If unifying the
OEM ID is also a good idea this should be done too.

If later on it should be decided that the board vendor and model
should be used again, this should be somehow derived from
Kconfig.

The following command was used for the change [3].

    $ git grep -l '\/\* TABLE ID \*\/' | xargs sed -i '/TABLE ID/s/"\([^"]*\)"/"COREBOOT"/'

This patch is split out from [2].

[1] http://www.acpi.info/spec40a.htm
[2] http://review.coreboot.org/#/c/2464/
[3] http://stackoverflow.com/questions/5207838/sed-regex-matching-text-between-to-double-quotes-when-a-certain-text-appears-i

Change-Id: Iec98c615ce37f928abc1b500eff5aa865d772cb2
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/2472
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-02-25 18:51:29 +01:00
Ronald G. Minnich 3faa2c77ed google/snow: enable GPIO entries and CHROMEOS in building
These were not separable or it would have been two CLs.

Enable CHROMEOS configure option on snow. Write gpio support code for
the mainboard.  Right now the GPIO just returns hard-wired values for
"virtual" GPIOs.

Add a chromeos.c file for snow, needed to build.

This is tested and creates gpio table entries that our hardware can use.

Lots still missing but we can now start to fill in the blanks, since
we have enabled CHROMEOS for this board. We are getting further into
the process of actually booting a real kernel.

Change-Id: I5fdc68b0b76f9b2172271e991e11bef16f5adb27
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/2467
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-02-25 18:50:00 +01:00
Paul Menzel 5f20b35222 QEMU x86: northbridge.c: Name enabling device function to `northbridge_enable`
Similar to the discussion on the coreboot list [1]

    Am Freitag, den 22.02.2013, 02:17 +0100 schrieb Peter Stuge:

    […]

    > Function names should try to be descriptive. "enable_dev" is not very
    > descriptive. I like "mainboard_enable" because it makes output such
    > as
    >
    > printk("%s: foo", __func__);
    >
    > useful.

rename the function for the northbridge to `northbridge_enable`.

[1] http://www.coreboot.org/pipermail/coreboot/2013-February/074549.html

Change-Id: I262311ec511e394550330214621b8c37780c1d4e
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/2496
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-02-25 18:49:15 +01:00
Martin Roth 30901baabc Persimmon: Fix warning, enable warnings as errors
- Fix redefinition warning for SB_GPIO_REG50 introduced in commit
     fa8702cf - http://review.coreboot.org/#/c/2446/
     Persimmon: adapt PCIe reset code copied from Inagua to actually
                 match Persimmon
     The warning being fixed is:
        SB800.h:1491, GNU Compiler 4 (gcc), Priority: Normal
        "SB_GPIO_REG50" redefined [enabled by default]

 - Enable warnings as errors so no more warnings will be accidentally
     committed.

Change-Id: Ib443b2bd2067f0b7d5f93f79170899a0f8f61060
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/2494
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-02-25 18:48:21 +01:00
Paul Menzel 528640d141 mainboard.c: Name enable_dev function uniformly `mainboard_enable`
To reduce the differences between these file name the enabling
device function in the directory `src/mainboard` uniformly
`mainboard_enable` [1].

Thanks to the awesome help of gnomon and BlastHardcheese in the
IRC channel #sed on <irc.freenode.net>. gnomon came up with the
following command to do the actual work.

    $ cd src/mainboard
    $ for f in */*/mainboard.c ; \
    > do src="$(awk '/\.enable_dev = /{v=$NF; sub(/,$/,"",v); print v}' "$f")" ; \
    > [[ -z $src ]] && continue ; \
    > printf '%s\n' "g/${src}/s/${src}\([,(]\)/mainboard_enable\1/p" w | ed -s "$f" ; \
    > done

`src/mainboard/digitallogic/msm586seg/mainboard.c` and
`src/mainboard/technologic/ts5300/mainboard.c` had to be adapted
manually as no comma was used separating the struct members.

And with the following statement, gnomon is even more likable!

    My pleasure entirely.  Good luck with coreboot; I'm a big fan of the project.

[1] http://www.coreboot.org/pipermail/coreboot/2013-February/074548.html

Change-Id: Ife9cd0c2d9cc1ed14afc6d40063450553f06a6c6
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/2493
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-02-25 18:47:00 +01:00
Paul Menzel 1fc7416545 Technologic TS5300: mainboard.c: Move { to next line
This is coreboot’s coding style.

Change-Id: I7441f2c1927a49a3b7171112b7798dae6b56cfb5
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/2492
Reviewed-by: Martin Roth <martin.roth@se-eng.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Bernhard Urban <lewurm@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-02-25 18:46:31 +01:00
Stefan Reinauer 1cd6160821 ARMv7: Simplify div64
We don't need the overly complex optimized version, since
we're only doing this in very few non-critical places.

Also, add the div* files to the bootblock, they're needed
if we do printk.

Signed-off-by: Stefan Reinauer <reinauer@google.com>

Change-Id: I83bd766d4b03b488326ade1c13b7c364a7119e7b
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/2508
Tested-by: build bot (Jenkins)
2013-02-25 17:01:27 +01:00
Paul Menzel 14c2398ce9 Siemens SITEMP G1P1: mainboard.c: Rename `init` to `mainboard_init`
This is the common way to name that function, so unify that.

Change-Id: I8a01051bd304039662894b89eed53ce14dde98b6
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/2491
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-02-24 17:03:08 +01:00
Martin Roth e533fdaa59 AMD f14 vendorcode: Fix warning
Add brackets around initializer in #define for
PCIE_DDI_DATA_INITIALIZER to fix the warning:
  PlatformGnbPcie.c:89, GNU Compiler 4 (gcc), Priority: Normal
  missing braces around initializer [-Wmissing-braces]

This warning happens for Inagua and South Station

Change-Id: I7d8f742dd8335b704b0493aa6e9eaebc3cc50b1e
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/2495
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-02-24 17:01:20 +01:00
Stefan Reinauer 49428d8403 Add support for Google's Chromebook Pixel
Ladies and gentlemen, I'm very happy to announce coreboot support for
the latest and greatest Google Chromebook: The Chromebook Pixel.

See the link below for more information on the Chromebook Pixel, and
its exciting specs:
http://www.google.com/intl/en/chrome/devices/chromebooks.html#pixel

The device is running coreboot and open source firmware on the EC
(see ChromeEC commit for more information on that exciting topic)

Change-Id: I03d00cf391bbb1a32f330793fe9058493e088571
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2482
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-23 04:27:08 +01:00
Jens Rottmann 940095fe5e AMD based boards: platform_cfg.h: Replace `_*BOARDNAME*_CFG_H_` with `_PLATFORM_CFG_H_`
Reduce unnecessary differences between AMD based boards only
using the file `platform_cfg.h` for configuration making them
a little bit easier to compare.

Inagua & co. mention the board name in several places which are really not
that board specific.  Sometimes people even forget to change it:
Union Station’s platform_cfg.h starts with "#ifndef _PERSIMMON_CFG_H_".
Funny.  Change that to "_PLATFORM_CFG_H_" everywhere.

The following command was used.

    $ find . -name platform_cfg.h | xargs sed -i '/_CFG_H_/s/_.*_/_PLATFORM_CFG_H_/'

More boards seem to use that kind of naming (`git grep _CFG_H_`)
but it is not certain that this will not break anything as for
example the board AMD Dinar also has header files for
configuration stuff for the north- and southbridge.

    $ git grep _CFG_H_
    […]
    src/mainboard/amd/dinar/platform_cfg.h:#ifndef _PLATFORM_CFG_H_
    src/mainboard/amd/dinar/platform_cfg.h:#define _PLATFORM_CFG_H_
    src/mainboard/amd/dinar/platform_cfg.h:#endif //_PLATFORM_CFG_H_
    src/mainboard/amd/dinar/rd890_cfg.h:#ifndef  _RD890_CFG_H_
    src/mainboard/amd/dinar/rd890_cfg.h:#define _RD890_CFG_H_
    src/mainboard/amd/dinar/rd890_cfg.h:#endif //_RD890_CFG_H_
    src/mainboard/amd/dinar/sb700_cfg.h:#ifndef _SB700_CFG_H_
    src/mainboard/amd/dinar/sb700_cfg.h:#define _SB700_CFG_H_
    src/mainboard/amd/dinar/sb700_cfg.h:#endif //_SB700_CFG_H
    […]

Change-Id: Ida15fa6a7adfc770240ac30e795946000dae3f16
Signed-off-by: Jens Rottmann <JRottmann@LiPPERTembedded.de>
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/2464
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin.roth@se-eng.com>
2013-02-23 01:22:29 +01:00
Mike Loptien ac529b1e15 AMD/Persimmon: Add RTC init to CIMX SB800
Adding RTC init code to the Southbridge initialization
code in 'late.c'.  This initializes the RTC so that the
Date Alarm register is set to a valid value (0x00) at
startup.  By setting the Date Alarm register to 0x00,
it does not get evaluated along with the seconds,
minutes, and hours when running 'fwts s3'.
Information about fwts (Firmware Test Suite) can be
found here:
https://wiki.ubuntu.com/Kernel/Reference/fwts

This was tested on a Persimmon but will apply to
other mainboards as well.

Change-Id: I9a11bc3f9e3f53c46e7a4d72e62ebb0a4ba1bfe4
Signed-off-by: Mike Loptien <mike.loptien@se-eng.com>
Reviewed-on: http://review.coreboot.org/2488
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-02-23 01:16:50 +01:00
Stefan Reinauer d6682e88af Add support for Google ChromeEC
Google ChromeEC is an EC with completely open source firmware.
See https://gerrit.chromium.org/gerrit/gitweb?p=chromiumos/platform/ec.git;a=summary
for the EC firmware source code (aka more information about the ChromeEC)

This patch adds support for the ChromeEC on coreboot's side.

Great thanks to the ChromeEC team for this amazing work. It's another
important milestone towards a free and open firmware stack on modern
hardware.

Change-Id: Iace78af9d291791d2f5f80ccca1587b418738cec
Signed-off-by: Stefan Reinauer <reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/2481
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-22 23:10:01 +01:00
Patrick Georgi 50f313c8b2 */acpi_tables.c: Use ALIGN macro
At the request of Paul Menzel, I reran an
old classic of a coccinelle script:
  @@
  expression E;
  @@
  -(E + 7) & -8
  +ALIGN(E, 8)

  @@
  expression E;
  @@
  -(E + 15) & -16
  +ALIGN(E, 16)

Change-Id: I01da31b241585e361380f75aacf3deddb13d11c3
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/2487
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-02-22 22:38:50 +01:00
Patrick Georgi 12781422d5 nvramtool: reduce memory mapping
Instead of trying to map the first megabyte, only map what is
required to read the tables.

Change-Id: I9139dbc8fd1dd768bef7ab85c27cd4c18e2931b3
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/2485
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
2013-02-22 16:04:03 +01:00
Hung-Te Lin fbf078311f libpayload: cbfs: Fix CBFS max size calculation.
Cherry-picking CBFS fix from http://review.coreboot.org/#/c/2292/

For x86, the old CBFS search behavior was to bypass bootblock and we should keep
that.  This will speed up searching if a file does not exist in CBFS.
For arm, the size in header is correct now so we can remove the hack by
CONFIG_ROM_SIZE.

Change-Id: I286ecda73bd781550e03b0b817ed3fb567d6b8d7
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: http://review.coreboot.org/2458
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-02-22 09:23:43 +01:00
Hung-Te Lin 58fd5e1d3d libcbfs: Fix legacy CBFS API, typos
Pulling CBFS fix from libpayload: http://review.coreboot.org/#/c/2455/2

get_cbfs_header expects CBFS_HEADER_INVALID_ADDRESS (0xffffffff)
instead of NULL when something is wrong.
Also, fix typo.

Change-Id: I7f393f7c24f74a3358f7339a3095b0d845bdc02d
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: http://review.coreboot.org/2457
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-02-22 09:23:04 +01:00
Stefan Reinauer 39d497d5cf Update 3rdparty mark to latest repository
Change-Id: Ied5515a332e3f2f9abbed1c015cad76f7bb4cd9f
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2480
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
2013-02-22 09:22:41 +01:00
Paul Menzel 2872f4e946 AMD Fam14 boards: Unify `acpi_table.c` by mainly using Inagua’s one
There were just whitespace differences and three boards did not
contain

    printk(BIOS_DEBUG, "alib\n");
    dump_mem(ssdt, ((void *)alib) + alib->length);

which is enclosed `#if DUMP_ACPI_TABLES == 1` to dump the ACPI
tables.

Basically the whitespace in the license header in Inagua’s file
was fixed and then the file copied over to the other directories.

Change-Id: I23f73acad427b5ec14cf51651af67240871f7488
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/2470
Tested-by: build bot (Jenkins)
Reviewed-by: Alvaro G. <andor@pierdelacabeza.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-02-21 23:15:14 +01:00
Paul Menzel 522b55638f AMD boards: Fix typo `@brief` in comment
The following command was used to correct the typo.

    $ git grep -l @breif | xargs sed -i 's/@breif/@brief/'

Change-Id: If0b579279de3c41571b9cda643836f5748a752a2
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/2473
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-02-21 23:14:50 +01:00
Jens Rottmann 824e192809 Persimmon: platform_cfg.h: Declare codec arrays as `static const`
From ISO C99 standard: »The placement of a storage-class specifier
other than at the beginning of the declaration specifiers in a
declaration is an obsolescent feature.«

Found at <http://www.approxion.com/?p=41>.

Change-Id: Iee7878affb2a5d157a94763083689d75e8218b2f
Signed-off-by: Jens Rottmann <JRottmann@LiPPERTembedded.de>
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/2474
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-02-21 19:33:52 +01:00
Paul Menzel 3138bb875c Persimmon: dimmSpd.c: Use spaces for alignment of if-predicate
The relational operators in the if-predicate are aligned in all
`dimmSpd.c` files so revert part of the change in

    commit 36abff1dc8
    Author: Marc Jones <marcj303@gmail.com>
    Date:   Mon Nov 7 23:26:14 2011 -0700

        Cleanup Persimmon mainboard whitespace.

        Reviewed-on: http://review.coreboot.org/427

to remove the incorrectly introduced tabs and to unify that. It
might contradict the current coding style but it is even used in
the latest code as seen in the following file.

     src/northbridge/amd/agesa/family15tn/dimmSpd.c

Change-Id: Ib611267f99090d0830bdc2319527389f193ea1eb
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/2471
Reviewed-by: Alvaro G. <andor@pierdelacabeza.com>
Tested-by: build bot (Jenkins)
2013-02-21 14:51:05 +01:00
Paul Menzel cec4cfdb13 Persimmon: Indent comment
This was overlooked in the following commit.

    commit 36abff1dc8
    Author: Marc Jones <marcj303@gmail.com>
    Date:   Mon Nov 7 23:26:14 2011 -0700

        Cleanup Persimmon mainboard whitespace.

        Reviewed-on: http://review.coreboot.org/427

Change-Id: If6bf4836b46077614a04c1e106c241a4f97da166
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/2468
Tested-by: build bot (Jenkins)
Reviewed-by: Alvaro G. <andor@pierdelacabeza.com>
2013-02-21 12:08:51 +01:00
Jens Rottmann df729d7778 AMD Fam14 boards: dimmSpd.c: Set `iobase` to `SMBUS0_BASE_ADDRESS` instead of `0xB00`
For AMD Inagua, the following two commits

    commit 01f7ab9335
    Author: Kerry Sheh <shekairui@gmail.com>
    Date:   Thu Jan 19 13:18:36 2012 +0800

        Inagua: Synchronize AMD/inagua mainboard.

        Reviewed-on: http://review.coreboot.org/542

and

    commit d91c9b7e3c
    Author: efdesign98 <efdesign98@gmail.com>
    Date:   Thu Sep 15 10:59:55 2011 -0600

        AMD Inagua platform updates

        Reviewed-on: http://review.coreboot.org/136

replaced the constant `iobase` is set to by the define `SMBUS0_BASE_ADDRESS` from `OEM.h`.

Do the same for AMD Persimmon, South Station, Union station and ASRock E350M1.

Change-Id: If095cd9d9b28b118b4072c7c9d345bf620b774c9
Signed-off-by: Jens Rottmann <JRottmann@LiPPERTembedded.de>
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/2453
Tested-by: build bot (Jenkins)
2013-02-21 12:01:35 +01:00
Zheng Bao 22ec9f9a72 AMD S3: Introduce Kconfig variable 'S3_DATA_SIZE'
Currently the size of the volatile storage for S3 reserved in the
image is hardcoded to 32768 bytes. Make that configurable by
introducing the Kconfig 'S3_DATA_SIZE'.

As the storage space is needed for storing non-volatile, volatile and
MTRR data, add a check if the size is big enough.

Change-Id: I9152797cf0045c8da48109a9d760e417717686db
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/2383
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-02-21 05:57:57 +01:00
Ronald G. Minnich c8fadd9f46 ARMV7: create a correct LB_SERIAL table entry
If CONFIG_CONSOLE_SERIAL is set, and we can call the standard function
and get a non-zero uart address, then we create an lb table entry.

The code was mostly right, just needed a tweak.

Change-Id: I5b36c7b4e580a23319b7ba92cc8ad61592b1757a
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/2466
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
2013-02-21 01:10:18 +01:00
Paul Menzel a8ae1c66f9 Whitespace: Replace tab character in license text with two spaces
For whatever reason tabs got inserted in the license header text.
Remove one occurrence of that with the following command [1].

    $ git grep -l 'MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.'$'\t' | xargs sed -i 's,MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.[        ]*,MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.\ \ ,'

[1] http://sed.sourceforge.net/grabbag/tutorials/sedfaq.txt

Change-Id: Iaf4ed32c32600c3b23c08f8754815b959b304882
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/2460
Tested-by: build bot (Jenkins)
Reviewed-by: Jens Rottmann <JRottmann@LiPPERTembedded.de>
Reviewed-by: Cristian Măgherușan-Stanciu <cristi.magherusan@gmail.com>
2013-02-20 23:30:45 +01:00