Commit Graph

15928 Commits

Author SHA1 Message Date
Timothy Pearson 1eaaa0e446 southbridge/amd/sr5650: Add MCFG ACPI table support
As the southbridge largely controls the PCI[e] configuration space
this patch moves the resource allocation from the northbridge
to the southbridge when the extended configuration space region
is enabled.

Change-Id: I0c4ba74ddcc727cd92b848d5d3240e6f9f392101
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/12050
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
2015-12-18 19:51:44 +01:00
Timothy Pearson 5f2bf6d02d mainboard/asus/kgpe-d16: Enable CBFS spinlocks
Change-Id: I8f6226d3e74ac5c7f29f708128a7502ced1287bf
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/12062
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2015-12-18 19:48:52 +01:00
Timothy Pearson 7b22d84d55 drivers/pc80: Add optional spinlock for nvram CBFS access
When enabling the IOMMU on certain systems dmesg is spammed with I/O page faults like the following:
AMD-Vi: Event logged [IO_PAGE_FAULT device=00:14.0 domain=0x000a address=0x000000fdf9103300 flags=0x0030]

Decoding the faulting address:
0x000000fdf9103300
        fdf91x          Hypertransport system management region
              33        SysMgtCmd (System Management Command) = 0x33
              3         Base Command Type = 0x3: STPCLK (Stop Clock request)
               3        SMAF (System Management Action Field) = [3:1] = 0x1
               1        Signal State Bit Map = [0] = 0x1

Therefore, the error appears to be triggered by an upstream C1E request.

This was eventually traced to concurrent access to the SP5100's SPI Flash controller by
multiple APs during startup.  Calls to the nvram read functions get_option and read_option
call CBFS functions, which in turn make near-simultaneous requests to the SPI Flash
controller, thus placing the SP5100 in an invalid state.  This limitation is not documented
in any public AMD errata, and was only discovered through considerable debugging effort.

Change-Id: I4e61b1ab767b1b7958ac7c1cf20eee41d2261bef
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/12061
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2015-12-18 19:47:01 +01:00
Stefan Reinauer 5a3f1e54d5 cpu/samsung/exynos5250: Move update-bl1.sh to 3rdparty/blobs/
The binary is taken from blobs, so the script should live over
there, too.

Change-Id: I3cc0aabc846c352ccf5cb348132b320a37f273a6
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/12725
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
2015-12-18 19:06:11 +01:00
Werner Zeh 1f7395bb4d siemens/mc_tcu3: Set GPIO_S0_SC[75] to output
The usage of the pin has changed and therefore this pin needs
to be set up as output and drive low initially.

Change-Id: Ie3eb9cc703f7f73d59fad52ea9e514997d84606a
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/12754
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-12-18 10:48:22 +01:00
Stefan Reinauer d373a00a79 Enable KCONFIG_STRICT mode
Change-Id: I6aa77db1b12a67472302ea39d7433993a6838af6
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/10978
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2015-12-17 21:55:45 +01:00
Denis 'GNUtoo' Carikli d18f81be85 google/veyron: Add commercial board names in Kconfig.name
The correspondence between engineering code names and
commercial names can be found on chromium.org website at:
https://www.chromium.org/chromium-os/developer-information-for-chrome-os-devices

This it to make the names more relevant:
towiki (in util/board_status/to-wiki/towiki.sh) will pick such
names, which end up in the supported board list at:
http://www.coreboot.org/Supported_Motherboards

Change-Id: I2d705672d7202964fea3f62a5bd61a231d3f14c0
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Reviewed-on: https://review.coreboot.org/12652
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
2015-12-17 21:53:48 +01:00
Denis 'GNUtoo' Carikli 3747ba16c7 Kconfig: Fix CONFIG_GDB_STUB dependencies
If we select CONFIG_GDB_STUB without CONFIG_SERIAL:

build/console/console.romstage.o: In function `__gdb_hw_init':
[...]src/include/console/uart.h:74: undefined reference to `uart_init'
build/console/console.romstage.o: In function `__gdb_tx_byte':
[...]/src/include/console/uart.h:75: undefined reference to `uart_tx_byte'
build/console/console.romstage.o: In function `__gdb_tx_flush':
[...]/src/include/console/uart.h:76: undefined reference to `uart_tx_flush'
build/console/console.romstage.o: In function `__gdb_rx_byte':
[...]/src/include/console/uart.h:77: undefined reference to `uart_rx_byte'

Note that CONFIG_GDB_STUB should also work trough usbdebug,
But due to the lack of testing, it has been disabled when added.
This commit gives more information on the issue:
f2f7f03 console: Add console for GDB

Change-Id: I9accf8189dfd2c4ae379c03649d2e5863183457b
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Reviewed-on: https://review.coreboot.org/12708
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2015-12-17 21:35:26 +01:00
Denis 'GNUtoo' Carikli e87e73edba google/veyron: Indicate which boards are laptops.
This is to make towiki pick that information, to make
these boards end up in the laptop list at:
http://www.coreboot.org/Supported_Motherboards

Change-Id: Ibf8bf4bf6566080a34687e36675d4c4c8b89f334
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Reviewed-on: https://review.coreboot.org/12716
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-12-17 21:30:08 +01:00
Stefan Reinauer c32e80d604 Drop src/cpu/ indirection for MIPS
Change-Id: I406166e650e07851ab1b293450fa29da8af075d9
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/12724
Tested-by: build bot (Jenkins)
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
2015-12-17 21:25:31 +01:00
Martin Roth 92898b424b Makefile.inc: Include build/dsdt.d if it exists
The dsdt dependency file is created, but wasn't being used to determine
whether or not to update the dsdt file.  If it's present, include it
into the makefile so dsdt.aml gets rebuilt if any of the depencencies
change.

Change-Id: I76bc22541c6b9740841bda891a5b88030cb949cd
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12699
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-17 21:23:38 +01:00
Ionela Voinescu 2e8d4ed794 soc/imgtec/pistachio: add implementation for system reset
Implement system reset by calling the watchdog soft reset.
Following the soft reset, the SoC will reset to the same logic
state and therefore have the same effect as a hard (power-on)
reset except for:
 - watchdog scratch registers will be unaffected (hard reset
   will clear them)
 - the real time clock will be unaffected

BUG=none
TEST=tested on Pistachio bring up board

Change-Id: I1332c2249c756f6d8574fc5c407de52f88e60f08
Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com>
Reviewed-on: https://review.coreboot.org/12755
Tested-by: build bot (Jenkins)
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
2015-12-17 21:13:57 +01:00
Stefan Reinauer 3bdd45e714 soc/imgtec/pistachio: Implement hard_reset()
Verified boot needs hard_reset() now, so offer a dummy implementation
for the Imagination chip. Sorry, I don't have the specs for this chip
anymore to make a real implementation, but I would like to keep this
code from bit rotting.

Change-Id: I15aa47f7d248b99901a2ac0e65a46b43d7718717
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/12723
Tested-by: build bot (Jenkins)
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
2015-12-17 21:13:35 +01:00
Julius Werner 74babffccb vendorcode: google: chromeos: Remove old fmap.c file
This file became obsolete when FMAP code moved to src/lib/ and is no
longer built by any Makefile. Let's remove it to avoid confusing people.

Change-Id: I55639af28f9f3d4c4cb0429b805e3f120ecc374e
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/12753
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2015-12-17 19:55:26 +01:00
Martin Roth fdaf9cca36 Makefile.inc: Document extract_nth and the fields it extracts
Change-Id: I0b5cffff95aca0ea0d6302b436797dada1850ba0
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12713
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-17 18:59:56 +01:00
Martin Roth ffcd9393a4 soc/intel/fsp_baytrail: Adjust root port INT routing
Adjust the root port INT routing based on Bay Trail spec:
Document Number: 538136, Rev. 3.9

Table 241. Interrupt Generated for INT[A-D] Interrupts
             INTA  INTB  INTC  INTD
Root Port 1 INTA# INTB# INTC# INTD#
Root Port 2 INTD# INTA# INTB# INTC#
Root Port 3 INTC# INTD# INTA# INTB#
Root Port 4 INTB# INTC# INTD# INTA#

Change-Id: I22a8c0bc6ad731dfb79385d6e165f1ec0a07507d
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12684
Tested-by: build bot (Jenkins)
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Ben Gardner <gardner.ben@gmail.com>
2015-12-17 18:08:52 +01:00
Daisuke Nojiri 6d2c7226cb libpayload: add archive.h
archive.h is a header file for the programs which need to parse an archive
created by 'archive' tool. See archive.h for the format description.

BUG=chromium:502066
BRANCH=tot
TEST=Tested on Glados

Change-Id: I2bee9d7c12b0e1bce1529dfef360c5fa4ce0872d
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/311201
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://review.coreboot.org/12734
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-16 19:00:53 +01:00
Ben Gardner 6fc544d3d4 intel/fsp_baytrail: change indent to use tabs
Change-Id: If0d0a15442738bab0e34f1b05513e7f8e8fa9afc
Signed-off-by: Ben Gardner <gardner.ben@gmail.com>
Reviewed-on: https://review.coreboot.org/12698
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2015-12-16 04:53:54 +01:00
Martin Roth 35272fd237 northbridge/intel ACPI: Remove unused Local method
The remainder of the divide operation was being placed into a Local,
but was never being used, causing an IASL warning.  Since this
field is optional, just remove the Local.

Fixes IASL warning:
dsdt.aml 640:Divide (Multiply (CTDN, 125), 100, Local0, PL2V)
Warning  3144 - Method Local is set but never used ^  (Local0)

Change-Id: I0b43ef638b1bc3e1163c45f31f8da57aa0d39e22
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12706
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2015-12-16 04:49:30 +01:00
Martin Roth 019cdbf79b toolchain.inc: print XGCCPATH if it's set
To help a user debug issues, print the current XGCCPATH value if
it's set.

Change-Id: I69afdd1c93cfd4747547ecad0d5e1ab4c87511b7
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12677
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-12-16 01:22:59 +01:00
Ben Gardner 6b07cba70f x86/smbios: Return index 0 for empty strings
Section 6.1.3 (Text Strings) of the SMBIOS specification states:
  If a string field references no string, a null (0) is placed in that
  string field.

Change smbios_add_string() to do that.

Change-Id: I9c28cb89dcfe2c8ef2366c23ee6203e15b7c2513
Signed-off-by: Ben Gardner <gardner.ben@gmail.com>
Reviewed-on: https://review.coreboot.org/12697
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-16 01:20:00 +01:00
Martin Roth 6f656138a6 buildgcc: Add coreboot toolchain version to iasl
Add the coreboot toolchain version to iasl's version output.

% ./xgcc/bin/iasl -v
Intel ACPI Component Architecture
ASL+ Optimizing Compiler version 20150619-64
Copyright (c) 2000 - 2015 Intel Corporation

coreboot toolchain v1.33 November 25th, 2015

This won't actually be checked until the next version of
iasl so that we don't have to rebuild again for no reason.

The buildgcc version was intentionally not incremented for
this minor change.

Change-Id: I03a1a777fdb84e34bfceb7b1eb43fffbc1f3a2fc
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12688
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-16 01:19:14 +01:00
Hannah Williams 03d4ae7684 lib: Fix strncmp
strncmp continues to compare the characters in the input strings past any
null termination it may encounter. Null termination check is added.

Reviewed-on: https://chromium-review.googlesource.com/314815
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Hannah Williams <hannah.williams@intel.com>
Tested-by: Hannah Williams <hannah.williams@intel.com>
(cherry picked from commit ca7022752115eddbcb776f0c0d778249555ddf32)
Reviewed-on: https://chromium-review.googlesource.com/315130

Change-Id: Ifc378966dcf6023efe3d32b026cc89d69b0bb990
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/12721
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-12-16 01:14:22 +01:00
Ben Gardner fa6014a6ec intel/fsp_baytrail: rename include folder baytrail to include/soc
This is to match the layout of the non-fsp baytrail to make comparisons
easier and possibly remove duplicate files.

Change-Id: I9a94842d724ab3826de711d398227e7bdc1045ff
Signed-off-by: Ben Gardner <gardner.ben@gmail.com>
Reviewed-on: https://review.coreboot.org/12686
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-12-16 01:10:06 +01:00
Martin Roth 1e1c7ac3b4 southbridge/amd/sb600: Update HPET base address with #define
The SB600 code had the base address of the HPET hardcoded throughout.
It looks like the plan was to have it be updated in ACPI if needed,
but this wasn't ever implemented.  The variable names being used to
do this update were the same, causing an IASL warning.  Because of
this, the operation to update the HPET address actually did nothing.
This was fine, because it didn't actually need to be updated.

- Replace all that code with a #define.
- Add and update some comments in the same area.

Fixes IASL warning:
dsdt.aml   1505:       Store(HPBA, HPBA)
Warning  3023 -                      ^ Duplicate value in list (Source is the
same as Target)

Change-Id: I9ba5fe226a4a464e0045ce7d3406898760df5e5a
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12705
Tested-by: build bot (Jenkins)
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
2015-12-16 00:56:08 +01:00
Ben Gardner 49bbfcd5d3 intel/fsp_baytrail: Fix PCI_DEV_PIRQ_ROUTE macro ending
The macro PCI_DEV_PIRQ_ROUTE ends with a comma and escaped newline.
Ending a macro with an escaped newline is always wrong.
The final comma is not necessary, as all uses of PCI_DEV_PIRQ_ROUTE()
properly separate calls with a comma.

I haven't investigated whether this is causing a real issue, but it should
be leaving gaps in struct baytrail_irq_route.pcidev.

The non-FSP baytrail does not have this issue.

Change-Id: If6782176068b07cb3bc819c00d1cdb1b618bcea8
Signed-off-by: Ben Gardner <gardner.ben@gmail.com>
Reviewed-on: https://review.coreboot.org/12696
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2015-12-16 00:53:48 +01:00
Alexander Couzens b619f44c67 build system/x86: depend on directories before touch /empty targets
$(objgenerated)/empty would touch files before the directory
is created on parallel builds.

Thanks to reproducible-builds.org for hitting this bug.

Change-Id: I7565e9fe130b4e9deaf1c7b9d568ff90b00dda52
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: https://review.coreboot.org/12717
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-12-16 00:43:22 +01:00
Stefan Reinauer 747d0f898b soc/samsung/exynos5250: Implement hard_reset()
Implement hard_reset() as power_reset() to make
vboot happy.

Change-Id: I16831055bd6ba8a8c95836fcf31f29c068153fcc
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/12722
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Tested-by: build bot (Jenkins)
2015-12-16 00:41:03 +01:00
Stefan Reinauer 490006bf7d intel/skylake: Work around ROMCC optimization bug
On Skylake systems, the bootblock fails to compile with the following
error message:

bootblock_simple.c:6.1:
0x13930e0 copy       Internal compiler error: non dominated rhs use point
0x13a3f70?
Aborted (core dumped)

The option -fno-simplify-phi works around the issue, but will cause the
code to use more registers, hence we also need to enable -mcpu=p4 (see
intel/truxton mainboard for another example of where this has been done
in the past)

Change-Id: Iea1a1ba18d76c7323bb626c5f4b0032e4ee04a86
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/12719
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-12-16 00:31:23 +01:00
Aaron Durbin 07a1b281a8 x86 acpi: remove ALIGN_CURRENT macro
The ALIGN_CURRENT macro relied on a local variable name
as well as being defined in numerous compilation units.
Replace those instances with an acpi_align_current()
inline function.

Change-Id: Iab453f2eda1addefad8a1c37d265f917bd803202
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12707
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-12-15 20:12:01 +01:00
Timothy Pearson ecd4cfcb86 mainboard/asus/kgpe-d16: Enable romstage spinlocks
Change-Id: Iac1adbeacdcded7faff2443b78a491cbb8a90fe8
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/12628
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2015-12-15 16:43:09 +01:00
Timothy Pearson 44d5342835 src/console: Add x86 romstage spinlock option and printk spinlock support
This paves the way for AP printk spinlock on AMD platforms

Change-Id: Ice42a0d3177736bf6e1bc601092e413601866f20
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/11958
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2015-12-15 16:41:13 +01:00
Martin Roth a09bb426d4 google/oak: Move CHROMEOS specific Kconfig objects under CHROMEOS
The symbols CHROMEOS_VBNV_EC, EC_SOFTWARE_SYNC, and VIRTUAL_DEV_SWITCH
should only be selected if CHROMEOS is selected.

Change-Id: I07ef631d63be53cf99a6bf61d0e91b88728dbba3
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12659
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-15 01:14:27 +01:00
Iru Cai 69bbfacd25 msrtool/configure: change svn to git
Change-Id: I212e44fc7edfd1458b04fb42a8e964a3367dd72d
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/12710
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-12-14 22:52:49 +01:00
Timothy Pearson 16ff807ba6 amd/[nb/fam10|sb/sr5650]: Minor cosmetic changes
Change-Id: Ia9cb4fe4f46327e38648f89da0ffce647fb118d3
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/12712
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-12-13 02:20:12 +01:00
Ronald G. Minnich ed4aa043c6 cbfstool: add ppc64 support
The constant for ppc64 is 'hotstuff'. For many reasons.

Note that line 2894 of elf.h is not indented. This is because in the
original the line begins with a space. Checkpatch rejects that.
Checkpatch also rejects changing the space to a tab because that makes
it more than 80 chars. I rejected breaking the line because it makes it
even less readable. All the changes forced by checkpatch make the code
less readable.

Herman Hollerith would be proud.

Change-Id: I21f049fe8c655a30f17dff694b8f42789ad9efb7
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: https://review.coreboot.org/12711
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Tested-by: build bot (Jenkins)
2015-12-12 01:36:51 +01:00
Patrick Georgi 8a3592eec3 build system: Switch to fmap based firmware layout
We still add a master header for compatibility purposes, and the default
layouts don't cover anything non-coreboot (eg. IFD regions) yet.

The default layouts can be overridden by specifying an fmd file, from
which the fmap is generated.

Future work:
- map IFD regions to fmap regions
- non-x86: build minimalistic trampolines that jump into the first cbfs
  file, so the bootblock can be part of CBFS instead of reserving a
  whole 64K for it.
- teach coreboot's cbfs code to work without the master header
- teach coreboot's cbfs code to work on different fmap regions

Change-Id: Id1085dcd5107cf0e02e8dc1e77dc0dd9497a819c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/11692
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2015-12-11 11:40:18 +01:00
Aaron Durbin 929b60267c fsp1_1: supply fsp version to mrc_cache API
The memory init code needs to match the saved mrc data. To
ensure that invariant holds supply the FSP version when
using the mrc cache API.

BUG=chrome-os-partner:46050
BRANCH=None
TEST=Built and booted on glados. Verified version mismatch checking
     works.

Change-Id: I3f6dd19cb15a18761d34509749adafc89a72ed2d
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12701
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-12-11 00:20:08 +01:00
Aaron Durbin bc6e7c0905 mrc_cache: add version field
In order to allow for updateable memory init code on intel x86
platforms one needs to ensure the saved mrc data matches the code
consuming the data. To that end add a version field to the saved
data structure.

BUG=chrome-os-partner:46050
BRANCH=None
TEST=Built and booted on glados. Suspended and resumed. Also verified
     version mismatch path.

Change-Id: Ie86db1750af5d9bff6446999b0d04b60612f8d29
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12700
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-12-11 00:20:02 +01:00
Martin Roth a606598150 ati/ragexl: Change .h #defines named CONFIG_ to CFG_
The CONFIG_ prefix should be reserved for Kconfig symbols.

Change-Id: I1d3141e0f5f9e1161bc7f88158af8a5d5780829c
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12564
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
2015-12-10 16:46:23 +01:00
Martin Roth f79062f478 soc/mediatek/mt8173: SPI_ATOMIC_SEQUENCING depends on SPI_FLASH
Don't select SPI_ATOMIC_SEQUENCING unless SPI_FLASH is being used.

warning: (... SOC_MEDIATEK_MT8173) selects SPI_ATOMIC_SEQUENCING
which has unmet direct dependencies (SPI_FLASH)

Change-Id: I93e9a7102d1d0ef62565110b5b3b677da8d0c72b
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12657
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-10 16:37:05 +01:00
Martin Roth ae1bab3c9d emulation/qemu-arm7: Fix Kconfig symbols for stage compilers
These had typos ARM_STAGE_ARM7 instead of ARCH_STAGE_ARM7

Change-Id: Iffe8fecb3e52a50ff02b774478a10c353093688b
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12660
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-10 16:36:04 +01:00
Martin Roth 3e41ee9847 ACPI: Fix IASL Warning about unused method for _S3 check
According to the ACPI Spec for CondRefOf, the result argument is
optional.  In all of these locations, it was getting set but not
used, creating a warning in new versions of IASL.  Since it's
an optional argument, just remove it.

dsdt.aml 640:              If (CondRefOf (\_S3, Local0))
Warning  3144 - Method Local is set but never used ^  (Local0)

Change-Id: I758d198c33e585a6a4ad2c1c70f2370a01af5138
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12693
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-10 16:32:56 +01:00
Martin Roth f77516cb6d ACPI: Work around IASL warning reading/writing same register
The newer versions of IASL are unhappy when an operator
has the same object as both source and destination.

The warning can be completely disabled with a command
line argument, but in general, I'd really rather not
just disable warnings.

The bits in this register are write 1 to clear, so reading and
writing the same register is what we want to do.  Instead, store
it in a temporary register then write it in a second operation.

Fixes warning:
dsdt.aml   1396:  Store(PWST, PWST)
Warning  3023 -                 ^ Duplicate value in list
(Source is the same as Target)

Change-Id: I52d73d4431db237be83016d67cd397f31b53d9c6
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12691
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-10 16:32:21 +01:00
Martin Roth 91d9cbc2fb ACPI: Fix IASL Warning about unused method for _OSI check
According to the ACPI Spec for CondRefOf, the result argument is
optional.  In all of these locations, it was getting set but not
used, creating a warning in new versions of IASL.  Since it's
an optional argument, just remove it.

dsdt.aml     22:   if(CondRefOf(\_OSI,Local1))
Warning  3144 -                           ^
Method Local is set but never used (Local1)

Change-Id: I07f49ac5a3708838d1c4a7216dfb11acc415c881
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12692
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-10 16:31:35 +01:00
Martin Roth 5a98bf2c0a ACPI: Fix IASL Warning about unused method for _TZ checks
According to the ACPI Spec for CondRefOf, the result argument is
optional.  In all of these locations, it was getting set but not
used, creating a warning in new versions of IASL.  Since it's
an optional argument, just remove it.

dsdt.aml 640:              If (CondRefOf (^GBUF, Local0)) {
Warning  3144 - Method Local is set but never used ^  (Local0)

Change-Id: Iddf46a4faab19019882847917397eee0614302b9
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12695
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-10 16:31:14 +01:00
Martin Roth 10f7f5044e ACPI: Fix IASL Warning about unused method for GBUF check
According to the ACPI Spec for CondRefOf, the result argument is
optional.  In all of these locations, it was getting set but not
used, creating a warning in new versions of IASL.  Since it's
an optional argument, just remove it.

dsdt.aml 640:              If (CondRefOf (^GBUF, Local0)) {
Warning  3144 - Method Local is set but never used ^  (Local0)

Change-Id: Ie2f46808e92c309a63ba7661bcbd77402a08366a
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12694
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-10 16:30:50 +01:00
Ben Gardner fad2313400 intel/fsp_baytrail: Remove code for nonexistant BBAR
The BBAR register (BIOS Base Address Configuration Register) defined in
the ICH9 datasheet does not exist in the Bay Trail E3800 datasheet.
Accessing it seems harmless, but should likely be avoided.

Change-Id: I5d9a6a1ccead84c8996796f516a2bdc5f248cfef
Signed-off-by: Ben Gardner <gardner.ben@gmail.com>
Reviewed-on: https://review.coreboot.org/12671
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-12-10 08:25:47 +01:00
Aaron Durbin 7e7a4df580 lib: remove assets infrastructure
Now that only CBFS access is supported for finding resources
within the boot media the assets infrastructure can be removed.
Remove it.

BUG=chromium:445938
BRANCH=None
TEST=Built and ran on glados.

Change-Id: I383fd6579280cf9cfe5a18c2851baf74cad004e9
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12690
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-10 04:44:09 +01:00
Aaron Durbin 6d720f38e0 cbfs/vboot: remove firmware component support
The Chrome OS verified boot path supported multiple CBFS
instances in the boot media as well as stand-alone assets
sitting in each vboot RW slot. Remove the support for the
stand-alone assets and always use CBFS accesses as the
way to retrieve data.

This is implemented by adding a cbfs_locator object which
is queried for locating the current CBFS. Additionally, it
is also signalled prior to when a program is about to be
loaded by coreboot for the subsequent stage/payload. This
provides the same opportunity as previous for vboot to
hook in and perform its logic.

BUG=chromium:445938
BRANCH=None
TEST=Built and ran on glados.
CQ-DEPEND=CL:307121,CL:31691,CL:31690

Change-Id: I6a3a15feb6edd355d6ec252c36b6f7885b383099
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12689
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-10 04:43:58 +01:00