Increase VBT_DATA_SIZE_KB to 10 since pirrha uses bigger VBT file.
It includes MIPI power sequence data for panel.
BUG=b:295112773
BRANCH=nissa
TEST=FW_NAME=pirrha emerge-nissa coreboot
Change-Id: Ib6c293ccb4a8df3ebbd2271e7db2de4e7bd9cc3e
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77163
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add a limited config for starbook/adl so that Jenkins will build
test it, and specifically, ramtop.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Idcfa45532835a6d89b167fa498b5023b62db0f0a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75386
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
BUG=b:292134655
BRANCH=nissa
TEST=Boot to OS on pirrha ADV board
Change-Id: I65429ec8d30b4458511f7c0138652528aadfde25
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76892
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Implement support for elan i2c touchscreen and use fw_config
to pick between i2c or HID-over-i2c touchscreen.
BUG=b:294456574
BRANCH=firmware-nissa-15217.B
TEST=build and verified touchscreen work
Change-Id: I32ba97f5e5f6d280d1ae47da22360fde421a26c0
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77104
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
The docker-shell target was originally intended to point at the
docker-jenkins-node image, and was documented as such. It was actually
split into two targets - docker-shell and docker-jenkins-shell.
This fixes the documentation for docker-shell and adds new help
for docker-jenkins-shell. The docker-jenkins-shell target is also
noted as phoney now.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ib3ce82f6a73a2f81e5ae51ce8063ae4e59ef67db
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76854
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Now that all of the makefiles under the src tree have SPDX headers,
add that expectation to the license header lint tool by removing
the exception for Makefile.inc.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Iab9d3262621af09a1c625378ae2e61e8a736cdf8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76952
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
This makefile had a 3-clause BSD license. Swap the full license text with an SPDX header.
Looking through the history determined that it had copyright lines,
so those were added back as the license required.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I53a746de6d2e6b60c41415531b7f261e02908b28
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77151
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Crawford <tcrawford@system76.com>
Update DPTF thermal settings from thermal team suggestion:
1. Modify CPU passive policy to 95.
2. Modify TS0/TS1/TS2 passive policy to 90 for CPU.
3. Modify TS1 passtve policy watt to 6w.
4. Modify TS0/TS1/TS2 critical policy to 100.
BUG=b:294479707
TEST=Build and verify DPTF value by thermal team on Boxy system
Change-Id: Ic34e44f218ff980c54bf93841880fab5e21b3fca
Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77108
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Instead of open coding this, use the mmio_range helper function to tell
the resource allocator about the northbridge's IOAPIC's MMIO. This
change sets the IORESOURCE_RESERVE and IORESOURCE_STORED bits in the
resource flags that weren't set before, but mmio_range is already used
elsewhere for similar purposes.
TEST=None
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id66a73cdb22fd551e4359914ba5513313dcc3193
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77173
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Disable NULL breakpoints in setup_realmode_idt before calling
write_idt_stub in a loop.
TEST=No more spurious Null dereference errors in the console output.
Before Mandolin showed these two errors before running the VBIOS:
[ERROR] Null dereference at eip: 0x4e6f1a35
[ERROR] Null dereference at eip: 0x4e6f1a4f
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I2255d85030e41192ae8a3a7f0f6576c0d373eead
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77172
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Instead of open coding the same functionality, use fixed_io_range_flags
to tell the resource allocator about the FCH subtractively decoding the
first 0x1000 bytes of I/O space. Also update the comment to match the
code.
TEST=On Mandolin the flags of this resource stay the same (0xc0040100).
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia30a87a4e37c98248568476b74af2730a3c0e88d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77170
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The resource allocator's setup_resource_ranges will make sure that the
memory resources are 4KiB-aligned. The resource allocator doesn't
enforce any alignment requirements on IO regions.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I3c148ce2acbe284b40126e331d8f372839817e73
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77167
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use get_iohc_fabric_id() to translate the coreboot domain's number into
the destination data fabric ID of the PCI root. This allows using the
coreboot domain 0 as primary domain of the SoC in all cases, so it's
still possible to use config_of_soc(). This allows dropping the
SOC_AMD_COMMON_BLOCK_DATA_FABRIC_DOMAIN_MULTI_PCI_ROOT Kconfig option
and do the check if the destination fabric ID in the PCI bus number,
MMIO, and IO decode registers is the correct one for the domain without
the need to use a non-zero number for the primary PCI root domain.
TEST=Mandolin still boots and the PCI bus, IO and MMIO resources still
get reported correctly.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I880ee0bf5c185cfe4af7de0d39581eb951ee603a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77169
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Implement get_iohc_fabric_id for each SoC that translates the coreboot
domain number to the fabric ID of the corresponding PCI root. This
allows the primary domain to have the number 0 even though the
destination data fabric ID will be non-zero. Keeping the primary domain
number 0 allows to use config_of_soc() which can be resolved at link
time and not need to dynamically find the SoC device to get the config.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I6538a777619eed974b449fc70d3fe3084ba447dd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77168
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
To help identify the licenses of the various files contained in the
coreboot source, we've added SPDX headers to the top of all of the
.c and .h files. This extends that practice to Makefiles.
Any file in the coreboot project without a specific license is bound
to the license of the overall coreboot project, GPL Version 2.
This patch adds the GPL V2 license identifier to the top of all
makefiles in the commonlib, console, northbridge, security, and
southbridge directories that don't already have an SPDX license line
at the top.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I02804a10d0b0355e41271a035613d9f3dfb122f8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68985
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Rewrite them to more accurately describe what they are about.
Change-Id: Icb0ac1e592b662bbb81da431ff97af1a00f952c0
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47429
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
In the case of SoCs hat have more than one PCI root, we need to check to
which PCI root the PCI bus number, IO and MMIO regions configured in the
data fabric registers get routed to and only tell the resource allocator
about the resources that get routed to the current PCI root domain. For
this the numbers of the domains need to match the PCI root's destination
data fabric ID.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib6a6412f733d321044678d2b064c33418a53861c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77113
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Intel Platform Service Record (PSR) provides on-platform persistent and
tamper resistant ledgers and counters.
Key events captured within the Intel PSR Event Ledger, e.g., Chassis
Intrusion Detection, can be observed over the life cycle of the platform
to help assess confidence.
Counters for platform S0 operational use and power state transitions can
be assessed to aid in the determination of general wear or correlations
of other platform events when determining platform decommission plans
(repurpose, resell, recycle).
PSR data is created and stored in CSE data partition. In platforms that
employ CSE Lite SKU firmware, a firmware downgrade involves clearing of
CSE data partition which results in PSR data being lost.
CSE Lite SKU firmware supports a command to backup PSR data before
initiating a firmware downgrade. Add a config to support this PSR data
backup flow.
BRANCH=None
BUG=b:273207144
Change-Id: Iad1ce2906177081c103ef4d4bcef78fa2c95026f
Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com>
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77068
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
With this change TPERST_HIGH could met spec.
Before
160ms
After
460ms(met spec min=400ms)
BUG=b:295277868
TEST=emerge coreboot
EE measured power sequence met spec
boot to system and check wifi connection is fine
Change-Id: Ifb909a55b36f2366132c3e20021c4bde4bc87a05
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77117
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
This adds a missing prerequisite, because otherwise it can happen that
curl tries to put the downloaded kernel in a non existing build
directory
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I459172f794ab9c1010cebcff5e28f1454e136fba
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76914
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Allows cbmem console log and timestamps to be read from Windows.
TEST=build/boot Win11 on google/eve, read cbmem log
Change-Id: I545ce43d4337dd71afedda6bc9208a8c3bf158ee
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77139
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Based on contents from coreboot wiki[1], this patch adds much needed
documentation for the very important abuild utility.
On top of what was there:
- Mainboard targets have been updated
- Added example for building one variant of one board
- Added example for building boards selectively and/or with custom
configurations using --skip_set/--skip_unset, -K, and config files
[1] https://www.coreboot.org/Abuild
Change-Id: I69701eaeef616828bc30736aba2f617e844a3148
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76775
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
The data fabric also controls which PCI bus numbers get decoded to the
PCI root. In order for the resource allocator to know how the hardware
is configured, read the corresponding data fabric registers to get the
information that then gets passed to the allocator.
Picasso, Cezanne, Mendocino and Rembrandt only support one PCI segment
with 256 buses while the Phoenix and Glinda data fabric hardware has
support for more PCI segments. Due to this change, the register layout
is different and incompatible between those two, so introduce the
SOC_AMD_COMMON_BLOCK_DATA_FABRIC_MULTI_PCI_SEGMENT Kconfig option for a
SoC to specify which implementation is needed. At the moment, coreboot
doesn't have support for multiple PCI segments and the code doesn't
support PCI segments other than segment 0.
On Picasso the PCI bus number limit read back from the data fabric
register is 255 even though CONFIG_ECAM_MMCONF_BUS_NUMBER is set to 64,
so also make sure that the bus and limit returned by
data_fabric_get_pci_bus_numbers is within the expected limits.
TEST=PCI bus allocation still works on Mandolin (Picasso) and Birman
(Phoenix). Picasso has 64 PCI buses. coreboot puts this info into the
resource producer in _SB\PCI0\_CRS which the Linux kernel reads:
* coreboot: PCI0 _CRS: adding busses [0-3f]
* Linux: pci_bus 0000:00: root bus resource [bus 00-3f]
This matches the information in the ACPI MCFG table.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ide5fa9b3e95cfd59232048910cc8feacb6dbdb94
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77080
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The fixed I/O resource descriptor macro implies that the device will
only decode 10 of the 16 IO port bits causing aliasing. Use an I/O port
descriptor instead and use Decode16 to tell the OS that this I/O
resource will decode all I/O address bits.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I2df260cea6f12f5a3a6cbae3c7b99bab244a556b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77066
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
The fixed I/O resource descriptor macro implies that the device will
only decode 10 of the 16 IO port bits causing aliasing. Use an I/O port
descriptor instead and use Decode16 to tell the OS that this I/O
resource will decode all I/O address bits.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I6183d625fb7968fb33caf396f19feef8917ba4fe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77065
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
The SOC_AMD_REMBRANDT_BASE comment at the end of Glinda's Kconfig is
probably a leftover from the Mendocino/Rembrandt SoC this file was
copied from. Change it to SOC_AMD_GLINDA to match the corresponding
'if SOC_AMD_GLINDA' in the file.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I85132e4840c1bc713cfc2f3493f800d66edd10ff
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77121
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested using `edk2` from
`github.com/starlabsltd/edk2/tree/uefipayload_vs`:
* Windows 11
* Ubuntu 22.04
* Manjaro 22
No known issues.
https://starlabs.systems/pages/starbook-specification
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I7c92bf92ab4de546c3633fae7e19a302409508ce
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74444
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Neither Windows nor mainline Linux make use of IOSF on the Braswell
platform, so adjust the ACPI status return value based on
CONFIG(CHROMEOS) to prevent an unknown device being listed in Windows
device manager.
TEST=build/boot Win11, Linux 6.2 on google/edgar
Change-Id: Ic51624ffd816d48c007c13d510601cf8cbf1edc4
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77142
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Neither Windows nor mainline Linux make use of IOSF on the Baytrail
platform, so adjust the ACPI status return value based on
CONFIG(CHROMEOS) to prevent an unknown device being listed in Windows
device manager.
TEST=build/boot Win11, Linux 6.2 on google/swanky
Change-Id: I249028c57cc704955cf5a11e2088780ef58e16cf
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77141
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Neither Windows nor mainline Linux make use of DPTF on the Baytrail
platform, so guard its inclusion with CONFIG(CHROMEOS) to prevent an
unknown device being listed in Windows device manager.
TEST=build/boot Win11, Linux 6.2 on google/swanky
Change-Id: Ifc4d349691b647fe2d70c92bd20d1b1128b1e10a
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77140
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
VBOOT_CBFS_INTEGRATION needs board_reset in its logic. Otherwise, it
will cause a build failure.
BUG=b:294643742
TEST=build coreboot
Change-Id: Ia4b81d8add71e62707f6b5a747d270caba502174
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77118
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
After enabling VBOOT_CBFS_INTEGRATION, bootblock exceeds allocated size
(60K) by 3.5K. Since TPM and EC won't be accessed in bootblock, we move
I2C and SPI initializaion to verstage to reduce bootblock size. The GSC
interrupt pin configuration is also moved to verstage to save more
spaces for bootblock.
The size of bootblock.raw.bin is reduced from 64,040 bytes to 60,808
bytes.
BUG=b:294643742
TEST=boot to kernel
Change-Id: I5f6855d5a1a0fce6e739d44652c88e406f6f7b89
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77107
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Set the ACPI device status to hidden, since no driver is necessary or
available under Windows.
Linux is unaffected as it does not use the ACPI device status.
TEST=build/boot Win11 on google/akemi
Change-Id: Ib1e274084400fa47e483267d331e632ceb5be757
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75178
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
If the variable `mirror_flag_attempts` isn't accessible, or doesn't
have a value, don't attempt to mirror the EC.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ia39b2ce4ffcb8db3a335449c8bdb0d5c8a28a52c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76581
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
The EC should be mirrored (if it's out of date) unconditionally if
the board support Thunderbolt. Use DRIVERS_INTEL_USB4_RETIMER instead
of SOC_INTEL_COMMON_BLOCK_TCSS as it's more suitable.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I27b238d4d404746c9a70bacf8e60d9e0b0e1ccca
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76579
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This variant was inadvertently missed when upstreaming other rambi
variants, so add it here for completeness. Add ACPI for the light
sensor to common code to match all other i2c devices.
Sourced from downstream Google branch firmware-expresso-5216.223.B,
commit 6f4073c0e8c8 ("baytrail: implement baytrail technical advisory
556192").
Change-Id: Ia507f95f6af85344e1ab8452f7b3c2cc61526699
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76950
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Set the maximum subordinate bus number of the domain to the last PCI bus
number that is decoded to this PCI root. This makes sure that the
resource allocator knows the maximum number of PCI buses on this PCI
root to not assign bus numbers to buses below this PCI root that aren't
routed to that PCI root.
Now that we have this info in the link list structure or the domain
device, we can pass the max_subordinate field to the
acpigen_resource_producer_bus_number call and can leave the subordinate
number after pci_domain_scan_bus is done unchanged instead of setting it
to the limit.
TEST=On Mandolin both the bus resource producer in _SB\PCI0\_CRS and the
PCI bus number allocation remain unchanged.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I2ee75b2a7054a306b0c7d98c5357391c029187bb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77112
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch adds the ability to show a pre-boot splash screen on
Meteor Lake systems using FSP-S.
The patch calls into `fsp_convert_bmp_to_gop_blt()` when the
`BMP_LOGO` config is enabled. This function converts a BMP
file to a BLT buffer, which is then used by FSP-S to render the splash
screen.
Additionally, increase the heap size (malloc'able size) upto 512KB
(when BMP_LOGO config is enabled) to accommodate high
resolution logo file.
BUG=b:284799726
TEST=Able to see pre-boot splash screen while booting google/rex.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I3608bfacc21574e12cde0e2012a16e6388ce54df
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76922
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
This patch adds an API to convert BMP images into GOP BLT buffers for
Intel FSP-S. This is required to display the OEM splash screen at
pre-boot phase.
Previously, Intel FSP-S had provision to consume the *.BMP file as is.
However, starting with the Alder Lake platform, Intel FSP has dropped
this conversion logic and expects the boot firmware to pass the BLT
buffer directly.
This patch implements the conversion logic in coreboot.
BUG=b:284799726
TEST=Able to build and boot google/rex
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I992b45d65374f09498ff0cab497f7091e1e7a350
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76921
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Seunghwan Kim