Commit Graph

18193 Commits

Author SHA1 Message Date
Furquan Shaikh e7f35cd292 ifwitool: Do not calculate checksum for subpart_dir
1. The checksum method that was documented is not correct. So, no use
filling in a value based on wrong calculations. This can be added back
once updated information is available.
2. Checksum does not seem to affect the booting up of SoC. So, fill in 0
for now.

Change-Id: I0e49ac8e0e04abb6d7c9be70323612bdef309975
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15145
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-06-12 12:45:25 +02:00
Furquan Shaikh fe42b11cdf ifwitool: Correct pack order and header order
Update pack and header order and mark the entries as mandatory and
recommended w.r.t. ordering (mandatory = essential for booting,
recommended = okay to change, but this config is tested and known to work).

Change-Id: Ia089bdaa0703de830bb9553130caf91a3665d2c4
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15144
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-06-12 12:44:23 +02:00
Jonathan Neuschäfer d15e9aaa48 riscv-spike: Replace custom UART with a memory-mapped 8250
Since the HTIF is a non-standard interface, and coreboot already has a
8250 driver, I started implementing an 8250 core for spike[1].

[1]: https://github.com/riscv/riscv-isa-sim/pull/53

Change-Id: I84adc1169474baa8cc5837358a8ad3d184cfa51b
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/15150
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-06-12 12:43:37 +02:00
Jonathan Neuschäfer 1282b8d996 arch/riscv: Compile with -mcmodel=medany
In the default (medlow) code model, pointers are loaded with a lui, addi
instruction sequence:

	lui	a0, 0xNNNNN
	addi	a0, a0, 0xNNN

Since lui sign-extends bits 32-63 from bit 31 on RV64, lui/addi can't
load pointers just above 0x80000000, where RISC-V's RAM now lives.

The medany code model gets around this restriction by loading pointers
trough auipc and addi:

	auipc	a0, 0xNNNNN
	addi	a0, a0, 0xNNN

This way, any pointer within the current pc ±2G can be loaded, which is
by far sufficient for coreboot.

Change-Id: I77350d9218a687284c1337d987765553cf915a22
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/15148
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-06-12 12:42:32 +02:00
Jonathan Neuschäfer f934efc9f8 arch/riscv: Add misc.c to bootblock/romstage to get udelay()
The uart8250mem driver needs it.

Change-Id: I09e6a17cedf8a4045f008f5a0d225055d745e8db
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/15147
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-06-12 12:41:48 +02:00
Jonathan Neuschäfer a9067c6ec0 arch/riscv: copy read/write8/16/32 from x86
Change-Id: I12de8f82499074f0fbbc1c09210b00c6a9614c1b
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/15146
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-06-12 12:40:51 +02:00
Jonathan Neuschäfer 4ac82401a8 arch/riscv/trap_util.S: Use "li" pseudo-instruction to load a constant
Change-Id: I9759771fa6fc708d7d97509c5f5e0cefb8ab4c96
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/14962
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-06-12 12:31:06 +02:00
Furquan Shaikh 6f762171de intel/apollolake: Use custom reset calls
Due to USB LDO issue in current steppings, cold reboot needs to be
temporarily disabled. Thus, hard_reset call should be the same as
soft_reset.

Once future steppings are available INTEL_COMMON_RESET can be enabled again.

Change-Id: If0ec56db3864d500acc93d2b363a78a6cd7632da
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15143
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-12 12:30:15 +02:00
Lee Leahy 061e0fb9ac Documentation/Intel/Board: Update the Galileo checklist
Update the Galileo board implementation checklist.

TEST=Build and run on Galileo Gen2

Change-Id: I1c88e9500d304273a3176d8b034a805920aab9bb
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15137
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-06-12 12:28:57 +02:00
Chris Ching 5343b1fc27 autoport: Add prompt for enabling unsafe inteltool glx option
Change-Id: Ib674ab7ca8b6464de553a86536b1762fda98d94e
Signed-off-by: Chris Ching <chingcodes@google.com>
Reviewed-on: https://review.coreboot.org/14901
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-06-12 12:27:57 +02:00
Patrick Rudolph bb9c90a207 nb/intel: Factor out common MRC code
Remove code duplication and use the common function
store_current_mrc_cache instead.
No functionality is changed.

Tested on Sandybridge Lenovo T520.

Change-Id: I4aa5463f1b1d5e1afbe44b4bfc659524d86204db
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/15074
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2016-06-12 12:27:32 +02:00
Lin Huang 70e03fea5b rockchip: rk3399: pass board specific message to BL31
Sometimes we need to pass board specific messages to BL31,
so that BL31 can do board specific operation based on
common code.

BRANCH=None
BUG=chrome-os-partner:51924
TEST=Build gru

Change-Id: I096878699c6e6933debdf2fb3423734f538691ae
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: af83e1b
Original-Change-Id: Ib7585ce7d3bf01d3ce53b388bf9bd60f3b65f5f1
Original-Signed-off-by: Lin Huang <hl@rock-chips.com>
Original-Signed-off-by: Douglas Anderson <dianders@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/349700
Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://review.coreboot.org/15116
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-12 12:14:36 +02:00
Martin Roth 75ced9a123 3rdparty/arm-trusted-firmware: Update to Jun 8, 2016 master
90 patches pulled in.

Change-Id: I3b893957cbd330e71d0f218262e768f577df4c66
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/15122
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-12 12:14:06 +02:00
PH Hsu cf6526c211 mt8173: dram: Add more sample points to improve dram timing margin
BRANCH=none
BUG=chrome-os-partner:52959
TEST=verified on elm-EVT SKU1/SKU2, Oak-rev5 2GB/4GB models.

Change-Id: I228c629d9a3d6cd8fc5c4e8ba24cc52d5283b4e6
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: 3c19e7d
Original-Change-Id: I22356aa8d196c4c126742cfc7e85cc693acd9b39
Original-Signed-off-by: PH Hsu <ph.hsu@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/347716
Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com>
Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/15115
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-12 12:13:10 +02:00
Julius Werner 99f065fb6e oak: Select VBOOT_EC_SLOW_UPDATE Kconfig option
All current Oak boards have PD chips with update speeds that range from
slow (Oak) to "OMG it's so awfully slow I could make a cup of coffee and
it would still not be done" (Elm). Set the flag that enables the "Your
system is applying a critical update. Please don't turn it off." message
on EC software sync so that our users don't accidentally carry it back
to the store and demand a refund while it's still not done booting.

BRANCH=None
BUG=chrome-os-partner:51145
TEST=Booted Oak in normal mode with a new EC-RW image. Confirmed that I
saw the magic screen.

Change-Id: I000eab36d26b61b25d1f0da505f02ced15457255
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: 274644b
Original-Change-Id: I64ba698985d5fbcf2b94115df72b70a5319106ac
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/348787
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/15114
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-12 12:12:31 +02:00
Julius Werner 0a0f9c5d68 Kconfig: Set VBOOT_OPROM_MATTERS for relevant non-x86 devices
The VBOOT_OPROM_MATTERS configuration option signals to vboot that the
board can skip display initialization in the normal boot path. It's name
is a left-over from a time when this could only happen by avoiding
loading the VGA option ROM on x86 devices. Now we have other
boards that can skip their native display initialization paths too, and
the effect to vboot is the same. (Really, we should rename oprom_matters
and oprom_loaded to display_skippable and display_initialized or
something, but I don't think that's worth the amount of repositories
this would need to touch.)

The only effect this still has in today's vboot is to reboot and
explicitly request display initialization for EC software sync on
VBOOT_EC_SLOW_UPDATE devices (which we haven't had yet on ARM). Still,
the vboot flag just declares the capability (for skipping display init),
and it should be set correctly regardless of whether that actually makes
a difference on a given platform (right now). This patch updates all
boards/SoCs that have a conditional path based on
display_init_required() accordingly.

BRANCH=None
BUG=chrome-os-partner:51145
TEST=Booted Oak, confirmed that there's no notable boot time impact.

Change-Id: Ic7c77dbd8356d67af7aee54e7869f9ac35241b99
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: 9c242f7
Original-Change-Id: I75e5cdda2ba2d111ea50ed2c7cdf94322679f1cd
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/348786
Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/15113
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-12 12:11:08 +02:00
Liangfeng Wu 76655cb82c rockchip: gru: Add USB DRD DWC3 controller support
This patch adds code to initialize the two DWC3 USB
host controllers, and uses them to initialize USB3.0
on the gru rk3399 board.

BRANCH=none
BUG=chrome-os-partner:52684
TEST=boot from USB3.0 on gru/kevin rk3399 platform

Change-Id: If6a6e56f3a7c7ce8e8b098634cfc2f250a91810d
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: 0306a9e
Original-Change-Id: I796fa1133510876f75873d134ea752e1b52e40a8
Original-Signed-off-by: Liangfeng Wu <wulf@rock-chips.com>
Original-Signed-off-by: Douglas Anderson <dianders@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/347524
Original-Commit-Ready: Brian Norris <briannorris@chromium.org>
Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/15112
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-12 12:10:22 +02:00
Liangfeng Wu 8c7e416309 libpayload: usb: xhci: Support rockchip xHCI controller
1. Make the xHCI driver to support xHCI controller v1.1
2. And a new function xhci_ring_doorbell(), it aims to
   add a memory barrier before ringing the doorbell, to ensure
   all TRB changes are written to memory.

BRANCH=none
BUG=chrome-os-partner:52684
TEST=boot from USB on Kevin rk3399 platform

Change-Id: Ife1070d1265476d0f5b88e2acf3299fc84af5832
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: 0c21e92
Original-Change-Id: I4e38e04dc3c7d32ee4bb424a473c70956a3c3ea9
Original-Signed-off-by: Liangfeng Wu <wulf@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/346831
Original-Commit-Ready: Brian Norris <briannorris@chromium.org>
Original-Tested-by: Douglas Anderson <dianders@chromium.org>
Original-Reviewed-by: Douglas Anderson <dianders@chromium.org>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/15111
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-06-12 12:09:55 +02:00
Lee Leahy 2030d257d1 arch/x86: Support "weak" BIST and timestamp save routines
Not all x86 architectures support the mm register set.  The default
routine that saves BIST in mm0 and a "weak" routine that saves the TSC
value in mm2:mm1.  Select the Kconfig value
BOOTBLOCK_SAVE_BIST_AND_TIMESTAMP to provide a replacement routine to
save the BIST and timestamp values.

TEST=Build and run on Amenia and Galileo Gen2.

Change-Id: I8119e74664ac3522c011767d424d441cd62545ce
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15126
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-11 19:22:42 +02:00
Lee Leahy db601b6818 mainboard/intel/galileo: Support bootblock in C
Initialize the GPIOs during the boot block to properly route the SOC
UART pins.

TEST=Build and run on Galileo Gen2

Change-Id: I22c24f8c83f04566a0bbd598a141a5209569a924
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15133
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-11 19:17:49 +02:00
Lee Leahy d131ea3078 arch/x86: Add debug spinloops in assembly_entry.S
Use Kconfig values to enable debug spinloops in assembly_entry.S.  This
makes it easy to debug the assembly code.

TEST=Build and run on Galileo Gen2

Change-Id: Ic56bf2260b8e3181403623961874c9289f3ca945
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15135
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-11 19:16:21 +02:00
Lee Leahy fdc8c8b5fa arch/x86: Add debug spinloop
Conditionally add a debug spinloop to enable easy connection of JTAG
debuggers.

TEST=Build and run on Galileo Gen2 with a JTAG debugger.

Change-Id: I7a21f9e6bfb10912d06ce48447c61202553630d0
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15127
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-11 19:14:55 +02:00
Brandon Breitenstein 3790a42003 Revert "soc/intel/apollolake: Do not use StackBase FSP-M parameter"
This reverts commit 5ede3d8cce.
No longer needed due to FSP being updated, with the 139_40 release,
to accept StackBase field

BUG=chrome-os-partner:52784
BRANCH=none
TEST=built and booted with FSP 139_40

Change-Id: Ic832d8dc4ca87631f5fef80d4d41558d9a72630a
Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com>
Reviewed-on: https://review.coreboot.org/15068
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-10 03:43:14 +02:00
Brandon Breitenstein 47d4f7cec3 soc/intel/apollolake: FSP Header file update for FSP 139_40
FSP 2.0 spec has updated the signatures for the FSPM and FSPS blobs
with the 139_40 release. In order to successfully pass through
memory/silicon init the header files must be updated to the latest
versions

BUG=chrome-os-partner:52784
BRANCH=none
TEST=built and booted

Change-Id: Ib60d0d9afa4ee29dff26177826ba59db81b630e8
Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com>
Reviewed-on: https://review.coreboot.org/15066
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2016-06-10 03:42:38 +02:00
Lee Leahy c9bf8bfabf util/checklist: Add bootblock support
Scan the boot block when building it with C_ENVIRONMENT_BOOTBLOCK
selected.

TEST=Build and run with Galileo Gen2

Change-Id: I922f761c31e95efde0975d8572c47084b91b2879
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15130
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-06-09 23:10:40 +02:00
Lee Leahy 9048384def vendorcode/intel/fsp1_1/checklist: romstage - Add car_stage_entry
Add car_stage_entry as an optional routine in the checklist.

TEST=Build and run on Galileo Gen2

Change-Id: I52f6aefc2566beac01373dbebf3a43d35032a0df
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15129
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-06-09 22:50:00 +02:00
Lee Leahy 6735871531 mainboard: Support ROM_SIZE > 16 MiB
Support ROM_SIZE greater than 16 MiB.  Work around SMBIOS rom size
limitation of 16 MiB by specifying 16 MiB as the ROM size.

TEST=Build and run on neoncity

Change-Id: I3f464599cd8a1b6482db8b9deab03126c8b92128
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15108
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2016-06-09 22:45:51 +02:00
Bora Guvendik de4b09fa26 soc/intel/apollolake: Update FSP header files
Update autogenerated FSP 2.0 generic header files
based on FSP release 136_30.
Changes were made to avoid duplicating some of the
structs for every SoC.

BUG=chrome-os-partner:50765
TEST=Build coreboot

Change-Id: I6f3c9270fb67210d6ea87e17ccf52d203fa64b4b
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://chromium.devtools.intel.com/7145
Reviewed-by: Petrov, Andrey <andrey.petrov@intel.com>
Tested-by: Petrov, Andrey <andrey.petrov@intel.com>
Reviewed-on: https://chromium.devtools.intel.com/7584
Reviewed-on: https://review.coreboot.org/15081
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-09 20:25:58 +02:00
Zhao, Lijian 1a718642ea intel/amenia: Program EMMC dll setting
EMMC TX DATA Control needs to be programmed to 0x1A1A to make amenia
system can run stable on EMMC with HS400 mode.

Change-Id: I42c23ff7e6956e75de5e1b1339a570b35d999301
Signed-off-by: Zhao, Lijian <lijian.zhao@intel.com>
Tested-by: Petrov, Andrey <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/15092
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-09 20:23:50 +02:00
Zhao, Lijian 1b8ee0b88a soc/intel/apollolake: Add EMMC DLL API
Starting from 136_30,FSP supports to update all the SDIO DLL 
programming value through silicon init upd. Implement the interface 
to pass board specific programming value to fsp silicon init.

Change-Id: Ifd901148f3f7f89f966217491c661ec346337c38
Signed-off-by: Zhao, Lijian <lijian.zhao@intel.com>
Reviewed-on: https://chromium.devtools.intel.com/7372
Reviewed-by: Petrov, Andrey <andrey.petrov@intel.com>
Tested-by: Petrov, Andrey <andrey.petrov@intel.com>
Reviewed-on: https://chromium.devtools.intel.com/7585
Reviewed-on: https://review.coreboot.org/15084
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-09 20:23:28 +02:00
Duncan Laurie 4001f244ad skylake: Support common LPSS I2C driver
Support the common Intel LPSS I2C driver for the 6 I2C bus controllers
that are present on the Skylake-LP PCH with a 120 mHz clock.  The
required lpss_i2c_base_address() method is implemented separately for
verstage/romstage and ramstage environments.

This provides methods to convert to and from "struct device" and the
I2C controller bus number for that device.  These are used to provide
support for the "I2C Bus Operations" that are present in the coreboot
devicetree.

To support the I2C controller before ramstage an early init function
is provided to do minimal initializaiton of the PCI device and assign
a temporary base address for use before memory.  The final base
address is assigned during device enumeration and used during ramstage.

Because it is usually not necessary to enable I2C controllers before
ramstage a config register for the devicetree is provided to perform
early initialization of this controller.  In addition the bus speed
can be set in the devicetree and that speed will be applied when the
device is initialized.  If not provided the default speed is set to
I2C_SPEED_FAST.

This was tested with the google/chell mainboard by reading and writing
from the trackpad and codec devices during both verstage and ramstage.

Change-Id: Ia0270adfaf2843a3be4e00c732c85401a3401ef5
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/15105
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2016-06-09 18:40:02 +02:00
Lee Leahy 7a29cdcc0f lib: Build reg_script for bootblock
Allow reg_script to be used during the bootblock.

TEST=Build and run on Galileo Gen2

Change-Id: I55fe0be3f50116927b801ce67a3f23bb1931f6e7
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15131
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-09 17:43:53 +02:00
Lee Leahy 3892597349 arch/x86: Enable SSE in bootblock_crt0.S
Don't write reserved bits in the Quark platform.  Follow the previous
boot behavior and just enable SSE.

TEST=Build and run on Galileo Gen2

Change-Id: Ib3143eff02b2610b595bd666c10d70e43103ccda
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15128
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-09 17:42:12 +02:00
Lee Leahy 538b324c5f lib: Add asmlinkage attribute to bootblock_main_with_timestamp
Add asmlinkage to bootblock_main_with_timestamp so that it may be called
directly from the assembly code.

TEST=Build for Amenia and Galileo Gen2

Change-Id: Iefb8e5c1ddce2ec495b9272966b595d5adcebc1c
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15125
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-09 17:15:35 +02:00
Duncan Laurie c8d45ac88e skylake: Move I2C bus configuration to separate structure
Move the existing I2C voltage configuration variable into a new
structure that is equivalent, similar to how USB ports are configured.

This is to make room for additional I2C configuration options like
bus speed and whether to enable the bus in early boot which are coming
in a subsequent commit.

The affected mainboards are updated in this commit so it will build.

Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Change-Id: Id2dea3df93e49000d60ddc66eb35d06cca6dd47e
Reviewed-on: https://review.coreboot.org/15104
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-06-09 17:08:33 +02:00
Duncan Laurie 7f3156dad6 skylake: gpio: Add support for setting 1.8V tolerant
Add the voltage tolerance GPIO attribute for configuring I2C/I2S buses
that are at 1.8V.  This is currently done by passing in a value to FSP
but it is needed earlier than FSP if the I2C bus is used in verstage.

This does not remove the need for the FSP input parameter, that is
still required so FSP doesn't disable what has been set in coreboot.
The mainboards that are affected are updated in this commit.

This was tested by exercising I2C transactions to the 1.8V codec while
in verstage on the google/chell mainboard.

Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Change-Id: I93d22c2e3bc0617c87f03c37a8746e22a112cc9c
Reviewed-on: https://review.coreboot.org/15103
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2016-06-09 17:07:26 +02:00
Duncan Laurie 205ed2d2b5 skylake: Add function to set PRR for protecting flash
Add a function similar to broadwell to set the PRR for a region of
flash and protect it from writes.  This is used to secure the MRC
cache region if the SPI is write protected.

BUG=chrome-os-partner:54003
BRANCH=glados
TEST=boot on chell, verify PRR register is set and that the
MRC cache region cannot be written if the SPI is write protected.

Change-Id: I925ec9ce186f7adac327bca9c96255325b7f54ec
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Commit-Id: abb6f645f5ceef3f52bb7afd2632212ea916ff8d
Original-Change-Id: I2f90556a217b35b7c93645e41a1fcfe8070c53da
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/349274
Original-Reviewed-by: Shawn N <shawnn@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-on: https://review.coreboot.org/15102
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-06-09 17:06:58 +02:00
Duncan Laurie 8a14c39ac6 soc/intel/common: Add LPSS I2C driver
Add a generic LPSS I2C driver for Intel SOCs that use the Synopsys
DesignWare I2C block and have a similar configuration of that block.

This driver is ported from the Chromium depthcharge project where it
was ported from U-Boot originally, though it looks very different now.
From depthcharge it has been modified to fit into the coreboot I2C
driver model with platform_i2c_transfer() and use coreboot semantics
throughout including the stopwatch API for timeouts.

In order for this shared driver to work the SOC must:

1) Define CONFIG_SOC_INTEL_COMMON_LPSS_I2C_CLOCK_MHZ to set the clock
speed that the I2C controller core is running at.

2) Define the lpss_i2c_base_address() function to return the base
address for the specified bus.  This could be either done by looking
up the PCI device or a static table if the controllers are not PCI
devices and just have a static base address.

The driver is usable in verstage/romstage/ramstage, though it does
require early initialization of the controller to set a temporary base
address if it is used outside of ramstage.

This has been tested on Broadwell and Skylake SOCs in both pre-RAM and
ramstage environments by reading and writing both single bytes across
multiple segments as well as large blocks of data at once and with
different configured bus speeds.

While it does need specific configuration for each SOC this driver
should be able to work on all Intel SOCs currently in src/soc/intel.

Change-Id: Ibe492e53c45edb1d1745ec75e1ff66004081717e
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/15101
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-09 17:06:05 +02:00
Duncan Laurie ec00968f08 device: i2c: Add support for I2C bus operations
In order to support doing bus operations on an I2C device that is
described in the devicetree there needs to be some linkage of the
device and the existing opaque I2C controller bus number.

This is provided in a similar fashion to the existing SMBUS operations
but modified to fit within the existing I2C infrastructure.

Variants of the existing I2C helper functions are provided that will
obtain the bus number that corresponds to this device by looking for
the SOC-provided I2C bus operation structure to provide a function
that will make that translation.

For example an SOC using a PCI I2C controller at 0:15.0 could use:

soc/intel/.../i2c.c:
  static int i2c_dev_to_bus(struct device *dev)
  {
    if (dev->path.pci.devfn == PCI_DEVFN(0x15, 0))
      return 0;
    return -1;
  }
  static struct i2c_bus_operation i2c_bus_ops = {
    .dev_to_bus = &i2c_dev_to_bus
  }
  static struct device_operations i2c_dev_ops = {
    .ops_i2c_bus = &i2c_bus_ops
    ...
  }

With an I2C device on that bus at address 0x1a described in the tree:

devicetree.cb:
  device pci 15.0 on # I2C0
    chip drivers/i2c/sample
      device i2c 1a.0 on end
    end
  end

That driver can then do I2C transactions with the device object
without needing to know that the SOC-specific bus number that this
I2C device lives on is "0".

For example it could read a version value from register address 0
with a byte transaction:

drivers/i2c/sample/sample.c:
  static void i2c_sample_enable(struct device *dev)
  {
    uint8_t ver;
    if (!i2c_dev_readb(dev, 0x00, &ver))
      printk(BIOS_INFO, "I2C %s version 0x02x\n", dev_path(dev), ver);
  }

Change-Id: I6c41c8e0d10caabe01cc41da96382074de40e91e
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/15100
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-09 17:05:40 +02:00
Lee Leahy 72179fad42 soc/intel/quark: Pass serial port address to FSP
Pass the serial port address to FSP using a UPD value in the MemoryInit
API.

TEST=Build and run on Galileo Gen2

Change-Id: I86449d80310b7b34ac503ebd2671a4052b080730
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15079
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-06-09 17:02:26 +02:00
Xing Zheng 96fbc31027 rockchip: rk3399: Add support i2s
This patch enable and configure the clocks and IOMUX for i2s audio path,
and the i2s0 clock is from CPLL.

Please refer to TRM V0.3 Part 1 Chapter 3 CRU, P126/P128/P144/P154/P155
for the i2s clock div and gate setting.

BRANCH=none
BUG=chrome-os-partner:52172
TEST=boot kevin rev1, press ctrl+u and hear the beep voice.

Change-Id: Id00baac965c8b9213270ba5516e1ca684e4304a6
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: 9c58fa7
Original-Change-Id: I130a874a0400712317e5e7a8b3b10a6f04586f68
Original-Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/347526
Original-Commit-Ready: Wonjoon Lee <woojoo.lee@samsung.com>
Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://review.coreboot.org/15034
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-08 23:27:01 +02:00
Vadim Bendebury 8f8cf4d336 gru: kevin: enable EC SPI interface
This configures and enables SPI interface #5 used for EC
communications on Gru/Kevin.

BRANCH=none
BUG=chrome-os-partner:51537
TEST=with the appropriate depthcharge change it is possible to trigger
     booting Chrome OS from the SD card by pressing '^U' on Gru
     keyboard at the right time.

Change-Id: I5304bf47e030c0b9b7794752f30ffdca6c03a4f4
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: b5cc177
Original-Change-Id: I99883daa60562ccddfaeb858c1957d497f05a501
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/346632
Reviewed-on: https://review.coreboot.org/15032
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-08 23:22:54 +02:00
Vadim Bendebury 9ed93cb5d5 gru: kevin: configure board GPIOs
Set board GPIOs as required and add their description into the
appropriate section of the coreboot table, to make them available to
depthcharge.

BRANCH=none
BUG=chrome-os-partner:51537
TEST=with the rest of the patches applied it is possible to use
     keyboard on Gru, which indicates that the EC interrupt GPIO is
     properly configured. The rest of the pins will be verified later.

Change-Id: I5818bfe855f4e7faa2114484a9b7b44c7d469727
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: e02a05f
Original-Change-Id: I82be76bbd3211179e696526a34cc842cb1987e69
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/346631
Reviewed-on: https://review.coreboot.org/15031
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-08 23:21:55 +02:00
Julius Werner 221fdd8cce veyron: Add exception_init() to romstage
I'm not even sure how this slipped through... looks like it had never
been there in the first place. Anyway, on ARM exceptions should always
be reinitialized in all stages to make sure the handlers are still
around (especially in an OVERLAP_VERSTAGE_ROMSTAGE board like this one).

Change-Id: Ic74ea1448d63b363f2ed59d9e2529971b3d32d9a
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/15099
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-06-08 23:21:18 +02:00
Vadim Bendebury 5554d1cf8a rk3399: add ability to configure SPI5
This defines mux settings for the GPIO bank responsible for SPI
interface #5.

BRANCH=none
BUG=chrome-os-partner:51537
TEST=with the rest of the patches applied it is possible to
     communicate with the EC on gru: pressing Ctrl-U during boot
     allows to start Chrome OS from the SD card.

Change-Id: Ibc2293b5662892f7b275434f9a672ef68edf4f9e
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: 4f92452
Original-Change-Id: Idf55c069b05492f8cdc204a8c273e39a19a3aef3
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/346630
Original-Tested-by: Shunqian Zheng <zhengsq@rock-chips.com>
Reviewed-on: https://review.coreboot.org/15030
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-08 23:20:18 +02:00
Vadim Bendebury 993dbe1fc8 gru: kevin: define GPIOs used on both platforms
The same GPIOs are used on both platforms, definitions are added an a
new .h to make it easier to re-use them across the code.

BRANCH=none
BUG=chrome-os-partner:51537
TEST=panel backlight still enabled on Gru as before. The rest of the
     GPIOs are used in the upcoming patches.

Change-Id: If06f4b33720ab4bf098d23fb91322bba23fe6e90
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: c587880
Original-Change-Id: I1a6c5b5beb82ffcc5fea397e8e9ec2f183f4a7e0
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/346219
Original-Tested-by: Shunqian Zheng <zhengsq@rock-chips.com>
Reviewed-on: https://review.coreboot.org/15029
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-08 23:19:32 +02:00
Stefan Tauner 37fcd58ba6 inteltool: handle unsafe dumping of graphics registers
The current implementation from Vladimir simply dumps 1 MB of memory
contents starting at the base address of the second PCI device (which
most likely is the VGA controller on Intel systems). This locks up a
number of different systems, e.g. my Ibex Peak-based T410s.

This patch documents the issue and stops dumping the graphics registers
for the -a/--all parameter.

Change-Id: I581bdc63db60afaf4792bc11fbeed73aab57f63a
Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at>
Reviewed-on: https://review.coreboot.org/14627
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2016-06-08 22:35:57 +02:00
Alexandru Gagniuc 6a587343a9 drivers/intel/fsp2.0: Add semantic patch for FspUpdVpd.h header
Previous FSP implementations in coreboot have included FspUpdVpd.h
directly, along with with efi headers. Instead of taking that
approach in FSP 2.0, we provide a semantic patch that, with minimal
modifications, makes FspUpdVpd.h easier to include in coreboot, and
eliminates reliance on external headers and definitions.

Change-Id: I0c2a6f7baf6fb50ae22b64e08e653cfe1aefdaf9
Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com>
Reviewed-on: https://review.coreboot.org/13331
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-08 22:35:18 +02:00
Hannah Williams 0f61da8582 soc/apollolake: Add SOC specific c-state table
Please refer Apollolake BIOS Writers Guide

Change-Id: I5f82cdc4b34a53b5184ef1e918cae15a1df6cc5e
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/15051
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-06-08 22:31:27 +02:00
Hannah Williams f8daa37861 soc/intel/common: Add common code for acpi c/p/t-state entries
Change-Id: I87505bb31cd1b46d27cc5c9ba8d086df7393653e
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/15050
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-08 22:30:58 +02:00