Commit Graph

4004 Commits

Author SHA1 Message Date
Maxim Polyakov 0a6f82835e util/intelp2m: Check keywords in common code
TEST = ./intelp2m -n -file inteltool.log;
       ./intelp2m -fld cb -file inteltool.log;
       ./intelp2m -fld fsp -file inteltool.log;
       ./intelp2m -fld raw -file inteltool.log.
       Before and after the patch, gpio.h is no different.

Change-Id: I8af28960e41fcb97f03fe97c42cdddde07b3615a
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45167
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-09-21 08:07:26 +00:00
Michael Niewöhner e0d749c23b lint: check for misuse of Kconfig SUBSYSTEM_*_ID
Check that nobody misuses the Kconfigs SUBSYSTEM_*_ID. They are meant to
be used for overriding the devicetree subsystem ids locally but shall
not be added to a board's Kconfig. Instead, the devicetree option
`subsystemid` should be used.

Add a linter script for this that finds and warns about such misuse.

Also add a note in the Kconfigs' description.

TEST=CB:45513

Change-Id: I21c021c718154f1396f795a555af47a76d6efe03
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45513
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-09-20 17:03:32 +00:00
Duncan Laurie cbd0bd8155 sconfig: Add function for parse+override of tree
Extract the steps to parse and override a devicetree into a function
so it can be used multiple times without copying the same logic.

Change-Id: I4e496a223757beb22e3bd678eb6115968bd32529
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44036
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2020-09-18 22:41:56 +00:00
Duncan Laurie 51c8373593 sconfig: Switch to getopt
Instead of positional arguments switch sconfig to use getopt and pass
the arguments as options in the build system.  This will make it easier
to add additional options.

Change-Id: I431633781e80362e086c000b7108191b5b01aa9d
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44035
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-18 17:50:00 +00:00
Yilin Yang 46eaa5a1ba util/rockchip: Port make_idb.py to python3
BUG=chromium:1023662
TEST=buildbot pass
TEST=1. Use python2 script
     2. Run `emerge-kevin coreboot` twice, so we get bootblock.bin.1
     and bootblock.bin.2
     3. Run `xxd` on these two bootblock so we get bootblock.bin.1.hex
     and bootblock.bin.2.hex
     4. `diff bootblock.bin.1.hex bootblock.bin.2.hex` and record the
     difference. (at least, the time info changes)
     5. Migrate to python3
     6. Similar steps, we get bootblock.bin.py3.hex
     7. `diff bootblock.bin.1.hex bootblock.bin.py3.hex`, the difference
     is similar. (time info, git hash changes)

Signed-off-by: Yilin Yang <kerker@google.com>
Change-Id: I04253084ec9b65310c52598b629390051cd2172b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45447
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-18 13:30:05 +00:00
Yilin Yang 1502494cba util/exynos: Port *_cksum.py to python3
BUG=chromium:1023662
TEST=1. Create a tiny file `in.txt` as input
     2. Run `fixed_cksum.py in.txt out.txt 20` with py2 and py3 version,
     the output is the same
     3. Run `variable_cksum.py in.txt out.txt` with py2 and py3 version,
     the output is the same

Signed-off-by: Yilin Yang <kerker@google.com>
Change-Id: I9428269dfb826a3a95fffef9ea3f7c1a7107ef84
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45460
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-09-18 08:00:39 +00:00
Yilin Yang f944e619dd util/mtkheader: Port gen-bl-img.py to python3
BUG=chromium:1023662
TEST=1. Use python2 script
     2. Run `emerge-asurada coreboot` twice, so we get bootblock.bin.1
     and bootblock.bin.2
     3. Run `xxd` on these two bootblock so we get bootblock.bin.1.hex
     and bootblock.bin.2.hex
     4. `diff bootblock.bin.1.hex bootblock.bin.2.hex` and record the
     difference. (at least, the time info changes)
     5. Migrate to python3
     6. Similar steps, we get bootblock.bin.py3.hex
     7. `diff bootblock.bin.1.hex bootblock.bin.py3.hex`, the difference
     is similar.

Signed-off-by: Yilin Yang <kerker@google.com>
Change-Id: I788e7c9b09257142728a0f76df8c2ccc72bf6b3b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45440
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-09-18 08:00:22 +00:00
Masanori Ogino 33f64b5d78 crossgcc: Fix libcpp to address -Wformat-security
On some systems where the system compiler enables `-Wformat-security
-Werror=format-security` options by default, building libcpp fails
because the code passes a variable directly as a format string.

This change addresses this problem by patching the affected code.

Tested with the default compiler of Nixpkgs unstable, GCC 9.3.0 with the
options described above enabled by default.

Signed-off-by: Masanori Ogino <mogino@acm.org>
Change-Id: Ibf3c9e79ce10cd400c9f7ea40dd6de1ab81b50e2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45311
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-14 07:11:59 +00:00
Jacob Garber 07201d7a0f coreinfo: Use SPDX license identifiers
- Remove copyright notices and add authors to AUTHORS
- Use SPDX license identifiers for all files
- Add coreinfo to the license header lint

Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Change-Id: Ib0c5328a4027849b1eda4f57141a898335230726
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45178
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-14 07:05:27 +00:00
Martin Roth 1ba86f685b utils/docker/coreboot-sdk: Update python to python2, add python3
The latest debian image needs the python2 package specified instead of
just 'python'.  Also add python3 to the builder as we'll probably be
getting python3 scripts before too long.

Change-Id: Iceea3981b1e219141bf06ad0b559cdbf1c98b360
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45265
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-09-13 23:14:16 +00:00
Nico Huber 8e1ea525d1 sconfig: Allow to link devices to other device's drivers
Rarely, the driver of one device needs to know about another device
that can be anywhere in the device hierarchy. Current applications
boil down to EEPROMs that store information that is consumed by some
code (e.g. MAC address).

The idea is to give device nodes in the `devicetree.cb` an alias that
can later be used to link it to a device driver's `config` structure.
The driver has to declare a field of type `struct device *`, e.g.

    struct some_chip_driver_config {
            DEVTREE_CONST struct device *needed_eeprom;
    };

In the devicetree, the referenced device gets an alias, e.g.

    device i2c 0x50 alias my_eeprom on end

The author of the devicetree is free to choose any alias name that
is unique in the devicetree. Later, when configuring the driver the
alias can be used to link the device with the field of a driver's
config:

    chip some/chip/driver
            use my_eeprom as needed_eeprom
    end

Override devices can add an alias if it does not exist, but cannot
change the alias for a device that already exists.

Alias names are checked for conflicts both in the base tree and in the
override tree.

References are resolved after the tree is parsed so aliases and
references do not need to be in a specific order in the tree.

Change-Id: I058a319f9b968924fbef9485a96c9e3f900a3ee8
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35456
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-11 17:34:01 +00:00
Patrick Georgi 28276fc834 util/abuild: Remove symbols that don't exist anymore in Kconfig
Bayou and OpenBIOS aren't supported by the coreboot build system
anymore, so remove these mentions.

Change-Id: Ibdf6fdc776068041cb468fdbf5b56b06f85c2d4b
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45180
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-10 15:50:27 +00:00
Rob Barnes 97dd498815 util/mb/google: Update dalboz/trembyle template
- Fix relative path to spd folder.
- Add spd folder with empty files.

BUG=None
TEST=None

Change-Id: Iae88ff9c8255f60544312f0eeadf1ce617437baf
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44947
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2020-09-09 10:46:43 +00:00
Rob Barnes ad1da3a326 util/spd_tools: Support comments in mem_parts_used
Allow comments prefixed with '#' in mem_parts_used csv file.

BUG=None
TEST=Run gen_part_id with mem_parts_used file containing comments

Change-Id: Ia9e274d45aa06dea7a3a5f8cd1c8ee2b23398876
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44950
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-09-09 10:46:03 +00:00
Michael Niewöhner f23794cf04 util/spd_tools: output binaries instead of hexdumps
Instead of generating hexdumps, output binary SPD files since we plan to
convert all hex SPD files to binary. Also adjust the file extension
where needed.

Test: compared generated binaries with converted binaries from hex files

Change-Id: Ie99d108ca90758d09dbefad20fe6c9f7fc263ef1
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44878
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-08 05:46:41 +00:00
Michael Niewöhner e10efa3a03 util/apcb_edit: fix handling of binary SPD files
Passing binary SPD files to apcb_edit can lead to an encoding error,
since the files were read in text mode. To fix this, read SPD files
always in binary mode and only decode them, when `--hex` is set.

Tested by comparing output files from the same SPDs in both, binary and
hex mode.

Change-Id: I6b75a9e1234e71667bdc8cb4eb10daf8c0ac3c17
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44778
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-09-08 05:44:28 +00:00
Subrata Banik 60296aec76 util/ifdtool: Add NULL check for pointer fpsba
This patch adds NULL check inside get_ifd_version_from_fcba()
function to fix Klocwork issue.

BUG=b:153888802

Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: I525054376b36c658b93760b185ef6dd170f5aea9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45130
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-09-08 05:37:36 +00:00
Sam McNally 911db1f997 util/mb/google/tmpl/puff: Update DPTF to the new implementation
Apply the change in CB:44905 to the puff template, moving DPTF policies
from static ASL files into the new SSDT-based DPTF implementation.

BUG=b:158986928
BRANCH=puff
TEST=None

Change-Id: I601fd4c6aeaa3afee0f7fd9d13376f2fffd6d793
Signed-off-by: Sam McNally <sammc@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45073
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2020-09-06 23:41:00 +00:00
Patrick Georgi 80370ff991 crossgcc: Ensure that GMP is built for a generic CPU on x86
While GMP supports fat builds on x86 that adapt to the CPU's
capabilities, by default it builds for the CPU of the builder.
Running that binary on an older CPU then can fail.

Change-Id: Iafdc2eb696189b9e2c5ead316f310d98c949ef74
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45044
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-03 18:47:09 +00:00
Martin Roth b1f648fc5c util/amdfwtool: Add PSP verstage signature entry
Add the field for the PSP verstage signature entry.  This adds the
public key signing token to the PSP Directory table to verify the signed
PSP verstage binary

BUG=b:166100797
TEST=Build in a file and verify that it's present with the correct ID.
BRANCH=Zork

Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I7525045d8746b6857979d07b02758ab4d4835026
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44987
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Eric Peers <epeers@google.com>
2020-09-03 16:30:14 +00:00
Martin Roth eca423b44f util/amdfwtool: Fix warning taking address of packed struct member
GCC9 introduced a new warning [-Waddress-of-packed-member].  This
is giving the following warning when building amdfwtool: warning: taking
address of packed member of ‘struct _bios_directory_entry’ may result in
an unaligned pointer value. Looking at the definition of the struct, it
looks like this is probably true.

Since the function being called doesn't read from the values, zeroing
them out in the beginning of the function, the code just passes pointers
to the temporary variables without initializing them.

BUG=None
TEST=Build & use AMD firmware table.
BRANCH=Zork

Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I2f1e0aede8563e39ab0f2ec6daed91d6431eac43
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44986
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Eric Peers <epeers@google.com>
2020-09-03 16:25:40 +00:00
Subrata Banik e5d3992639 util/ifdtool: Fix eSPI frequency as per Gen 11 SPI flash guide
BUG=b:153888802
TEST=Able to list correct eSPI frequency as per TGL SPI flash guide

Without this CL :
Found Component Section
FLCOMP     0x093030f6
  Dual Output Fast Read Support:       not supported
  Read ID/Read Status Clock Frequency: 50MHz
  Write/Erase Clock Frequency:         50MHz
  Fast Read Clock Frequency:           50MHz
  Fast Read Support:                   supported
  Read Clock Frequency:                20MHz

With this CL :
Found Component Section
FLCOMP     0x093030f6
  Dual Output Fast Read Support:       not supported
  Read ID/Read Status Clock Frequency: 50MHz
  Write/Erase Clock Frequency:         50MHz
  Fast Read Clock Frequency:           50MHz
  Fast Read Support:                   supported
  Read eSPI/EC Bus Frequency:          60MHz

Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: I20840e6f931d7c1fabea0b6892e3bd19ead81168
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44820
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-09-02 07:17:44 +00:00
Subrata Banik d16ef4d21e util/ifdtool: Fix SPI frequency as per Gen11 SPI flash guide
BUG=b:153888802
TEST=Able to list correct SPI frequency as per TGL SPI flash guide

Without this CL :
Found Component Section
FLCOMP     0x093030f6
  Dual Output Fast Read Support:       not supported
  Read ID/Read Status Clock Frequency: 33MHz
  Write/Erase Clock Frequency:         33MHz
  Fast Read Clock Frequency:           33MHz
  Fast Read Support:                   supported
  Read Clock Frequency:                20MHz

With this CL :
Found Component Section
FLCOMP     0x093030f6
  Dual Output Fast Read Support:       not supported
  Read ID/Read Status Clock Frequency: 50MHz
  Write/Erase Clock Frequency:         50MHz
  Fast Read Clock Frequency:           50MHz
  Fast Read Support:                   supported
  Read Clock Frequency:                20MHz

Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: Id0a0a0cbd948ef8334cf522c09e881b464e87f0e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44819
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-02 07:17:39 +00:00
Subrata Banik bd2da5a4b5 util/ifdtool: Add FLMAP3 dump for Gen11 onwards PCH
BUG=b:153888802
TEST=Able to dump FLMAP3 for Volteer platform with TGP
> ifdtool -d coreboot.rom

FLMAP3:      0x00000000
  Minor Revision ID:     0x0000
  Major Revision ID:     0x0000

Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: I681abd6ae7b87f6638d4f6dc59168cf22b93c787
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44818
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-02 07:17:33 +00:00
Subrata Banik ac1b1dd83e util/ifdtool: Fix miscellaneous IFD offset since Gen 5 PCH
This patch performs below operations:
1. Remove reserved NR field from Gen 5 onwards SPI programming guide
2. Convert ISL to PSL as applicable for Gen 5 onwards PCH
3. Skip FLMAP2 register dump due to nonuniformity since Gen 5 onwards PCH
4. Dump FLILL1 register as applicable for Gen 5 onwards PCH
5. Remove FLPB register as not applicable since Gen 5 PCH

BUG=b:153888802
TEST=Dump FD for Hatch platform as below
> ifdtool -d coreboot.rom

PCH Revision: 300 series Cannon Point/ 400 series Ice Point
FLMAP0:    0x00040003
  FRBA:    0x40
  NC:      1
  FCBA:    0x30
FLMAP1:    0x45100208
  PSL:     0x45
  FPSBA:   0x100
  NM:      2
  FMBA:    0x80

FLILL1     0xc7c4b9b7
  Invalid Instruction 7: 0xc7
  Invalid Instruction 6: 0xc4
  Invalid Instruction 5: 0xb9
  Invalid Instruction 4: 0xb7

Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: I5141ae5dd174659fde5401fac313a701ae4f8f44
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44817
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-09-02 07:17:25 +00:00
Subrata Banik 26058dca96 util/ifdtool: Identify between ICH and PCH Revision
Consider IBEX_PEAK onwards all chipsets are belong to PCH family.

BUG=b:153888802
TEST=Able to print correct PCH revision on Hatch Platform.
> ifdtool -d coreboot.rom

Without this CL :
ICH Revision: 300 series Cannon Point/ 400 series Ice Point

With this CL :
PCH Revision: 300 series Cannon Point/ 400 series Ice Point

Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: Ifd40dddc9179f347c0ea75149ec08089a829fdb4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44816
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-09-02 07:17:16 +00:00
Subrata Banik 89db2255d0 util/ifdtool: Identify chipset without platform name
Able to uniquely identify the chipset without specifying the platform
specific quirks (adl/cnl/icl/jsl/tgl etc.).

BUG=b:153888802
TEST=Able to dump FD contains correctly without specifying platform
quirks on Hatch Platform.

> ifdtool -d coreboot.rom

Without this CL :
ICH Revision: 100 series Sunrise Point

With this CL :
ICH Revision: 300 series Cannon Point/ 400 series Ice Point

Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: I83763adb721e069343b19a10e503975ffa6abb24
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44815
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-31 06:57:42 +00:00
Subrata Banik d52df3cd84 util/ifdtool: Skip unused and reserved Flash Region
This patch ensures all unused and reserved flash region sections are not
getting listed while using -d option to dump FD.

BUG=b:153888802
TEST=List only used flash region section with below command
> ifdtool -p tgl -d coreboot.rom

Without this CL :
Found Region Section
FLREG0:    0x00000000
  Flash Region 0 (Flash Descriptor): 00000000 - 00000fff
FLREG1:    0x1fff0400
  Flash Region 1 (BIOS): 00400000 - 01ffffff
FLREG2:    0x03ff0001
  Flash Region 2 (Intel ME): 00001000 - 003fffff
FLREG3:    0x00007fff
  Flash Region 3 (GbE): 07fff000 - 00000fff (unused)
FLREG4:    0x00007fff
  Flash Region 4 (Platform Data): 07fff000 - 00000fff (unused)
FLREG5:    0x00007fff
  Flash Region 5 (Reserved): 07fff000 - 00000fff (unused)
FLREG6:    0x00007fff
  Flash Region 6 (Reserved): 07fff000 - 00000fff (unused)
FLREG7:    0x00007fff
  Flash Region 7 (Reserved): 07fff000 - 00000fff (unused)
FLREG8:    0x00007fff
  Flash Region 8 (EC): 07fff000 - 00000fff (unused)

With this CL :
Found Region Section
FLREG0:    0x00000000
  Flash Region 0 (Flash Descriptor): 00000000 - 00000fff
FLREG1:    0x1fff0400
  Flash Region 1 (BIOS): 00400000 - 01ffffff
FLREG2:    0x03ff0001
  Flash Region 2 (Intel ME): 00001000 - 003fffff
FLREG3:    0x00007fff
  Flash Region 3 (GbE): 07fff000 - 00000fff (unused)
FLREG4:    0x00007fff
  Flash Region 4 (Platform Data): 07fff000 - 00000fff (unused)
FLREG8:    0x00007fff
  Flash Region 8 (EC): 07fff000 - 00000fff (unused)

Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: I900a29d8968bd61d66c04012e60e1ba4baff786d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44813
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-08-31 06:57:29 +00:00
Subrata Banik 15da174652 util/ifdtool: Add platform specific quirks for ADL/ICL/JSL/TGL
BUG=b:153888802
TEST=Able to dump FD contain using below command
> ifdtool -p tgl -d coreboot.rom

Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: I0c9106051f4daf592d2467ebf79f9ddb037011dc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44809
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-08-31 06:56:53 +00:00
Elyes HAOUAS 796c567b1c lint/lint-extended-007-checkpatch: Remove obsolete path
Change-Id: I8a91d2a8bc6a1fa709aeadd3b7482d1785068276
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44899
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-08-31 06:40:55 +00:00
Elyes HAOUAS 668132a47c {intel/gma,include/device}: Delete unused 'drm_dp_helper.h' file
'drm_dp_helper.h' file is duplicated and not used.

Change-Id: Ibb08f7ff91c3914940dfe899be331b06e292c7c9
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44842
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-08-31 06:36:18 +00:00
Karthikeyan Ramasubramanian cb5961d148 cross-repo-cherrypick: Do not prepend "Original-" to "Cq-Depend:"
Marking dependencies has undergone some change in Chrome OS tree. The
script to cherry-pick the changes to ChromeOS tree prepends "Original-" to
the concerned meta data i.e. Cq-Depend becomes Original-Cq-Depend. This
causes dependencies to not take effect when changes are submitted to the
continuous integration. Do not prepend "Original-" to the dependency
meta data.

BUG=None
TEST=Ensure that the Cq-Depend line is added without any prefix.

Change-Id: I0503234954f872ee56708e19e89cae9d9fa30df7
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44843
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-08-31 06:33:56 +00:00
Matt DeVillier 62e883d73b util/inteltool: Add support for Comet Lake-U
Add support for 10th-gen/Comet Lake-U based boards:
- add PCI IDs for host bridge, IGD, LPC devices
- add support for dumping GPIOs, PCRs, etc

Tested on an unbranded CML-U board running AMI firmware

Change-Id: I44871917565fc628fd1073a6e5c36b6a3246a61c
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44301
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
2020-08-29 13:41:04 +00:00
Rob Barnes 8283ae6bab util: Add memory parts needed by zork boards
Add memory parts needed by zork boards. Attributes are derived from data
sheets.

BUG=b:162939176
TEST=Compared generated SPDs with data sheets and checked in SPDs

Signed-off-by: Rob Barnes <robbarnes@google.com>
Change-Id: I67f205f9af24bbc5c12656be1f363a15fe975955
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44447
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-28 14:29:44 +00:00
Nick Vaccaro 913ea9278f util/gen_spd: translate DeviceBusWidth to die bus width
If a memory part is a x16 part that has two dies and only a single
rank, then the x16 describes the part width (since this solution will
need to be a stacked solution) and as such, we must translate the
DeviceBusWidth to the "die bus width" instead.

Change DeviceBusWidth variable name to PackageBusWidth to be more
descriptive

BUG=b:166645306, b:160157545
TEST=run gen_spd and verify that spds for parts matching description
above changed appropriately.

Change-Id: Ia6f3ca109d344b7a015da28125a94ce10d2bdfb8
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44870
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-08-28 14:20:30 +00:00
Aaron Durbin 0245f43bcd Revert "util: update lp4x gen_part_id tool to include memory type"
This reverts commit eb7a1dd80e.

MEMORY_TYPE = lines in Makefiles are not longer needed. Drop it.

Change-Id: I96ac39a30555a870e7778a0e71d738407b6b89ef
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44895
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-28 05:01:31 +00:00
Rob Barnes a662648a7f util: Add support to spd_tools for fixed id
For boards that have already assigned memory ids, there needs to be a
way to fix parts to a specific id. After assigning all the fixed ids the
tool still attempts to minimize the SPDs entries. Since a fixed ID could
be anywhere, gaps can be created in the list. So an empty SPD entry is
created to fill the gaps in the list until they are used.

BUG=b:162939176
TEST=Generate various outputs

Signed-off-by: Rob Barnes <robbarnes@google.com>
Change-Id: I1f8ea1ff4f33a97ab28ba94896a1054e89189576
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44463
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2020-08-28 04:36:55 +00:00
Nick Vaccaro 48fc1640a8 util: volteer/dedede: move generic SPDs to common location
Now that generic SPD files have the memory type prepended to the
filename, they can be stored in the same location.  This CL moves
the generic SPDs to the new location.

Change the ddr4 gen_part_id.go and gen_spd.go tools to use
"ddr4_spd_manifest.generated" instead of "spd_manifest.generated".

Change the lpddr4x gen_part_id.go and gen_spd.go tools to use
"lp4x_spd_manifest.generated" instead of "spd_manifest.generated".

Move TGL DDR4 and LPDDR4x generic SPDs into a common location.

Move JSL DDR4 and LPDDR4x generic SPDs into a common location.

Change the volteer/spd/Makefile.inc to use the new path for the spds.

Change the dedede/spd/Makefile.inc to use the new path for the spds.

BUG=b:165854055
TEST="emerge-volteer coreboot" and verify all variants build correctly.

Change-Id: I83b088cb718d15ffd3012c84a12b5231ae84a3e4
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44648
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-28 04:35:56 +00:00
Rob Barnes c19140b49f util: Add check for duplicate entries in mem parts json
Check for duplicate entries in mem parts json file.

BUG=b:162939176
TEST=Verified that tool throws error when there is a duplicate.

Signed-off-by: Rob Barnes <robbarnes@google.com>
Change-Id: I7c638c7938958727cfc832e7b4556acbc04b0ca4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44478
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-27 22:39:32 +00:00
Rob Barnes 8cc80d5e50 util: Add Picasso and Pollock platforms to spd_tools
PCO = Picasso
PLK = Pollock

BUG=b:162939176

Signed-off-by: Rob Barnes <robbarnes@google.com>
Change-Id: I43b74f68871062112f53fbbef8a170db53734b3e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44477
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-27 21:41:30 +00:00
Rob Barnes a2e431331c util/spd_tools: Support comments in json
Allow comments in json file for better documentation. Comments must be
on seperate line.

BUG=none
TEST=Injest global_ddr4_mem_parts.json.txt with comments

Change-Id: I51295408d4f916708e4ed5bc42d5468ccdc68a6b
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44834
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-08-27 21:41:18 +00:00
Rob Barnes 196e9c0021 util/spd_tools: Remove intel subfolder
Move ddr4 and lp4x to spd_tools root folder. The tool now applies to non
intel platforms.

BUG=b:162939176
TEST=Run tool

Signed-off-by: Rob Barnes <robbarnes@google.com>
Change-Id: I0941ea036d760ee27eb34f259f4506a4b7584bee
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44844
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-27 20:14:34 +00:00
Nick Vaccaro eb7a1dd80e util: update lp4x gen_part_id tool to include memory type
Add "MEMORY_TYPE = lp4x" to the generated Makefile.inc to indicate
this is lpddr4x memory and to use the generic SPDs from the lpddr4x
respository of SPDs.

BUG=b:160157545
TEST=run gen_part_id for volteer and verify that it adds the line "MEMORY_TYPE =
lp4x" to the makefile produced.

Change-Id: I416690ae8aff8052474b16ef0d3e940e72e6a2fb
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44647
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-08-25 18:27:59 +00:00
Nick Vaccaro 90aeb4d1b5 util: Add spd_tools to generate DDR4 SPDs for TGL boards
Serial Presence Detect (SPD) data for memory modules is used by Memory
Reference Code (MRC) for training the memory. This SPD data is
typically obtained from part vendors but has to be massaged to format
it correctly as per JEDEC and MRC expectations. There have been
numerous times in the past where the SPD data used is not always
correct.

In order to reduce the manual effort of creating SPDs and generating
DRAM IDs, this change adds tools for generating SPD files for DDR4
memory used in memory down configurations on Intel Tiger Lake (TGL)
based platforms. These tools generate SPDs following JESD79-4C and
Jedec "4.1.2.L-5 R29 v103" specification.

Two tools are provided:
* gen_spd.go: Generates de-duplicated SPD files using a global memory
  part list provided by the mainboard in JSON format. Additionally,
  generates a SPD manifest file (in CSV format) with information about
  what memory part from the global list uses which of the generated
  SPD files.

* gen_part_id.go: Allocates DRAM strap IDs for different DDR4
  memory parts used by the board. Takes as input list of memory parts
  used by the board (with one memory part on each line) and the SPD
  manifest file generated by gen_spd.go. Generates Makefile.inc for
  integrating the generated SPD files in the coreboot build.

BUG=b:160157545

Change-Id: I263f936b332520753a6791c8d892fc148cb6f103
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44429
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-08-25 16:48:02 +00:00
Elyes HAOUAS 9618706da6 crossgcc: Upgrade MPC to version 1.2.0
Change-Id: I8b754c2bbb18e38d2f8619f6ac8e1544702836ee
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44551
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-24 09:13:44 +00:00
Patrick Georgi 0d431acf6c util/abuild: Don't pass kconfig output through head
Closing stdout early seems to have a detrimental effect on kconfig on a
system under high load (e.g. when doing lots of builds in parallel).

Change-Id: I6987f1deac596124c7b397bf7bc5a78d691cc538
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44625
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2020-08-24 09:08:21 +00:00
Patrick Georgi c01a49fb3f util/abuild: Delete temporary config in failure case
Change-Id: I9b6e6b6dcfbf2b1f43c98027acae8d9af61bd6d8
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44624
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-24 09:06:42 +00:00
Martin Roth 48dd9fe21f util/amdfwtool: Refactor APOB_NV requirements
amdfwtool currently assumes that we MUST have an apob_nv area if we
have an aopb.  This is not required, so if neither the apob_nv size or
base are specified, just move on.

BUG=b:158363448
TEST=Build an image with no APOB_NV region.  Dump regions to show that
it's not there.

Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: Ibaeacd3dcdfd73f690df61c2a19d39bbb9dcc838
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44045
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-21 18:46:58 +00:00
Patrick Georgi 942c199341 util/abuild: Avoid another git submodule invocation
.xcompile is generated before the submodules handling, but there's no
need for the submodules to be around, so skip here, too.

Change-Id: I60205f65b124a09067de5ae50f066b5cf64733f2
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44550
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2020-08-19 20:21:33 +00:00
Elyes HAOUAS 8f1853c4b0 crossgcc: Upgrade LLVM to version 10.0.1
Change-Id: I1d96654fd66a5972c6c5cc24311ca2d889866331
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39921
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-18 13:50:02 +00:00